Datasheet BQ2202SNTR, BQ2202SN-NTR, BQ2202SN-N, BQ2202SN, BQ2202PN-N Datasheet (Texas Instruments)

Features

ä

Power monitoring and switching
for nonvolatile control of SRAMs

ä

Write-protect control

ä

Input decoder allows control of
up to 2 banks of SRAM

ä

3-volt primary cell input

ä

3-volt rechargeable battery in­put/output

ä

Reset output for system power-on
reset

ä

Less than 10ns chip enable
propagation delay

ä

5% or 10% supply operation

General Description

The CMOS bq2202 SRAM Nonvolatile
Controller With Reset provides all the
necessary functions for converting one
or two banks of standard CMOS
SRAM into nonvolatile read/write
memory.

A precision comparator monitors the
5V V

CC

input for an out-of-tolerance
condition. When out-of-tolerance is
detected, the two conditioned
chip-enable outputs are forced inac­tive to write-protect both banks of
SRAM.

Power for the external SRAMs is
switched from the VCCsupply to the
battery-backup supply as VCCde­cays. On a subsequent power--up, the
V

OUT

supply is automatically
switched from the backup supply to
the VCCsupply. The external SRAMs
are write-protected until a power­valid condition exists. The reset out­put provides power-fail and power-on
resets for the system.

During power-valid operation, the
input decoder selects one of two
banks of SRAM.

1

Pin Names

V

OUT

Supply output

RST

Reset output
THS Threshold select input
CE

Chip enable active low input
CE

CON1

, Conditioned chip enable outputs

CE

CON2

A Bank select input
BC

P

3V backup supply input
BC

S

3V rechargeable backup supply input/output
NC No connect
V

CC

+5 volt supply input
V

SS

Ground

Two banks of CMOS static RAM can be battery-backed
using the V

OUT

and conditioned chip-enable output pins
from the bq2202. As the voltage input VCCslews down
during a power failure, the two conditioned chip enable
outputs, CE

CON1

and CE

CON2

, are forced inactive

independent of the chip enable input CE.
This activity unconditionally write-protects external

SRAM as V

CC

falls to an out-of-tolerance threshold

V

PFD.VPFD

is selected by the threshold select input pin,
THS. If THS is tied to VSS, the power-fail detection oc­curs at 4.62V typical for 5% supply operation.

If THS is tied to V

CC

, power-fail detection occurs at

4.37V typical for 10% supply operation. The THS pin
must be tied to VSSor VCCfor proper operation.

If a memory access is in process to any of the two exter­nal banks of SRAM during power-fail detection, that
memory cycle continues to completion before the memory
is write-protected. If the memory cycle is not terminated
within time t

WPT

(150µsec maximum), the two chip en­able outputs are unconditionally driven high, write­protecting the controlled SRAMs.

SRAM NV Controller With Reset

bq2202

Sept. 1997D

1

PN220201.eps

16-Pin Narrow DIP or SOIC

2

3

4

5

6

7
8

16

15

14

13

12

11

10

9

V

CC

BC

S
CE

CE

CON1
CE

CON2
NC

RST
NC

V

OUT
BC

P

NC

A

NC

NC

THS
V

SS

Functional Description

Pin Connections

As the supply continues to fall past V

PFD

, an internal

switching device forces V

OUT

to the internal backup en-

ergy source. CE

CON1

and CE

CON2

are held high by the

V

OUT

energy source.

During power-up, V

OUT

is switched back to the 5V sup­ply as VCCrises above the backup cell input voltage
sourcing V

OUT

. Outputs CE

CON1

and CE

CON2

are held

inactive for time t

CER

(120ms maximum) after the

power supply has reached V

PFD

, independent of the CE

input,toallowforprocessorstabilization.
During power-valid operation, the CE

input is passed

through to one of the two CE

CON

outputs with a propa­gation delay of less than 10ns. The CE input is output on
one of the two CE

CON

output pins; depending on the
level of bank select input A, as shown in the Truth Ta­ble.

Bank select input A is usually tied to a high-order ad­dress pin so that a large nonvolatile memory can be de­signed using lower-density memory devices.Nonvolatility
and decoding are achieved by hardware hookup as shown
in Figure 1.

The reset output (RST) goes active within t

PFD

(150µsec

maximum) after V

PFD,

and remains active for a minimum
of 40ms (120ms maximum) after power returns valid. The
RST output can be used as the power-on reset for a micro­processor . Access to the external RAM may begin when
RST returns inactive.

Energy Cell Inputs—BCP,BC

S

Two backup energy source inputs are provided on the
bq2202—a primary cell BC

P

and a secondary cell BCS.
The primary cell input is designed to accept any 3V pri­mary battery (non-rechargeable), typically some type of
lithium chemistry.If a primary cell is not to be used, the
BCPpin should be grounded. The secondary cell input
BCSis designed to accept constant-voltage current­limited rechargeable cells.

During normal 5V power valid operation, 3.3V is output
on the BC

S

pin and is current-limited internally.

2

FG220201.eps

V

CC

CE
BC

P

THS
V

SS

V

OUT

bq2202

V

CC

CE

CMOS
SRAM

5V

From Address

Decoder

CE

CON2

BC

S

RST

CE

CON1

A

V

CC

CE

CMOS
SRAM

To Microprocessor

Figure 1. Hardware Hookup (5% Supply Operation)

Sept. 1997D

bq2202

If a secondary cell is not to be used, the BCSpin must be
tied directly to VSS. If both inputs are used, during
power failure the V

OUT

and CE

CON

outputs are forced

high by the secondary cell so long as it is greater than

2.5V. Only the secondary cell is loaded by the data reten­tion current of the SRAM until the voltage at the BC

S

pin falls below 2.5V. When and if the voltage at BC

S

falls below 2.5V, an internal isolation switch automati­cally transfers the load from the secondary cell to the
primary cell.

To prevent battery drain when there is no valid data to
retain, V

OUT

,CE

CON1

, and CE

CON2

are internally iso-

lated from BCPand BCSby either:

■

Initial connection of a battery to BCPor BCSor

■

Presentation of an isolation signal on CE.

A valid isolation signal requires CE

low as VCCcrosses

both V

PFD

and VSOduring a power-down. See Figure

2. Between these two points in time, CE must be
brought to V

CC ∗

(0.48 to 0.52) and held for at least

700ns. The isolation signal is invalid if CE exceeds V

CC

*

0.54 at any point between VCCcrossing V

PFD

and VSO.

The battery is connected to V

OUT

,CE

CON1

, and

CE

CON2

immediately on subsequent application and

removal of VCC.

3

TD220201.eps

V

CC

CE

V

PFD

V

SO

0.5 V

CC

700ns

Figure 2. Battery Isolation Signal

Truth Table

Input Output

CE ACE

CON1

CE

CON2

HXHH
LLLH
LHHL

Sept. 1997D

bq2202

4

Recommended DC Operating Conditions (T

A=TOPR

)

Symbol Parameter Minimum Typical Maximum Unit Notes

V

CC

Supply voltage

4.75 5.0 5.5 V THS = V

SS

4.50 5.0 5.5 V THS = V

CC

V

BCP

Backup cell input voltage

2.0 - 4.0
VVCC<V

BC

V

BCS

2.5 - 4.0

V

SS

Supply voltage 0 0 0 V

V

IL

Input low voltage -0.3 - 0.8 V

V

IH

Input high voltage 2.2 - VCC+ 0.3 V

THS Threshold select -0.3 - VCC+ 0.3 V

Note: Typical values indicate operation at TA= 25°C, VCC=5VorVBC.

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions

V

CC

DC voltage applied on VCCrelative to V

SS

-0.3 to +7.0 V

V

T

DC voltage applied on any pin excluding V

CC

relative to V

SS

-0.3 to +7.0 V V

T

≤

V

CC

+ 0.3

T

OPR

Operating temperature

0 to +70 °C Commercial

-40 to +85 °C Industrial “N”

T

STG

Storage temperature -55 to +125 °C

T

BIAS

Temperature under bias -40 to +85 °C

T

SOLDER

Soldering temperature 260 °C For 10 seconds

I

OUT

V

OUT

current 200 mA

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera-

tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Expo­sure to conditions beyond the operational limits for extended periods of time may affect device reliability.

Sept. 1997D

bq2202

5

DC Electrical Characteristics (T

A=TOPR,VCC

=5V±10%)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

I

LI

Input leakage current - -

±

1

µ

AVIN=VSSto V

CC

V

OH

Output high voltage 2.4 - - V IOH= -2.0mA

V

OHB

VOH, backup supply VBC- 0.3 - - V VBC>VCC,IOH= -10µA

V

OL

Output low voltage - - 0.4 V IOL= 4.0mA

I

CC

Operating supply current - 3 6 mA

No load on V

OUT

,CE

CON1

,

and CE

CON2

V

PFD

Power-faildetect voltage

4.55 4.62 4.75 V THS = V

SS

4.30 4.37 4.50 V THS = V

CC

V

SO

Supply switch-over voltage - V

BC

-V

I

CCDR

Data-retention mode
current

- - 100 nA

No load on V

OUT

,CE

CON1

,

and CE

CON2

V

OUT1

V

OUT

voltage

VCC- 0.2 - - V VCC>VBC,I

OUT

= 100mA

V

CC

- 0.3 - - V VCC>VBC,I

OUT

= 160mA

V

OUT2

V

OUT

voltage VBC- 0.2 - - V VCC<VBC,I

OUT

= 100µA

V

BC

Active backup cell voltage

-V

BCS

-VV

BCS

> 2.5V

-V

BCP

-VV

BCS

< 2.5V

R

BCS

BCScharge output internal
resistance

500 1000 1750

Ω

V

BCSO

≥

3.0V

V

BCSO

BCScharge output voltage 3.0 3.3 3.6 V

V

CC>VPFD

, RST inactive,

full charge or no load

I

OUT1

V

OUT

current - - 160 mA V

OUT

≥

V

CC

- 0.3V

I

OUT2

V

OUT

current - 100 -

µ

AV

OUT

≥

V

BC

- 0.2V

Note: Typical values indicate operation at TA= 25°C, VCC=5VorVBC.

Capacitance (T

A

= 25°C, F = 1MHz, VCC= 5.0V)

Symbol Parameter Minimum Typical Maximum Unit Conditions

C

IN

Input capacitance - - 8 pF Input voltage = 0V

C

OUT

Output capacitance - - 10 pF Output voltage = 0V

Note: This parameter is sampled and not 100% tested.

Sept. 1997D

bq2202

6

AC Test Conditions

Parameter Test Conditions

Input pulse levels 0V to 3.0V
Input rise and fall times 5ns
Input and output timing reference levels 1.5V (unless otherwise specified)

FG220102.eps

5V

960

100pF

CE

CON

510

Figure 3. Output Load

Sept. 1997D

Power-Fail Control (T

A=TOPR

)

Symbol Parameter Min. Typ. Max. Unit Conditions

t

PF

VCCslew 4.75 to 4.25V 300 - -

µ

s

t

FS

VCCslew 4.25 V to V

SO

10 - -

µ

s

t

PU

VCCslew 4.25 to 4.75V 0 - -

µ

s

t

CED

Chip-enable propagation delay - 7 10 ns

t

CER

Chip-enable recovery time t

RR

-tRRms

Time during which SRAM is write­protected after VCCpasses V

PFD

on

power-up

t

RR

VPFD to RST inactive 40 80 120 ms

Time, after V

CC

becomes valid, before

RST is cleared

t

AS

Input A set up to CE 0--ns

t

WPT

Write-protect time t

R

-t

R

µ

s

Delay after V

CC

slews down past V

PFD

before SRAM is write-protected

t

R

V

PFD

to RST active 40 100 150µs

Delay after V

CC

slews down past V

PFD

before RST is active

Note: Typical values indicate operation at TA= 25°C, VCC=5V.

bq2202

7

TD220202.eps

V

CC

CE

CON

t

PF

t

FS

4.75
V

PFD

4.25
V

SO

t

WPT

V

OHB

CE

t

R

RST

Power-Down Timing

TD220203.eps

V

CC

t

PU

CE

CE

CON

V

OHB

V

SO

4.25

V

PFD

4.75

t

CER

t

CED

t

CED

RST

t

RR

Power-Up Timing

Sept. 1997D

bq2202

TD220204.eps

CE

CON1

t

AS

CE

CE

CON2

A

t

CED

t

CED

Address-Decode Timing

8

Sept. 1997D

bq2202

16-Pin DIP Narrow

16-Pin DIP Narrow (PN)

Dimension Minimum Maximum

A 0.160 0.180

A1 0.015 0.040

B 0.015 0.022

B1 0.055 0.065

C 0.008 0.013
D 0.740 0.770
E 0.300 0.325

E1 0.230 0.280

e 0.300 0.370
G 0.090 0.110
L 0.115 0.150
S 0.020 0.040

All dimensions are in inches.

16-Pin SOIC Narrow

A

A1

.004

C

B

e

D

E

H

L

16-Pin SOIC Narrow (SN)

Dimension Minimum Maximum

A 0.060 0.070

A1 0.004 0.010

B 0.013 0.020
C 0.007 0.010
D 0.385 0.400
E 0.150 0.160

e 0.045 0.055

H 0.225 0.245
L 0.015 0.035

All dimensions are in inches.

9

bq2202

Sept. 1997D

Ordering Information

bq2202

PackageOption:

PN = 16-pin narrow plastic DIP
SN = 16-pin narrow SOIC

Device:

bq2202 SRAM Nonvolatile Controller WithReset

TemperatureRange:

blank = Commercial (0 to +70°C)
N = Industrial (-40 to +85°C)

Data Sheet Revision History

Change No. Page No. Description Nature of Change

1 2 Deleted last sentence Clarification

15V

BCSO

—BCScharge output voltage

Was: 3.15 min, 3.3 typ, 3.45 max
Is: 3.0 min, 3.3 typ, 3.6 max

25

Changed maximum charge output internal resis­tance (R

BCS

)

Was:1500Ω
Is: 1750Ω

3 1, 4, 5 10% supply operation

Was:THS tied to V

OUT

Is: THS tied to V

CC

Note: Change 1 = Dec. 1992 B changes from Sept. 1991 A.

Change 2 = Nov.1994 C changes from Dec. 1992 B.
Change 3 = Sept. 1997 D changes from Nov.1994 C.

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