Datasheet BQ2201PN-N, BQ2201PN, BQ2201SNTR, BQ2201SN-NTR, BQ2201SN-N Datasheet (Texas Instruments)

Download

Page 1

Features

➤ Power monitoring and switching

for 3-volt battery-backup applications

➤ Write-protect control ➤ 3-volt primary cell inputs ➤ Less than 10ns chip-enable

propagation delay

➤ 5% or 10% supply operation

General Description

The CMOS bq2201 SRAM Nonvolatile Controller Unit provides all necessary functions for converting a standard CMOS SRAM into nonvolatile read/write memory.

A precision comparator monitors the 5V V

input for an out-of-tolerance condition. When out of tolerance is detected, a conditioned chip-enable output is forced inactive to writeprotect any standard CMOS SRAM.

During a power failure, the external SRAM is switched from the V

supply to one of two 3V backup supplies. On a subsequent power-up, the SRAM is write-protected until a power-valid condition exists.

The bq2201 is footprint- and timingcompatible with industry standards with the added benefit of a chip-enable propagation delay of less than 10ns.

SRAM Nonvolatile Controller Unit

bq2201

Oct. 1998 D

Pin Names

OUT

Supply output

BC1—BC23-volt primary backup cell inputs

THS Threshold select input

CE chip-enable active low input

CON

Conditioned chip-enable output

+5-volt supply input

Ground

NC No Connect

Functional Description

Pin Connections

An external CMOS static RAM can be battery-backed using the V

OUT

and the conditioned chip-enable output pin from the bq2201. As VCCslews down during a power failure, the conditioned chip-enable output CE

CON

forced inactive independent of the chip-enable input CE.

This activity unconditionally write-protects external SRAM as V

falls to an out-of-tolerance threshold V

PFD

is selected by the threshold select input pin,THS.

If THS is tied to VSS, power-fail detection occurs at 4.62V typical for 5% supply operation. If THS is tied to VCC, power-fail detection occurs at 4.37V typical for 10% supply operation. The THS pin must be tied to VSSor VCCfor proper operation.

If a memory access is in process during power-fail detection, that memory cycle continues to completion before the memory is write-protected. If the memory cycle is not terminated within time t

WPT

, the CE

CON

output is uncondi-

tionally driven high,write-protecting the memory.

PN220101.eps

8-Pin Narrow DIP or SOIC

CON

OUT

THS

PN2201E.eps

16-Pin SOIC

7 8

CON

NC CE

OUT

THS

Page 2

As the supply continues to fall past V

PFD

, an internal

switching device forces V

OUT

to one of the two external

backup energy sources. CE

CON

is held high by the V

OUT

energy source.

During power-up, V

OUT

is switched back to the VCCsupply as VCCrises above the backup cell input voltage sourcing V

OUT

. The CE

CON

output is held inactive for

time t

CER

(120 ms maximum) after the supply has

reached V

PFD

, independent of the CE input, to allow for

processor stabilization.

During power-valid operation, the CE

input is fed

through to the CE

CON

output with a propagation delay of less than 10ns. Nonvolatility is achieved by hardware hookup, as shown in Figure 1.

Energy CellInputs—BC1,BC

Two primary backup energy source inputs are provided on the bq2201. The BC1and BC2inputs accept a 3V primary battery, typically some type of lithium chemistry. If no primary cell is to be used on either BC1or BC2, the unused input should be tied to VSS.

If both inputs are used, during power failure the V

OUT

output is fed only by BC1as long as it is greater than

2.5V. If the voltage at BC1falls below 2.5V, an internal isolation switch automatically switches V

OUT

from BC

to BC2.

To prevent battery drain when there is no valid data to retain, V

OUT

and CE

CON

are internally isolated from

BC1and BC2by either of the following:

■

Initial connection of a battery to BC1or BC2,or

■

Presentation of an isolation signal on CE.

A valid isolation signal requires CE

low as VCCcrosses

both V

PFD

and VSOduring a power-down. See Figure 2. Between these two points in time, CE must be brought to the point of (0.48 to 0.52)*VCCand held for at least 700ns. The isolation signal is invalid if CE exceeds

0.54*VCCat any point between VCCcrossing V

PFD

and

VSO.

The appropriate battery is connected to V

OUT

and CE

CON

immediately on subsequent application and removal of VCC.

FG220101.eps

CE BC

THS V

OUT

CON

bq2201

CMOS SRAM

From Address Decoder

Primary

Cell

3V Primary Cell

Figure 1. Hardware Hookup (5% Supply Operation)

Oct. 1998 D

TD220101.eps

PFD

0.5 V

700ns

Figure 2. Battery Isolation Signal

bq2201

Page 3

Absolute Maximum Ratings

Symbol Parameter Value Unit Conditions

DC voltage applied on VCCrelative to V

-0.3 to 7.0 V

DC voltage applied on any pin excluding V

relative to V

-0.3 to 7.0 V

≤

+ 0.3

OPR

Operating temperature

0 to +70 °C Commercial

-40 to +85 °C Industrial “N”

STG

Storage temperature -55 to +125 °C

BIAS

Temperature under bias -40 to +85 °C

SOLDER

Soldering temperature 260 °C For 10 seconds

OUT

current 200 mA

Note: Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional opera-

tion should be limited to the Recommended DC Operating Conditions detailed in this data sheet. Exposure to conditions beyond the operational limits for extended periods of time may affect device reliability.

Recommended DC Operating Conditions (T

A=TOPR

)

Symbol Parameter Minimum Typical Maximum Unit Notes

Supply voltage

4.75 5.0 5.5 V THS = V

4.50 5.0 5.5 V THS = V

Supply voltage 0 0 0 V

Input low voltage -0.3 - 0.8 V

Input high voltage 2.2 - VCC+ 0.3 V

BC1

BC2

Backup cell voltage 2.0 - 4.0 V

THS Threshold select -0.3 - V

+ 0.3 V

Note: Typical values indicate operation at TA= 25°C, VCC= 5V or VBC.

Oct. 1998 D

bq2201

Page 4

DC Electrical Characteristics (T

A=TOPR,VCC

= 5V±10%)

Symbol Parameter Minimum Typical Maximum Unit Conditions/Notes

Input leakage current - -

AVIN=VSSto V

Output high voltage 2.4 - - V IOH= -2.0mA

OHB

VOH, BC supply VBC- 0.3 - - V VBC>VCC,IOH= -10µA

Output low voltage - - 0.4 V IOL= 4.0mA

Operating supply current - 3 5 mA No load on V

OUT

and CE

CON

PFD

Power-fail detect voltage

4.55 4.62 4.75 V THS = V

4.30 4.37 4.50 V THS = V

Supply switch-over voltage - V

-V

CCDR

Data-retention mode current

- - 100 nA

OUT

data-retention current to additional memory not included.

OUT1

OUT

voltage

- 0.2 - - V VCC>VBC,I

OUT

= 100mA

- 0.3 - - V VCC>VBC,I

OUT

= 160mA

OUT2

OUT

voltage VBC- 0.3 - - V VCC<VBC,I

OUT

= 100µA

Active backup cell voltage

-V

BC2

-VV

BC1

< 2.5V

-V

BC1

-VV

BC1

> 2.5V

OUT1

OUT

current - - 160 mA V

OUT>VCC

- 0.3V

OUT2

OUT

current - 100 -

OUT>VBC

- 0.2V

Note: Typical values indicate operation at TA= 25°C, VCC= 5V or VBC.

Oct. 1998 D

bq2201

Page 5

AC Test Conditions

Parameter Test Conditions

Input pulse levels 0V to 3.0V

Input rise and fall times 5ns

Input and output timing reference levels 1.5V (unless otherwise specified)

Output load (including scope and jig) See Figure 3

FG220102.eps

960

100pF

CON

510

Figure 3. Output Load

Capacitance (T

= 25°C, F = 1MHz, VCC= 5.0V)

Symbol Parameter Minimum Typical Maximum Unit Conditions

Input capacitance - - 8 pF Input voltage = 0V

OUT

Output capacitance - - 10 pF Output voltage = 0V

Note: This parameter is sampled and not 100% tested.

Oct. 1998 D

bq2201

Page 6

TD220102.eps

CON

4.75 V

PFD

4.25 V

WPT

OHB

Power-Down Timing

Power-Fail Control

(TA = T

OPR

)

Symbol Parameter Minimum Typical Maximum Unit Notes

VCCslew, 4.75V to 4.25V 300 - -

VCCslew, 4.25V to V

10 - -

VCCslew, 4.25V to 4.75V 0 - -

CED

Chip-enable propagation delay

- 7 10 ns

CER

Chip-enable recovery 40 80 120 ms

Time during which SRAM is write-protected after V

passes V

PFD

on power-up.

WPT

Write-protect time 40 100 150

Delay after VCCslews down past V

PFD

before SRAM is

write-protected.

Note: Typical values indicate operation at TA= 25°C.

Caution: Negative undershoots below the absolute maximum rating of -0.3V in battery-backup mode

may affect data integrity.

Oct. 1998 D

bq2201

Page 7

Oct. 1998 D

TD220103.eps

CON

OHB

4.25

PFD

4.75

CER

CED

Power-Up Timing

bq2201

Page 8

Oct. 1998 D

8-Pin SOIC Narrow (SN)

Dimension Minimum Maximum

A 0.060 0.070

A1 0.004 0.010

B 0.013 0.020 C 0.007 0.010 D 0.185 0.200 E 0.150 0.160

e 0.045 0.055 H 0.225 0.245 L 0.015 0.035

All dimensions are in inches.

8-Pin SOIC Narrow (SN)

8-Pin DIP Narrow (PN)

Dimension Minimum Maximum

A 0.160 0.180

A1 0.015 0.040

B 0.015 0.022

B1 0.055 0.065

C 0.008 0.013

D 0.350 0.380

E 0.300 0.325

E1 0.230 0.280

e 0.300 0.370

G 0.090 0.110

L 0.115 0.150 S 0.020 0.040

All dimensions are in inches.

8-Pin DIP Narrow (PN)

bq2201

Page 9

bq2201

Oct. 1998 D

S: 16-Pin SOIC

.004

16-Pin S(SOIC

)

Dimension Minimum Maximum

A 0.095 0.105

A1 0.004 0.012

B 0.013 0.020 C 0.008 0.013 D 0.400 0.415 E 0.290 0.305

e 0.045 0.055

H 0.395 0.415

L 0.020 0.040

All dimensions are in inches.

Page 10

bq2201

Oct. 1998 D

Data Sheet Revision History

Change No. Page No. Description Nature of Change

1 Added industrial temperature range

2 1, 3, 4 10% supply operation

Was: THS tied to V

OUT

Is: THS tied to V

3 1, 9, 11 Added 16-pin package option

Note: Change 1 = Sept. 1991 B changes from Sept. 1990 A.

Change 2 = Aug. 1997 C changes from Sept. 1991 B. Change 3 = Oct. 1998 D changes from Aug. 1997 C.

Page 11

Ordering Information

bq2201

Package Option:

PN = 8-pin narrow plastic DIP SN = 8-pin narrow SOIC S = 16-pin SOIC

Device:

bq2201 Nonvolatile SRAM Controller

Temperature Range:

blank = Commercial (0 to +70°C) N = Industrial (-40 to +85°C)

bq2201

Oct. 1998 D

Page 12

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERSTOOD T O BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.