Datasheet ATA3741, ATA3741P2-TGQY, ATA3741P2-TGSY, ATA3741P3-TGQY, ATA3741P3-TGSY Datasheet (Atmel)

Download

Page 1

Features

• Minimal External Circuitry Requirements, No RF Components on the PC Board Except

Matching to the Receiver Antenna

• High Sensitivity, Especially at Low Data Rates

• Sensitivity Reduction Possible Even While Receiving

• Fully Integrated VCO

• Low Power Consumption Due to Configurable Self Polling with a Programmable Time

Frame Check

• Supply Voltage 4.5V to 5.5V

• Operating Temperature Range –40°C to +105°C

• Single-ended RF Input for Easy Adaptation to λ / 4 Antenna or Printed Antenna on PCB

• Low-cost Solution Due to High Integration Level

• ESD Protection According to MIL-STD. 883 (4 KV HBM) Except Pin POUT (2 KV HBM)

• High Image Frequency Suppression due to 1 MHz IF in Conjunction with a SAW

Front-end Filter

– Up to 40 dB is Thereby Achievable with Newer SAWs

• Programmable Output Port for Sensitivity Selection or for Controlling External

Periphery

• Communication to the Microcontroller Possible via a Single, Bi-directional Data Line

• Power Management (Polling) is also Possible by Means of a Separate Pin via the

Microcontroller

• 2 Different IF Bandwidth Versions are Available (300 kHz and 600 kHz)

UHF ASK Receiver IC

ATA3741

1. Description

The ATA3741 is a multi-chip PLL receiver device supplied in an SO20 package. It has been specially developed for the demands of RF low-cost data transmission systems with low data rates from 1 kBaud to 10 kBaud (1 kBaud to 3.2 kBaud for FSK) in Manchester or Bi-phase code. The receiver is well-suited to operate with Atmel's PLL RF transmitter U2741B. Its main applications are in the areas of telemetering, security technology, and keyless-entry systems. It can be used in the frequency receiving range of f ments made below refer to 433.92-MHz and 315-MHz applications.

= 300 MHz to 450 MHz for ASK or FSK data transmission. All the state-

4899B–RKE–10/06

Page 2

Figure 1-1. System Block Diagram

1 Li cell

Encoder

ATARx9x

Keys

Figure 1-2. Block Diagram

FSK/ASK

CDEM

AVCC

SENS

AGND

DGND

UHF ASK/FSK

Remote control transmitter

U2741B

PLL

XTO

VCO

Power

amp.

FSK/ASK

Demodulator

and data filter

RSSI

IF Amp

Order

Limiter out

Antenna

DEMOD_OUT

Sensitivity reduction

ATR3741

LNA

Polling circuit

and

control logic

FE CLK

UHF ASK/FSK

Remote control receiver

Demod

PLL

VCO

50 kΩ

DATA

ENABLE

TEST

POUT

MODE

DVCC

Control

1...3

Microcontroller

XTO

LPF

MIXVCC

LNAGND

LNA_IN

ATA3741

LNA

3 MHz

IF Amp

LPF

3 MHz

Standby logic

VCO

÷ 64

XTO

LFGND

LFVCC

XTO

4899B–RKE–10/06

Page 3

2. Pin Configuration

Figure 2-1. Pinning SO20

DATA

SENS

FSK/ASK

CDEM

AVCC AGND DGND

MIXVCC

LNAGND

LNA_IN

1 2 3 4 5 6 7 8 9 10

Table 2-1. Pin Description

Pin Symbol Function

1 SENS Sensitivity-control resistor 2 FSK/ASK Selecting FSK/ASK. Low: FSK, High: ASK 3 CDEM Lower cut-off frequency data filter 4 AVCC Analog power supply 5 AGND Analog ground 6 DGND Digital ground 7 MIXVCC Power supply mixer 8 LNAGND High-frequency ground LNA and mixer

9 LNA_IN RF input 10 NC Not connected 11 LFVCC Power supply VCO 12 LF Loop filter 13 LFGND Ground VCO 14 XTO Crystal oscillator 15 DVCC Digital power supply 16 MODE Selecting 433.92 MHz/315 MHz. Low: 4.90625 MHz (USA). High: 6.76438 (Europe) 17 POUT Programmable output port 18 TEST Test pin, during operation at GND

Enables the polling mode

19 ENABLE

20 DATA Data output/configuration input

Low: polling mode off (sleep mode) High: polling mode on (active mode)

20 19 18 17 16 15 14 13 12 11

ENABLE TEST POUT MODE DVCC XTO LFGND LF LFVCC

ATA3741

4899B–RKE–10/06

Page 4

3. RF Front End

The RF front end of the receiver is a heterodyne configuration that converts the input signal into a 1-MHz IF signal. As seen in the block diagram, the front end consists of an LNA (low noise amplifier), LO (local oscillator), a mixer, and an RF amplifier.

The LO generates the carrier frequency for the mixer via a PLL synthesizer. The XTO (crystal oscillator) generates the reference frequency f erates the drive voltage frequency f

for the mixer. fLO is dependent on the voltage at pin LF. f

is divided by a factor of 64. The divided frequency is compared to f

. The VCO (voltage-controlled oscillator) gen-

XTO

by the phase frequency

XTO

detector. The current output of the phase frequency detector is connected to a passive loop filter and thereby generates the control voltage V is controlled in a way that fLO/ 64 is equal to f

for the VCO. By means of that configuration, V

. If fLO is determined, f

XTO

can be calculated

XTO

using the following formula:

XTO

--------=

The XTO is a one-pin oscillator that operates at the series resonance of the quartz crystal. The crystal should be connected to GND via a capacitor CL according to Figure 3-1. The value of the capacitor is recommended by the crystal supplier. The value of CL should be optimized for the individual board layout to achieve the exact value of f

and thereby of fLO. When designing the

XTO

system in terms of receiving bandwidth, the accuracy of the crystal and XTO must be considered.

Figure 3-1. PLL Peripherals

DVCC

XTO

LFGND

R1 = 820Ω C9 = 4.7 n

C10

C10 = 1 nF

= 100 kHz.

Loop

LFVCC

The passive loop filter connected to pin LF is designed for a loop bandwidth of B This value for B

exhibits the best possible noise performance of the LO. Figure 3-1 shows

Loop

the appropriate loop filter components to achieve the desired loop bandwidth. If the filter components are changed for any reason, please note that the maximum capacitive load at pin LF is limited. If the capacitive load is exceeded, a bit check may no longer be possible since f

cannot settle before the bit check starts to evaluate the incoming data stream. Therefore, self polling also will not work .

ATA3741

4899B–RKE–10/06

Page 5

ATA3741

fLO is determined by the RF input frequency fRF and the IF frequency fIF using the following formula:

LOfRFfIF

To determine f frequency is f is tuned by the crystal frequency f f

MODE 0 (USA) f

MODE 1 (Europe) f

The relation is designed to achieve the nominal IF frequency of f tions. For applications where f f

is then dependent on the logical level at pin MODE and on fRF. Table 3-1 summarizes the dif-

–=

, the construction of the IF filter must be considered at this point. The nominal IF

= 1 MHz. To achieve a good accuracy of the filter’s corner frequencies, the filter

. This means that there is a fixed relation between fIF and

XTO

that depends on the logic level at pin mode. This is described by the following formulas:

----------==

314

------------------==

432.92

= 1 MHz for most applica-

= 315 MHz, MODE must be set to “0”. In the case of

= 433.92 MHz, MODE must be set to ”1”. For other RF frequencies, fIF is not equal to 1 MHz.

ferent conditions.

The RF input either from an antenna or from a generator must be transformed to the RF input pin LNA_IN. The input impedance of LNA_IN is specified in “Electrical Characteristics” on page

23. The parasitic board inductances and capacitances also influence the input matching. The RF

receiver ATA3741 exhibits its highest sensitivity at the best signal-to-noise ratio in the LNA. Hence, noise matching is the best choice for designing the transformation network.

A good practice when designing the network is to start with power matching. From that starting point, the values of the components can be varied to some extent to achieve the best sensitivity.

If a SAW is implemented into the input network, a mirror frequency suppression of ∆P can be achieved. There are SAWs available that exhibit a notch at ∆f=2MHz. These SAWs work best for an intermediate frequency of IF = 1 MHz. The selectivity of the receiver is also improved by using a SAW. In typical automotive applications, a SAW is used.

Figure 3-2 on page 6 shows a typical input matching network for f

= 433.92 MHz using a SAW. Figure 3-3 on page 6 illustrates an input matching to 50Ω with-

out a SAW. The input matching networks shown in Figure 3-3 are the reference networks for the parameters given in the “Electrical Characteristics” on page 23.

Table 3-1. Calculation of LO and IF Frequency

Conditions Local Oscillator Frequency Intermediate Frequency

= 315 MHz, MODE = 0 fLO = 314 MHz fIF = 1 MHz

= 433.92 MHz, MODE = 1 fLO = 432.92 MHz fIF = 1 MHz

300 MHz < f

365 MHz < f

< 365 MHz, MODE = 0

< 450 MHz, MODE = 1

----------------------------=

----------+

314

------------------+

432.92

-------------------=

----------= 314

------------------=

432.92

Ref

= 315 MHz and

=40dB

4899B–RKE–10/06

Page 6

Figure 3-2. Input Matching Network With SAW Filter

LNAGND

ATA3741

22p

fRF = 433.92 MHz

8.2 pF

TOKO LL2012

F33NJ

33n

25n

IN IN_GND

LNA_IN

C16

100p

B3555

CASE_GND

3, 4 7, 8

27n

C17

8.2p

TOKO LL2012

27NJ

OUT

OUT_GND

Figure 3-3. Input Matching Network Without SAW Filter

fRF = 433.92 MHz

15p

25n

LNAGND

ATA3741

LNA_IN

47p

fRF = 315 MHz

10 pF

TOKO LL2012

fRF = 315 MHz

F82NJ

82n

33p

25n

IN IN_GND

LNAGND

ATA3741

LNA_IN

C16

100p

B3551

CASE_GND

3, 4 7, 8

25n

47n

C17

22p

TOKO LL2012

F47NJ

OUT

OUT_GND

LNAGND

ATA3741

LNA_IN

3.3p 22n

100p

TOKO LL2012

F22NJ

3.3p 39n

100p

TOKO LL2012

F39NJ

Please note that for all coupling conditions (Figure 3-2 and Figure 3-3), the bond wire inductivity of the LNA ground is compensated. C3 forms a series resonance circuit together with the bond wire. L = 25 nH is a feed inductor to establish a DC path. Its value is not critical but must be large enough not to detune the series resonance circuit. For cost reduction, this inductor can be easily printed on the PCB. This configuration improves the sensitivity of the receiver by about 1 dB to 2dB.

ATA3741

4899B–RKE–10/06

Page 7

4. Analog Signal Processing

4.1 IF Amplifier

The signals coming from the RF front end are filtered by the fully integrated 4th-order IF filter. The IF center frequency is f is used. For other RF input frequencies, refer to Table 3-1 on page 5 to determine the center frequency.

The ATA3741 is available with 2 different IF bandwidths. ATA3741-M2, the version with B

= 300 kHz, is well suited for ASK systems where Atmel’s PLL transmitter U2741B is used.

The receiver ATA3741-M3 employs an IF bandwidth of B together with the U2741B in FSK and ASK mode. If used in ASK applications, it allows higher tolerances for the receiver and PLL transmitter crystals. SAW transmitters exhibit much higher transmit frequency tolerances compared to PLL transmitters. Generally, it is necessary to use B

= 600 kHz together with such transmitters.

4.2 RSSI Amplifier

The subsequent RSSI amplifier enhances the output signal of the IF amplifier before it is fed into the demodulator. The dynamic range of this amplifier is DR operated within its linear range, the best signal-to-noise ratio (SNR) is maintained in ASK mode. If the dynamic range is exceeded by the transmitter signal, the SNR is defined by the ratio of the maximum RSSI output voltage and the RSSI output voltage due to a disturber. The dynamic range of the RSSI amplifier is exceeded if the RF input signal is about 60 dB higher compared to the RF input signal at full sensitivity.

ATA3741

= 1 MHz for applications where fRF= 315 MHz or fRF=433.92MHz

= 600 kHz. This version can be used

= 60 dB. If the RSSI amplifier is

RSSI

In FSK mode, the SNR is not affected by the dynamic range of the RSSI amplifier.

The output voltage of the RSSI amplifier is internally compared to a threshold voltage V V

is determined by the value of the external resistor R

Th_red

Sense

. R

is connected between

Sense

Th_red

pin SENS and GND or VS. The output of the comparator is fed into the digital control logic. This makes it possible to operate the receiver at lower sensitivity.

If R is defined by the value of R

is connected to VS, the receiver operates at a lower sensitivity. The reduced sensitivity

Sense

, the maximum sensitivity by the SNR of the LNA input. The

Sense

reduced sensitivity is dependent on the signal strength at the output of the RSSI amplifier.

Since different RF input networks may exhibit slightly different values for the LNA gain, the sensitivity values given in the electrical characteristics refer to a specific input matching. This matching is illustrated in Figure 3-3 on page 6 and exhibits the best possible sensitivity.

can be connected to VS or GND via a microcontroller or by the digital output port POUT of

Sense

the ATA3741 receiver IC. The receiver can be switched from full sensitivity to reduced sensitivity or vice versa at any time. In polling mode, the receiver will not wake up if the RF input signal does not exceed the selected sensitivity. If the receiver is already active, the data stream at pin DATA will disappear when the input signal is lower than defined by the reduced sensitivity. Instead of the data stream, the pattern shown in Figure 4-1 is issued at pin DATA to indicate that the receiver is still active.

Figure 4-1. Steady L State Limited DATA Output Pattern

4899B–RKE–10/06

DATA

min2

DATA_L_max

Page 8

4.3 FSK/ASK Demodulator and Data Filter

The signal coming from the RSSI amplifier is converted into the raw data signal by the ASK/FSK demodulator. The operating mode of the demodulator is set via pin ASK/FSK. Logic “L” sets the demodulator to FSK, Logic “H” sets it into ASK mode.

In ASK mode an automatic threshold control circuit (ATC) is employed to set the detection reference voltage to a value where a good SNR is achieved. This circuit also implies the effective suppression of any kind of in-band noise signals or competing transmitters. If the SNR exceeds 10 dB, the data signal can be detected properly.

The FSK demodulator is intended to be used for an FSK deviation of ∆f ≥ 20 kHz. Lower values may be used, but the sensitivity of the receiver will be reduced. The minimum usable deviation is dependent on the selected baud rate. In FSK mode, only BR_Range0 and BR_Range1 are available. In FSK mode, the data signal can be detected if the SNR exceeds 2 dB.

The output signal of the demodulator is filtered by the data filter before it is fed into the digital signal processing circuit. The data filter improves the SNR as its bandpass can be adopted to the characteristics of the data signal. The data filter consists of a 1st-order high-pass filter and a 1st-order low-pass filter.

The high-pass filter cut-off frequency is defined by an external capacitor connected to pin CDEM. The cut-off frequency of the high-pass filter is defined by the following formula:

cu_DF

-------------------------------------------------------------=

2 π× 30 kΩ× CDEM×

In self-polling mode, the data filter must settle very rapidly to achieve a low current consumption. Therefore, CDEM cannot be increased to very high values if self-polling is used. On the other hand, CDEM must be large enough to meet the data filter requirements according to the data signal. Recommended values for CDEM are given in the “Electrical Characteristics” on page 23. The values are slightly different for ASK and FSK mode.

The cut-off frequency of the low-pass filter is defined by the selected baud rate range (BR_Range). BR_Range is defined in the OPMODE register (Section “Configuration of the

Receiver” on page 17). BR_Range must be set in accordance to the used baud rate.

The ATA3741 is designed to operate with data coding where the DC level of the data signal is 50%. This is valid for Manchester and Bi-phase coding. If other modulation schemes are used, the DC level should always remain within the range of VDC_min = 33% and VDC_max = 66%. The sensitivity may be reduced by up to 1.5 dB in that condition.

Each BR_Range is also defined by a minimum and a maximum edge-to-edge time (t These limits are defined in the “Electrical Characteristics” on page 23. They should not be exceeded to maintain full sensitivity of the receiver.

4.4 Receiving Characteristics

The RF receiver ATA3741 can be operated with and without a SAW front-end filter. In a typical automotive application, a SAW filter is used to achieve better selectivity. The selectivity with and without a SAW front-end filter is illustrated in Figure 4-2 on page 9. This example relates to ASK mode and the 300-kHz bandwidth version of the ATA3741. FSK mode and the 600-kHz version of the receiver exhibit similar behavior. Note that the mirror frequency is reduced by 40 dB. The plots are printed relative to the maximum sensitivity. If a SAW filter is used, an insertion loss of about 4 dB must be considered.

ee_sig

ATA3741

4899B–RKE–10/06

Page 9

ATA3741

When designing the system in terms of receiving bandwidth, the LO deviation must be considered as it also determines the IF center frequency. The total LO deviation is calculated to be the sum of the deviation of the crystal and the XTO deviation of the ATA3741. Low-cost crystals are specified to be within ±100 ppm. The XTO deviation of the ATA3741 is an additional deviation due to the XTO circuit. This deviation is specified to be ±30 ppm. If a crystal of ±100 ppm is used, the total deviation is ±130 ppm in that case. Note that the receiving bandwidth and the IF-filter bandwidth are equivalent in ASK mode but not in FSK mode.

Figure 4-2. Receiving Frequency Response

0.0

-10.0

-20.0

-30.0

-40.0

-50.0

-60.0

dP (dB)

-70.0

-80.0

-90.0

-100.0

-6.0 -5.0 -4.0 -3.0 -2.0 -1.0 0.0 1.0 2.0 3.0 4.0 5.0 6.0

df (MHz)

without SAW

with SAW

5. Polling Circuit and Control Logic

The receiver is designed to consume less than 1 mA while being sensitive to signals from a corresponding transmitter. This is achieved via the polling circuit. This circuit enables the signal path periodically for a short time. During this time the bit-check logic verifies the presence of a valid transmitter signal. Only if a valid signal is detected does the receiver remain active and transfer the data to the connected microcontroller. If there is no valid signal present, the receiver is in sleep mode most of the time, resulting in low current consumption. This condition is called polling mode. A connected microcontroller is disabled during that time.

All relevant parameters of the polling logic can be configured by the connected microcontroller. This flexibility enables the user to meet the specifications in terms of current consumption, system response time, data rate, etc.

Regarding the number of connection wires to the microcontroller, the receiver is very flexible. It can be either operated by a single bi-directional line to save ports to the connected microcontroller, or it can be operated by up to three uni-directional ports.

5.1 Basic Clock Cycle of the Digital Circuitry

The complete timing of the digital circuitry and the analog filtering is derived from one clock. As seen in Figure 5-1 on page 10, this clock cycle T combination with a divider. The division factor is controlled by the logical state at pin MODE. The frequency of the crystal oscillator (f defines the operating frequency of the local oscillator (f

is derived from the crystal oscillator (XTO) in

Clk

) is defined by the RF input signal (f

XTO

) (See “RF Front End” on page 4).

) which also

RFin

4899B–RKE–10/06

Page 10

Figure 5-1. Generation of the Basic Clock Cycle

Divider :14/:10

XTO

Clk

XTO

MODE

DVCC

XTO

L : USA (:10) H: Europe (:14)

Pin MODE can now be set in accordance with the desired clock cycle T

Clk

. T

controls the fol-

Clk

lowing application-relevant parameters:

• Timing of the polling circuit including bit check

• Timing of analog and digital signal processing

• Timing of register programming

• Frequency of the reset marker

• IF filter center frequency (f

Most applications are dominated by two transmission frequencies: f used in the USA, f

= 433.92 MHz in Europe. In order to ease the usage of all T

Send

IF0

)

= 315 MHz is mainly

Send

-dependent

Clk

parameters, the electrical characteristics display three conditions for each parameter.

• USA Applications (f

= 4.90625 MHz, MODE = 0, T

XTO

= 2.0383 µs)

Clk

• Europe Applications (f

= 6.76438 MHz, MODE = 1, T

XTO

= 2.0697 µs)

Clk

• Other applications (T

is dependent on f

Clk

is given as a function of T

and on the logical state of pin MODE. The electrical characteristic

XTO

Clk

The clock cycle of some function blocks depends on the selected baud rate range (BR_Range) which is defined in the OPMODE register. This clock cycle T

is defined by the following for-

XClk

mulas for further reference:

ATA3741

BR_Range = BR_Range0: T

BR_Range1: T

BR_Range2: T

BR_Range3: T

XClk

= 8 × T = 4 × T = 2 × T = 1 × T

Clk

4899B–RKE–10/06

Page 11

5.2 Polling Mode

ATA3741

As shown in Figure 3-2 on page 6, the receiver stays in polling mode in a continuous cycle of three different modes. In sleep mode, the signal processing circuitry is disabled for the time period T nal processing circuits are enabled and settled. In the following bit-check mode, the incoming data stream is analyzed bit by bit against a valid transmitter signal. If no valid signal is present, the receiver is set back to sleep mode after the period T check as it is a statistical process. An average value for T

istics” on page 23. During T

current consumption in polling mode is dependent on the duty cycle of the active mode and can be calculated as:

while consuming a low current of IS=I

Sleep

and T

Startup

Bitcheck

. During the start-up period, T

Soff

. This period varies check by

Bitcheck

is given in “Electrical Character-

Bitcheck

the current consumption is IS =I

, all sig-

Startup

. The average

Son

5.2.1 Sleep Mode

Spoll

During T

SoffTSleepISon

------------------------------------------------------------------------------------------------------------=

SleepTStartupTBitcheck

and T

Sleep

Startup

+()×+×

StartupTBitcheck

, the receiver is not sensitive to a transmitter signal. To guarantee the reception of a transmitted command, the transmitter must start the telegram with an adequate preburst. The required length of the preburst is dependent on the polling parameters T

, T

tup

on the actual bit rate and the number of bits (N

, and the startup time of a connected microcontroller (T

Bitcheck

) to be tested.

Start_µC

). T

thus depends

Bitcheck

Sleep

, T

Star-

The following formula indicates how to calculate the preburst length.

The length of period T extension factor X

Preburst

≥ T

Sleep

+ T

Startup

is defined by the 5-bit word Sleep of the OPMODE register, on the

Sleep

according to Figure 5-4 on page 13, and on the basic clock cycle T

Sleep

Bitcheck

+ T

Start_µC

Clk

. It is

calculated to be:

Sleep

In US and European applications, the maximum value of T

Sleep X

× 1024× T

Sleep

×=

Clk

is about 60 ms if X

Sleep

is set to 1.

Sleep

The time resolution is about 2 ms in that case. The sleep time can be extended to almost half a second by setting X

Sleep

to 8. X

can be set to 8 by bit X

Sleep

SleepStd

or by bit X

SleepTemp

, resulting in

a different mode of action as described below:

= 1 implies the standard extension factor. The sleep time is always extended.

SleepStd

SleepTemp

= 1 implies the temporary extension factor. The extended sleep time is used as long as every bit check is OK. If the bit check fails once, this bit is set back to 0 automatically, resulting in a regular sleep time. This functionality can be used to save current in the presence of a modulated disturber similar to an expected transmitter signal. The connected microcontroller is rarely activated in that condition. If the disturber disappears, the receiver switches back to regular polling and is again sensitive to appropriate transmitter signals.

4899B–RKE–10/06

As seen in Table 5-6 on page 19, the highest register value of Sleep sets the receiver to a permanent sleep condition. The receiver remains in that condition until another value for Sleep is programmed into the OPMODE register. This function is desirable where several devices share a single data line.

Page 12

Figure 5-2. Polling Mode Flow Chart

Sleep Mode:

All circuits for signal processing are disabled. Only XTO and polling logic is enabled. Output level on pin IC_ACTIVE => low

= I

SON

= Sleep × X

Sleep

× 1024 × T

Clk

Sleep: 5-bit word defined by Sleep0 to Sleep4 in

OPMODE register

Extension factor defined by X

Sleep

according to Table 5-7

SleepTemp

Start-up Mode:

The signal processing circuits are enabled. After the start-up time (T all circuits are in stable condition and ready to receive. I

= I

SON

Startup

Bit-check Mode:

The incoming data stream is analyzed. If the timing indicates a valid transmitter signal, the receiver is set to receiving mode. Otherwise is set to Sleep mode. I

= I

Son

Bitcheck

Bit-check

OK?

YES

Receiving Mode:

The receiver is turned on permanently and passes the data stream to the connected microcontroller. It can be set to Sleep mode through an OFF command via pin DATA or ENABLE I

= I

SON

OFF command

Startup

: Basic clock cycle defined by f

Clk

)

Startup

MODE

Is defined by the selected baud rate range

and T

. The baud rate range is defined

Clk

by Baud0 and Baud1 in the OPMODE

XTO

and pin

: Depends on the result of the bit check.

Bitcheck

If the bit check is ok, T on the number of bits to be checked (N

) and on the utilized data rate.

Bitchecked

Bitcheck

depends

If the bit check fails, the average time period for that check depends on the selected baud rate range on T baud rate range is defined by Baud0 and

Clk

. The

Baud1 in the OPMODE register.

Figure 5-3. Timing Diagram for a Completely Successful Bit Check

Bit check ok

1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit

Number of Checked Bits: 3

Enable IC

Bit check

Dem_out

DATA

ATA3741

Polling mode

1/2 Bit

Receiving mode

4899B–RKE–10/06

Page 13

5.3 Bit-check Mode

In bit-check mode, the incoming data stream is examined to distinguish between a valid signal from a corresponding transmitter and signals due to noise. This is done by subsequent time frame checks where the distances between 2 signal edges are continuously compared to a programmable time window. The maximum count of this edge-to-edge test, before the receiver switches to receiving mode, is also programmable.

5.3.1 Configuring the Bit Check

Assuming a modulation scheme that contains 2 edges per bit, two time frame checks verify one bit. This is valid for Manchester, Bi-phase and most other modulation schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the variable N register. This implies 0, 6, 12 and 18 edge-to-edge checks respectively. If N higher value, the receiver is less likely to switch to the receiving mode due to noise. In the presence of a valid transmitter signal, the bit check takes less time if N In polling mode, the bit-check time is not dependent on N example where 3 bits are tested successfully and the data signal is transferred to pin DATA.

Figure 5-4 shows how the time window for the bit check is defined by two separate time limits. If

the edge-to-edge time t limit T

Lim_max

the bit check will be terminated and the receiver will switch to sleep mode.

. Figure 5-3 on page 12 shows an

Bitcheck

is in between the lower bit check limit T

, the check will be continued. If tee is smaller than T

ATA3741

in the OPMODE

Bitcheck

is set to a lower value.

Bitcheck

and the upper bit check

Lim_min

or tee exceeds T

Lim_min

is set to a

Lim_max

Figure 5-4. Valid Time Window for Bit Check

1/f

Sig

Dem_out

For best noise immunity it is recommended to use a low span between T

lim_min

lim_max

and T

Lim_min

Lim_max

This is achieved using a fixed frequency at a 50% duty cycle for the transmitter preburst. A “11111...” or a “10101...” sequence in Manchester or Bi-phase is a good choice in this regard. A good compromise between receiver sensitivity and susceptibility to noise is a time window of ±25% regarding the expected edge-to-edge time t

. Using preburst patterns that contain vari-

ous edge-to-edge time periods, the bit check limits must be programmed according to the required span.

The bit-check limits are determined by means of the formula below:

T T

= Lim_min × T

Lim_min

= (Lim_max –1) × T

Lim_max

XClk

Lim_min and Lim_max are defined by a 5-bit word each within the LIMIT register.

4899B–RKE–10/06

Using the above formulas, Lim_min and Lim_max can be determined according to the required T minimum edge-to-edge time t

Lim_min

, T

Lim_max

and T

. The time resolution when defining T

XClk

DATA_L_min

, t

DATA_H_min

) is defined in Section “Receiving Mode”

Lim_min

and T

Lim_max

is T

XClk

. The

on page 15. Due to this, the lower limit should be set to Lim_min ≥ 10. The maximum value of

the upper limit is Lim_max = 63.

Page 14

Figure 5-5, Figure 5-6 and Figure 5-7 illustrate the bit check for the default bit-check limits

Lim_min = 14 and Lim_max = 24. When the IC is enabled, the signal processing circuits are enabled during T

Startup

that period. When the bit check becomes active, the bit-check counter is clocked with the cycle T

XClk

Figure 5-5 shows how the bit check proceeds if the bit-check counter value CV_Lim is within the

limits defined by Lim_min and Lim_max at the occurrence of a signal edge. In Figure 5-6, the bit check fails as the value CV_lim is lower than the limit Lim_min. The bit check also fails if CV_Lim reaches Lim_max. This is illustrated in Figure 5-7.

Figure 5-5. Timing Diagram During Bit Check

(Lim_min = 14, Lim_max = 24)

Enable IC

Bit check

Dem_out

Startup

. The output of the ASK/FSK demodulator (Dem_out) is undefined during

Bit check ok Bit check ok

1/2 Bit

1/2 Bit 1/2 Bit

Bit check counter

23456 2 451781367891112131410

XClk

15161718 1 2 3 4 5 6

Figure 5-6. Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)

(Lim_min = 14, Lim_max = 24)

Enable IC

Bit check

Dem_out

Bit check counter

Startup Mode

23456 2 451 3 6 7 8 9 11 1210

Bit check Mode

Bit check failed ( CV_Lim < Lim_min )

1/2 Bit

Sleep Mode

Figure 5-7. Timing Diagram for Failed Bit Check (Condition: CV_Lim ≥ Lim_max)

(Lim_min = 14, Lim_max = 24)

Enable IC

Bit check

Dem_out

1/2 Bit

Bit check failed (CV_Lim = Lim_max)

7891011121314151234

Bit check counter

ATA3741

Startup Mode

23456 2 451736789111210

Bit check Mode

13141516171819 21222324 01

Sleep Mode

4899B–RKE–10/06

Page 15

5.3.2 Duration of the Bit Check

If no transmitter signal is present during the bit check, the output of the ASK/FSK demodulator delivers random signals. The bit check is a statistical process and T Therefore, an average value for T on the selected baud rate range and on T T

, resulting in lower current consumption in polling mode.

Bitcheck

In the presence of a valid transmitter signal, T nal, on f

Sig

results in a longer period for T T

Preburst

5.4 Receiving Mode

If the bit check is successful for all bits specified by N mode. As seen in Figure 5-3 on page 12, the internal data signal is then switched to pin DATA. A connected microcontroller can be woken up by the negative edge at pin DATA. The receiver stays in that condition until it is explicitly switched back to polling mode.

5.4.1 Digital Signal Processing

The data from the ASK/FSK demodulator (Dem_out) is digitally processed in different ways and as a result converted into the output signal data. This processing depends on the selected baud rate range (BR_Range). Figure 5-8 illustrates how Dem_out is synchronized by the extended clock cycle T after T

XClk

integral multiple of T

The minimum time period between two edges of the data signal is limited to t implies an efficient suppression of spikes at the DATA output. At the same time, it limits the maximum frequency of edges at DATA. This eases the interrupt handling of a connected microcontroller. T t

as illustrated in Figure 5-9 on page 16. If tee is in between the specified bit-check limits, the

following level is frozen for the time period T T

DATA_min

The maximum time period for DATA to be low is limited to T finite response time during programming or switching off the receiver via pin DATA. T is thereby longer than the maximum time period indicated by the transmitter data stream. Figure

5-10 on page 16 gives an example where Dem_out remains low after the receiver has switched

to receiving mode.

ATA3741

varies for each check.

Bitcheck

is given in “Electrical Characteristics”. T

Bitcheck

. A higher baud rate range causes a lower value for

Clk

is dependent on the frequency of that sig-

Bitcheck

, and on the count of the checked bits, N

, requiring a higher value for the transmitter preburst

Bitcheck

. This clock is also used for the bit-check counter. Data can change its state only

XClk

. A higher value for N

Bitcheck

, the receiver switches to receiving

Bitcheck

elapsed. The edge-to-edge time period tee of the Data signal, as a result, is always an

XClk

≥ T

DATA_min

is to some extent affected by the preceding edge-to-edge time interval

DATA_min

=tmin1; if tee is outside that bit check limit,

= tmin2 is the relevant stable time period.

DATA_L_max

. This function ensures a

Bitcheck

DATA_min

depends

thereby

. This

DATA_L_max

Figure 5-8. Synchronization of the Demodulator Output

XClk

Clock bit check counter

Dem_out

DATA

4899B–RKE–10/06

Page 16

Figure 5-9. Debouncing of the Demodulator Output

Dem_out

DATA

Lim_min ≤ CV_Lim < Lim_max

tmin1

CV_Lim < Lim_min or CV_Lim ≥ Lim_max

Figure 5-10. Steady L State Limited DATA Output Pattern after Transmission

Enable IC

Bit check

Dem_out

tmin2

DATA

Sleep mode Receiving mode

Bit check mode

After the end of a data transmission, the receiver remains active and random noise pulses appear at pin DATA. The edge-to-edge time period t equal to or slightly higher than T

5.4.2 Switching the Receiver Back to Sleep Mode

The receiver can be set back to polling mode via pin DATA or via pin ENABLE.

When using pin DATA, this pin must be pulled to low by the connected microcontroller for the period t1. Figure 5-11 on page 17 illustrates the timing of the OFF command (see also Figure

5-15 on page 22). The minimum value of t1 depends on the BR_Range. The maximum value for

t1 is not limited but it is recommended not to exceed the specified value to prevent erasing the reset marker. This item is explained in more detail in Section “Configuration of the Receiver” on

page 17. Setting the receiver to sleep mode via DATA is achieved by programming bit 1 of the

OPMODE register to 1. Only one sync pulse (t3) is issued.

The duration of the OFF command is determined by the sum of t1, t2 and t10. After the OFF command, the sleep time T

Sleep

The resulting time constant τ together with an optional external pull-up resistor may not be exceeded to ensure proper operation.

If the receiver is set to polling mode via pin ENABLE, an “L” pulse (T pin. Figure 5-12 on page 17 illustrates the timing of that command. After the positive edge of this pulse, the sleep time T

elapses. The receiver remains in sleep mode as long as ENABLE is

Sleep

held to “L”. If the receiver is polled exclusively by a microcontroller, T “0” to enable an instantaneous response time. This command is the faster option than via pin DATA, but at the cost of an additional connection to the microcontroller.

DATA_L_max

of the majority of these noise pulses is

DATA_min

tmin2

elapses. Note that the capacitive load at pin DATA is limited.

) must be issued at that

Doze

can be programmed to

Sleep

ATA3741

4899B–RKE–10/06

Page 17

Figure 5-11. Timing Diagram of the OFF Command Via Pin DATA

t1 t2

Out1 (microcontroller)

t10

ATA3741

DATA (U3741BM)

Serial bi-directional data line

Receiver

OFF command

Bit 1 ("1")

(Start bit)

Figure 5-12. Timing Diagram of the OFF Command Via Pin ENABLE

ENABLE

DATA (U3741BM)

Serial bi-directional data line

Doze

off

Receiver on Startup mode

Sleep

Startup mode

5.5 Configuration of the Receiver

The ATA3741 receiver is configured via two 12-bit RAM registers called OPMODE and LIMIT. The registers can be programmed by means of the bi-directional DATA port. If the register contents have changed due to a voltage drop, this condition is indicated by a certain output pattern called reset marker (RM). The receiver must be reprogrammed in that case. After a power-on reset (POR), the registers are set to default mode. If the receiver is operated in default mode, there is no need to program the registers.

Table 5-2 on page 18 shows the structure of the registers. As shown in Table 5-1, bit 1 defines if

the receiver is set back to polling mode via the OFF command, (see Section “Receiving Mode”

on page 15) or if it is programmed. Bit 2 represents the register address; it selects the appropri-

ate register to be programmed.

Table 5-1. Effect of Bit 1 and Bit 2 in Programming the Registers

Bit 1 Bit 2 Action

1 x The receiver is set back to polling mode (OFF command) 0 1 The OPMODE register is programmed 0 0 The LIMIT register is programmed

4899B–RKE–10/06

Page 18

Table 5-3 through Table 5-9 on page 20 illustrate the effect of the individual configuration words.

The default configuration is labeled for each word.

BR_Range sets the appropriate baud rate range. At the same time, it defines XLim. XLim is used to define the bit check limits T

Lim_min

and T

as shown in Table 5-3.

Lim_max

POUT can be used to control the sensitivity of the receiver. In that application, POUT is set to “1” to reduce the sensitivity. This implies that the receiver operates with full sensitivity after a POR.

Table 5-2. Effect of the Configuration Words within the Registers

Bit1 Bit2 Bit2 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 Bit12 Bit13 Bit14

OFF Command

OPMODE Register

0 1 BR_Range N 0 1 Baud1 Baud0 BitChk1 BitChk0 POUT Sleep4 Sleep3 Sleep2 Sleep1 Sleep0 X

(Default)0010001 0110 0

LIMIT Register

0 0 Lim_min Lim_max 0 0 Lim_min5 Lim_min4 Lim_min3 Lim_min2 Lim_min1 Lim_min0 Lim_max5 Lim_max4 Lim_max3 Lim_max2 Lim_max1 Lim_max0

(Default)0011100 1100 0

Bitcheck

POUT

Sleep X

Sleep StdXSleep Temp

Sleep

Table 5-3. Effect of the Configuration Word BR_Range

BR_Range

Baud Rate Range/Extension Factor for Bit Check Limits (XLim)Baud1 Baud0

Table 5-4. Effect of the Configuration Word N

Bitcheck

00 0 01 3 1 0 6 (Default) 11 9

BR_Range0 (Application USA/Europe: BR_Range0 = 1.0 kBaud to 1.8 kBaud) (Default) XLim = 8 (Default)

BR_Range1 (Application USA/Europe: BR_Range1 = 1.8 kBaud to 3.2 kBaud) XLim = 4

BR_Range2 (Application USA/Europe: BR_Range2 = 3.2 kBaud to 5.6 kBaud) XLim = 2

BR_Range3 (Application USA/Europe: BR_Range3 = 5.6 kBaud to 10 kBaud) XLim = 1

Bitcheck

Number of Bits to be CheckedBitChk1 BitChk0

ATA3741

4899B–RKE–10/06

Page 19

Table 5-5. Effect of the Configuration Bit VPOUT

VPOUT Level of the Multi-purpose Output Port POUT

POUT

0 0 (Default) 11

Table 5-6. Effect of the Configuration Word Sleep

Sleep

000000 (Receiver polls continuously until a valid signal occurs) 000011 (T

Sleep

00010 2 00011 3

. . .

0101111 (USA: T

. . .

. .

. 11101 29 11110 30 11111 31 (Permanent sleep mode)

Start Value for Sleep Counter

= Sleep × X

Sleep

≈ 2 ms for X

Sleep

= 1 in US/European applications)

. . .

= 22.96 ms, Europe: T

Sleep

. . .

× 1024 × T

= 23.31 ms) (Default)

Sleep

ATA3741

)Sleep4 Sleep3 Sleep2 Sleep1 Sleep0

Clk

Table 5-7. Effect of the Configuration Word X

Sleep

SleepStd

0 0 1 (Default) 018 (X 10 8 (X 11 8 (X

4899B–RKE–10/06

SleepTemp

Sleep

Extension Factor for Sleep Time

= Sleep × X

Sleep

is reset to 1 if bit check fails once)

Sleep

is set permanently)

Sleep

is set permanently)

Sleep

× 1024 × T

Sleep

Clk

Page 20

Table 5-8. Effect of the Configuration Word Lim_min

Lim_min

001010 10 001011 11 001100 12 001101 13

001110

. . .

(USA: T

111101 61 111110 62 111111 63

Lower Limit Value for Bit Check

= Lim_min × XLim × T

Lim_min

14 (Default)

= 228 µs, Europe: T

Lim_min

Table 5-9. Effect of the Configuration Word Lim_max

Lim_max Upper Limit Value for Bit Check

Lim_max < 12 is not applicable (T

001100 12 001101 13 001110 14

. . .

011000

. . .

(USA: T

. . .

. .

. 111101 61 111110 62 111111 63

= (Lim_max – 1) × XLim × T

Lim_max

24 (Default)

= 375 µs, Europe: T

Lim_max

)Lim_min < 10 is not applicable

Clk

= 232 µs)

Lim_min

. . .

)

Clk

. . .

= 381 µs)

Lim_max

. . .

5.5.1 Conservation of the Register Information

The ATA3741 has integrated power-on reset and brown-out detection circuitry to provide a mechanism to preserve the RAM register information.

Figure 5-13 on page 21 shows the timing of a power-on reset (POR) generated if the supply volt-

age V

drops below the threshold voltage V

the configuration registers in that condition. Once V the minimum reset period t is turned on.

ATA3741

. The default parameters are programmed into

ThReset

exceeds V

. A POR is also generated when the supply voltage of the receiver

Rst

, the POR is canceled after

ThReset

4899B–RKE–10/06

Page 21

To indicate that condition, the receiver displays a reset marker (RM) at pin DATA after a reset. The RM is represented by the fixed frequency f an “L” pulse t1 at pin DATA. The RM implies the following characteristics:

•f

is lower than the lowest feasible frequency of a data signal. By this means, RM cannot be

misinterpreted by the connected microcontroller.

• If the receiver is set back to polling mode via pin DATA, RM cannot be canceled by accident if t1 is applied according to the proposal in Section “Programming the Configuration Register”

on page 21.

By means of that mechanism, the receiver cannot lose its register information without communicating that condition via the reset marker RM.

Figure 5-13. Generation of the Power-on Reset

POR

Rst

DATA (ATA3741)

ThReset

ATA3741

at a 50% duty cycle. RM can be canceled via

Figure 5-14. Timing of the Register Programming

Bit 1 ("0")

(Start bit)

Out1 (microcontroller)

DATA (ATA3741)

Serial bi-directional data line

Receiver

5.5.2 Programming the Configuration Register

The configuration registers are programmed serially via the bi-directional data line as shown in

Figure 5-14 and Figure 5-15 on page 22.

Bit 2

("1)

(Register select)

Programming Frame

Bit 13

("0")

(Poll8)

1/f

Sleep

Bit 14

("1")

(Poll8R)

Startup

mode

4899B–RKE–10/06

Page 22

Figure 5-15. One-wire Connection to a Microcontroller

ATA3741

Internal pull-up

resistor

DATA (ATA3741)

Bi-directional

data line

DATA

Microcontroller

I/O

Out 1 (microcontroller)

To start programming, the serial data line DATA is pulled to “L” by the microcontroller for the time period t1. When DATA has been released, the receiver becomes the master device. When the programming delay period t2 has elapsed, it emits 14 subsequent synchronization pulses with the pulse length t3. After each of these pulses, a programming window occurs. The delay until the program window starts is determined by t4, the duration is defined by t5. Within the programming window, the individual bits are set. If the microcontroller pulls down pin DATA for the time period t7 during t5, the according bit is set to “0”. If no programming pulse t7 is issued, this bit is set to “1”. All 14 bits are subsequently programmed in this way. The time frame to program a bit is defined by t6.

Bit 14 is followed by the equivalent time window t9. During this window, the equivalent acknowledge pulse t8 (E_Ack) occurs if the mode word just programmed is equivalent to the mode word that was already stored in that register. E_Ack should be used to verify that the mode word was correctly transferred to the register. The register must be programmed twice in that case.

Programming of a register is possible both during sleep and active mode of the receiver.

During programming, the LNA, LO, low-pass filter, IF amplifier and the demodulator are disabled.

The programming start pulse t1 initiates the programming of the configuration registers. If bit 1 is set to “1”, it represents the OFF command to set the receiver back to polling mode at the same time. For the length of the programming start pulse t1, the following convention should be considered:

• t1(min) < t1 < 1535 × T

: [t1(min) is the minimum specified value for the relevant

Clk

BR_Range]

Programming (or the OFF command) is initiated if the receiver is not in reset mode. If the receiver is in reset mode, programming (or the OFF command) is not initiated, and the reset marker RM is still present at pin DATA.

This period is generally used to switch the receiver to polling mode. In a reset condition, RM is not canceled by accident.

• t1 > 5632 × T

Clk

Programming (or the OFF command) is initiated in any case. RM is cancelled if present. This period is used if the connected microcontroller detected RM. If a configuration register is programmed, this time period for t1 can generally be used.

Note that the capacitive load at pin DATA is limited. The resulting time constant t together with an optional external pull-up resistor should not be exceeded, to ensure proper operation.

ATA3741

4899B–RKE–10/06

Page 23

ATA3741

6. Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Parameters Symbol Min. Max. Unit

Supply voltage V Power dissipation P Junction temperature T Storage temperature T Ambient temperature T Maximum input level, input matched to 50Ω P

tot

stg

amb

in_max

–55 +125 °C –40 +105 °C

7. Thermal Resistance

Parameters Symbol Value Unit

Junction ambient R

thJA

100 K/W

8. Electrical Characteristics

All parameters refer to GND, T

= 5V, T

Parameter Test Condition Symbol Basic Clock Cycle of the Digital Circuitry

Basic clock cycle

Extended basic clock cycle

Polling Mode

Sleep time

Start-up time

Time for bit check

= 25°C)

amb

MODE = 0 (USA) MODE = 1 (Europe)

BR_Range0 BR_Range1 BR_Range2 BR_Range3

Sleep and X are defined in the

Sleep

OPMODE register

BR_Range0 BR_Range1 BR_Range2 BR_Range3

Average bit check time while polling BR_Range0 BR_Range1 BR_Range2 BR_Range3

Bit check time for a valid input signal f N

= 0

Bitcheck

= 3

Bitcheck

= 6

Bitcheck

= 9

Bitcheck

= –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.

amb

6.76438-Mhz Oscillator (Mode 1)

Clk

2.0697

16.6

XClk

8.3

4.1

2.1

Sleep

Sleep × X

Sleep

1024

2.0697 1855

Startup

1061 1061

663

Bitcheck

0.45

0.24

0.14

Sig

Bitcheck

3 / f 6 / f 9 / f

Sig Sig Sig

3.5 / f

6.5 / f

9.5 / f

4.90625-Mhz Oscillator (Mode 0) Variable Oscillator

2.0383

16.3

8.2

4.1

2.0

Sleep

1024

2.0383 1827

1045 1045

653

0.47

0.26

0.16

0.15

3/f

Sig Sig Sig

6/f 9/f

Sig Sig Sig

3.5 / f

6.5 / f

9.5 / f

Sig Sig Sig

6V 450 mW 150 °C

10 dBm

UnitMin. Typ. Max. Min. Typ. Max. Min. Typ. Max.

1/(f

/10)

XTO

1/(f

/14)

XTO

× T

Clk

4 × T

Clk

2 × T

Clk

1 × T

Clk

Sleep

1024

Clk

896.5

512.5

320.5

× T

Clk

XClk

3.5 / f

Sig

6.5 / f

Sig

9.5 / f

Sig

µs µs

µs µs µs µs

ms ms ms ms

4899B–RKE–10/06

Page 24

8. Electrical Characteristics (Continued)

All parameters refer to GND, T (VS = 5V, T

Parameter Test Condition Symbol Receiving Mode

Intermediate frequency

Baud rate range

Minimum time period between edges at pin DATA (Figure 5-9

on page 16)

Maximum low period at DATA (Figure 5-10)

OFF command at pin ENABLE (Figure 5-12)

Configuration of the Receiver

Frequency of the reset marker (Figure 5-13)

Programming start pulse (Figure 5-11,

Figure 5-14)

Programming delay period (Figure 5-11,

Figure 5-14)

Synchronization pulse (Figure 5-11,

Figure 5-14)

Delay until the program window starts (Figure 5-11,

Figure 5-14)

Programming window (Figure 5-11,

Figure 5-14)

= 25°C)

amb

MODE=0 (USA) MODE=1 (Europe)

BR_Range0 BR_Range1 BR_Range2 BR_Range3

BR_Range0

BR_Range1

BR_Range2

BR_Range3

BR_Range0 BR_Range1 BR_Range2 BR_Range3

BR_Range0 BR_Range1 BR_Range2 BR_Range3 after POR

= –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.

amb

6.76438-Mhz Oscillator (Mode 1)

BR_Range

DATA _min

tmin1 tmin2 tmin1 tmin2 tmin1 tmin2 tmin1 tmin2

1.0

1.8

3.2

5.6

1.0 1.0

1.8

3.2

5.6

10.0

149 182

75 91

37.3

45.5

18.6

22.8

2169

DATA_L_max

1085

542 271

Doze

3.1 3.05 1.5 × T

117.9 119.8 Hz

2188 1104

561 290

3176 3176 3176 3176

11656

t2 795 798 783 786 384.5 × T

t3 265 261 128 × T

t4 131 129 63.5 × T

t5 530 522 256 × T

4.90625-Mhz Oscillator (Mode 0) Variable Oscillator

1.0

1.8

3.2

5.6

1.8

3.2

5.6

10.0

BR_Range0 × 2 µs / T BR_Range1 × 2 µs / T BR_Range2 × 2 µs / T BR_Range3 × 2 µs / T

147 179

73 90

36.7

44.8

18.3

22.4

2136 1068

534 267

Clk

1057 × T

2155 1087

553 286

11479

3128 3128 3128 3128

533 × T 271 × T 140 × T

5632 × T

Clk Clk Clk Clk

Clk

× 64 / 314

XTO

× 64 / 432.92

XTO

9 × T

XClk

11 × T

9 × T

XClk

11 × T

XClk

9 × T

XClk

11 × T

XClk

9 × T

XClk

11 × T

XClk

131 × T 131 × T 131 × T 131 × T

---------------------------------

4096 T

XCl

XClk XClk XClk XClk

CLK

Clk

Clk Clk Clk Clk

1535 × T 1535 × T 1535 × T 1535 × T

385.5 × T

Clk Clk Clk Clk

Clk

UnitMin. Typ. Max. Min. Typ. Max. Min. Typ. Max.

MHz MHz

kBaud kBaud kBaud kBaud

µs µs µs µs µs µs µs µs

µs µs µs µs

µs

ATA3741

4899B–RKE–10/06

Page 25

8. Electrical Characteristics (Continued)

All parameters refer to GND, T (VS = 5V, T

Parameter Test Condition Symbol

Time frame of a bit (Figure 5-14)

Programming pulse (Figure 5-11,

Figure 5-14)

Equivalent acknowledge pulse: E_Ack (Figure 5-14)

Equivalent time window (Figure 5-14)

OFF bit programming window (Figure 5-11)

= 25°C)

amb

= –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.

amb

6.76438-Mhz Oscillator (Mode 1)

t6 1060 1044 512 × T

t7 133 529 131 521 64 × T

t8 265 261 128 × T

t9 534 526 258 × T

t10 930 916 449.5 × T

4.90625-Mhz Oscillator (Mode 0) Variable Oscillator

Clk

ATA3741

Clk

256 × T

Clk

UnitMin. Typ. Max. Min. Typ. Max. Min. Typ. Max.

µs

9. Electrical Characteristics

All parameters refer to GND, T (VS = 5V, T

= 25°C)

amb

Parameters Test Conditions Symbol Min. Typ. Max. Unit

Current consumption

LNA Mixer

Third-order intercept point

LO spurious emission at RF

Noise figure LNA and mixer (DSB)

LNA_IN input impedance

1 dB compression point (LNA, mixer, IF amplifier)

Maximum input level

= –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.

amb

Sleep mode (XTO and polling logic active)

off

190 350 µA

IC active (start-up, bit-check, receiving mode)

7.0 8.6 mA

pin DATA = H

LNA/mixer/IF amplifier input matched according to Figure 3-3 on page 6

IIP3 –28 dBm

Input matched according to Figure

3-3, required according to

LORF

–73 –57 dBm

I-ETS 300220 Input matching according to Figure

3-3

At 433.92 MHz At 315 MHz

Input matched according to Figure

3-3, referred to RF

NF 7 dB

LNA_IN

1db

1.0 || 1.56

1.3 || 1.0

–40 dBm

Input matched according to Figure

3-3,

BER ≤ 10

–3

ASK mode

in_max

–28 –20

kΩ || pF kΩ || pF

dBm dBm

4899B–RKE–10/06

Page 26

9. Electrical Characteristics (Continued)

All parameters refer to GND, T (VS = 5V, T

= 25°C)

amb

Parameters Test Conditions Symbol Min. Typ. Max. Unit Local Oscillator

Operating frequency range VCO f

Phase noise VCO/LO

Spurious of the VCO At ±f VCO gain K

Loop bandwidth of the PLL

Capacitive load at pin LF

XTO operating frequency

Series resonance resistor of the crystal

Static capacitance of the crystal C

Analog Signal Processing

Input sensitivity ASK 300-kHz IF filter

Input sensitivity ASK 300-kHz IF filter BR_Range0 –109 –111 –113 dBm Input sensitivity ASK 300-kHz IF filter BR_Range1 –107 –109 –111 dBm Input sensitivity ASK 300-kHz IF filter BR_Range2 –106 –108 –110 dBm Input sensitivity ASK 300-kHz IF filter BR_Range3 –104 –106 –108 dBm

Input sensitivity ASK 600-kHz IF filter

= –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.

amb

299 449 MHz

–113

–90

–110

dBC/Hz

dBC/Hz –55 –47 dBC 190 MHz/V

= 432.92 MHz

osc

At 1 MHz At 10 MHz

XTO

VCO

L (fm) –93

VCO

For best LO noise (design parameter) R1 = 820Ω

Loop

100 kHz

C9 = 4.7 nF C10 = 1 nF

The capacitive load at pin LF is limited if bit check is used. The limitation therefore also applies to

LF_tot

10 nF

self polling. XTO crystal frequency,

appropriate load capacitance must be connected to XTAL

6.764375 MHz

4.90625 MHz

= 6.764 MHz

XTO

4.906 MHz

XTO

xto

6.764375 –30 ppm

4.90625

–30 ppm

6.764375

4.90625

6.764375 +30 ppm

4.90625

+30 ppm

150 220

6.5 pF

Input matched according to Figure

3-3

ASK (level of carrier) BER ≤ 10–3, B = 300 kHz

Ref_ASK

fin = 433.92 MHz/315 MHz T = 25°C, VS = 5V

= 1 MHz

Input matched according to Figure

3-3

ASK (level of carrier) BER ≤ 10

–3

, B = 600 kHz

Ref_ASK

fin = 433.92 MHz/315 MHz T = 25°C, V

= 1 MHz

= 5V

MHz

Ω Ω

ATA3741

4899B–RKE–10/06

Page 27

ATA3741

9. Electrical Characteristics (Continued)

All parameters refer to GND, T (VS = 5V, T

= 25°C)

amb

Parameters Test Conditions Symbol Min. Typ. Max. Unit

Input sensitivity ASK 600-kHz IF filter BR_Range0 –108 –110 –112 dBm Input sensitivity ASK 600-kHz IF filter BR_Range1 –106.5 –108.5 –110.5 dBm Input sensitivity ASK 600-kHz IF filter BR_Range2 –106 –108 –110 dBm Input sensitivity ASK 600-kHz IF filter BR_Range3 –104 –106 –108 dBm

Sensitivity variation ASK for the full operating range compared to

= 25°C, VS=5V

amb

Sensitivity variation ASK for full operating range including IF filter compared to T

= 25°C, VS = 5V

amb

Sensitivity variation ASK for full operating range including IF filter compared to T

= 25°C, VS = 5V

amb

Input sensitivity FSK 600-kHz IF filter

Sensitivity variation FSK for the full operating range compared to T

= 25°C, VS=5V

amb

Sensitivity variation FSK for full operating range including IF filter compared to T

= 25°C, VS = 5V

amb

FSK frequency deviation

SNR to suppress inband noise signals

Dynamic range RSSI ampl. ∆R

= –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.

amb

300-kHz and 600-kHz version f

= 433.92 MHz/315 MHz

= 1 MHz

= P

ASK

Ref_ASK

+ ∆P

Ref

∆P

Ref

+2.5 –1.5 dB

300-kHz version f

= 433.92 MHz/315 MHz

= 0.88 MHz to 1.12 MHz

fIF = 0.85 MHz to 1.15 MHz P

ASK

= P

Ref_ASK

+ ∆P

Ref

∆P

Ref

+5.5 +7.5

–1.5 –1.5

600-kHz version fin = 433.92 MHz/315 MHz fIF = 0.79 MHz to 1.21 MHz fIF = 0.73 MHz to 1.27 MHz

= P

ASK

Ref_ASK

+ ∆P

Ref

∆P

Ref

+5.5 +7.5

–1.5 –1.5

Input matched according to Figure

3-3,

BER ≤ 10 f

–3

, B = 600 kHz

= 433.92 MHz/315 MHz

Ref_FSK

T = 25°C, VS = 5V

= 1 MHz

BR_Range0 df ≥ ±20 kHz df ≥ ±30 kHz

–95.5 –96.5

–97.5 –98.5

–99.5

–100.5

BR_Range1 df ≥ ±20 kHz df ≥ ±30 kHz

–94.5 –95.5

–96.5 –97.5

–98.5 –99.5

600-kHz version

= 433.92 MHz/315 MHz

= 1 MHz

= P

FSK

Ref_FSK

+ ∆P

Ref

∆P

Ref

+2.5 –1.5 dB

600-kHz version f

= 433.92 MHz/315 MHz

= 0.86 MHz to 1.14 MHz

= 0.82 MHz to 1.18 MHz

FSK

= P

Ref_FSK

+ ∆P

Ref

∆P

Ref

+5.5 +7.5

–1.5 –1.5

The sensitivity of the receiver is higher for higher values of ∆f BR_Range0 BR_Range1

FSK

∆f

FSK

20 20

30 30

50 BR_Range2 and BR_Range3 are not suitable for FSK operation

ASK mode FSK mode

SNR SNR

ASK

FSK

RSSI

60 dB

dB dB

dBm dBm

dB dB

kHz kHz

dB dB

4899B–RKE–10/06

Page 28

9. Electrical Characteristics (Continued)

All parameters refer to GND, T (VS = 5V, T

= 25°C)

amb

Parameters Test Conditions Symbol Min. Typ. Max. Unit

= –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.

amb

Lower cut-off frequency of the data filter

Recommended CDEM for best performance

Maximum edge-to-edge time period of the input data signal for full sensitivity

Upper cut-off frequency data filter

Minimum edge-to-edge time period of the input data signal for full sensitivity

Reduced sensitivity

Reduced sensitivity variation over full operating range

cu_DF

-------------------------------------------------------------=

2 π× 30 kΩ× CDEM×

ASK mode BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3

FSK mode BR_Range0 (Default) BR_Range1 BR_Range2 and BR_Range3 are not suitable for FSK operation

BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3

Upper cut-off frequency programmable in 4 ranges via a serial mode word BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3

BR_Range0 (Default) BR_Range1 BR_Range2 BR_Range3

connected from pin SENS to

Sense

input matched according to

Figure 3-3

= 56 kΩ, fin= 433.92 MHz,

Sense

=5V, T

amb

= 25°C) At B = 300 kHz At B = 600 kHz

= 100 kΩ, fin = 433.92 MHz

Sense

At B = 300 kHz At B = 600 kHz

= 56 kΩ, fin = 315 MHz

Sense

At B = 300 kHz At B = 600 kHz

= 100 kΩ, fin = 315 MHz

Sense

At B = 300 kHz At B = 600 kHz

= 56 kΩ

Sense

= 100 kΩ

Sense

Red

= P

Ref_Red

+ DP

Red

cu_DF

0.11 0.16 0.20 kHz

CDEM

CDEM 27

ee_sig

2.5

4.3

7.6

ee_sig

Ref_Red

13.6

17.0

–71 –67

–80 –76

–72 –68

–81 –77

∆P

Red

39 22 12

8.2

3.1

5.4

9.5

–76 –72

–85 –81

–77 –73

–86 –82

0 0

1000

560 320 180

3.7

6.5

11.4

20.4 270

156

89 50

–81 –77

–90 –86

–82 –78

–91 –87

0 0

nF nF nF nF

nF nF

µs µs µs µs

kHz kHz kHz kHz

µs µs µs µs

dBm

(peak

level)

dBm dBm

dB dB

ATA3741

4899B–RKE–10/06

Page 29

ATA3741

9. Electrical Characteristics (Continued)

All parameters refer to GND, T (VS = 5V, T

= 25°C)

amb

Parameters Test Conditions Symbol Min. Typ. Max. Unit

= –40°C to +105°C, VS = 4.5V to 5.5V, f0 = 433.92 MHz and f0 = 315 MHz, unless otherwise specified.

amb

Values relative to R

= 56 kΩ

Sense

= 56 kΩ

R Reduced sensitivity variation for different values of R

Sense

Sense Sense Sense Sense Sense Sense Red

= 68 kΩ = 82 kΩ = 100 kΩ = 120 kΩ = 150 kΩ

= P

Ref_Red

+ ∆P

Red

Threshold voltage for reset V

Digital Ports

Data output

- Saturation voltage LOW

- Internal pull-up resistor

- Maximum time constant

- Maximum capacitive load

= 1 mA

//R

t = C

pup

Ext

) without external pull-up resistor R

= 5 kΩ

ext

POUT output

- Saturation voltage LOW

- Saturation voltage HIGH

POUT

= 1 mA = –1 mA

FSK/ASK input

- Low-level input voltage

- High-level input voltage

FSK selected ASK selected

ENABLE input

- Low-level input voltage

- High-level input voltage

Idle mode Active mode

MODE input

- Low-level input voltage

- High-level input voltage TEST input

- Low-level input voltage

Division factor = 10 Division factor = 14

Test input must always be set to LOW

∆P

Red

ThReset

Pup

0 –3.5 –6.0 –9.0

–11.0 –13.5

1.95 2.8 3.75 V

0.08

0.3 61

2.5 41

540

VS – 0.3V

0.8 × V

0.08

VS–0.14V

0.3 V

0.2 × V

dB dB dB dB dB dB

kΩ µs pF pF

V V

4899B–RKE–10/06

Page 30

10. Ordering Information

Extended Type Number Package Remarks

ATA3741P2-TGSY SO20 2: IF bandwidth of 300 kHz, tube, Pb-free ATA3741P2-TGQY SO20 2: IF bandwidth of 300 kHz, taped and reeled, Pb-free ATA3741P3-TGSY SO20 3: IF bandwidth of 600 kHz, tube, Pb-free ATA3741P3-TGQY SO20 3: IF bandwidth of 600 kHz, taped and reeled, Pb-free

11. Package Information

Package SO20

Dimensions in mm

0.4

1.27

20 11

12.95

12.70

11.43

0.25

0.10

2.35

technical drawings according to DIN specifications

9.15

8.65

7.5

7.3

0.25

10.50

10.20

110

12. Revision History

Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document.

Revision No. History

4899B-RKE-10/06 • Put datasheet in a new template

ATA3741

4899B–RKE–10/06

Page 31

Atmel Corporation Atmel Operations

2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600

Regional Headquarters

Europe

Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel: (41) 26-426-5555 Fax: (41) 26-426-5500

Asia

Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel: (852) 2721-9778 Fax: (852) 2722-1369

Japan

9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel: (81) 3-3523-3551 Fax: (81) 3-3523-7581

Memory

2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314

Microcontrollers

2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 436-4314

La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel: (33) 2-40-18-18-18 Fax: (33) 2-40-18-19-60

ASIC/ASSP/Smart Cards

Zone Industrielle 13106 Rousset Cedex, France Tel: (33) 4-42-53-60-00 Fax: (33) 4-42-53-60-01

1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759

Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel: (44) 1355-803-000 Fax: (44) 1355-242-743

RF/Automotive

Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel: (49) 71-31-67-0 Fax: (49) 71-31-67-2340

1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel: 1(719) 576-3300 Fax: 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/ High-Speed Converters/RF Datacom

Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel: (33) 4-76-58-30-00 Fax: (33) 4-76-58-34-80

Literature Requests

www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no

representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.

© 2006 Atmel Corporation. All rights reserved. Atmel®, logo and combinations thereof, Everywhere You Are® and others are registered trade- marks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

4899B–RKE–10/06