Datasheet 89C1632RPQK30, 89C1632RPQK25, 89C1632RPQK20, 89C1632RPQI30, 89C1632RPQI25 Datasheet (MAXWELL)

1

Memory

All data sheets are subject to change without notice

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16 Megabit (512K x 32-Bit)

89C1632

©2001 Maxwell Technologies.

All rights reserved.

MCM SRAM

12.20.01 Rev 1

1000558

FEATURES:

• Four 512k x 8 SRAM architecture

•R

AD-PAK® technology hardens against natural space radia-

tion technology

• Total dose hardness:

- > 100 krad (Si), depending upon space mission

• Excellent Single Event Effects:

- SEL > 68 MeV/mg/cm

2

- SEU threshold = 3 MeV/mg/cm

2

- SEU saturated cross section: 6E-9 cm2/bit

• Package: 68-pin quad flat package

• Fast access time: 20, 25 and 30 ns

• Completely static memory - no clock or timing strobe
required

• Internal bypass capacitor

• High-speed silicon-gate CMOS technology

• 5V or 3V ± 10% power supply

• Equal address and chip enable access times

• Three-state outputs

• All inputs and outputs are TTL compatible

DESCRIPTION:

Maxwell Technologies’ 89C1632 high-performance 16 Mega­bit Multi-Chip Module (MCM) Static Random Access Memory
features a greater than 100 krad (Si) total dose tolerance,
depending upon space mission. The four 4-Megabyte SRAM
die and bypass capacitors are incorporated into a high-reliable
hermetic quad flat-pack ceramic package. With high-perfor­mance silicon-gate CMOS technology, the 89C1632 reduces
power consumption and eliminates the need for external
clocks or timing strobes. It is equipped with output enable
(OE

) and four byte enable (CS1 - CS4) inputs to allow greater

system flexibility. When OE

input is high, the output is forced

to high impedance.

Maxwell Technologies' patented R

AD-PAK® packaging technol-

ogy incorporates radiation shielding in the microcircuit pack­age. In a GEO orbit, R

AD-PAK provides true greater than 100

krad (Si) total radiation dose tolerance, dependent upon space
mission. It eliminates the need for box shielding while provid­ing the required radiation shielding for a lifetime in orbit or a
space mission. This product is available in Class H or Class K
packaging and screening.

CS 1-4

MCM

OE, WE

Address

4Mb SRAM 4Mb SRAM 4Mb SRAM 4Mb SRAM

Power Ground

I/O 0-7 I/O 8-15 I/O 16-23 I/O 24-31

16 Megabit (512k x 32-bit) SRAM MCM

Logic Diagram

Memory

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All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

16 Megabit (512K x 32-Bit) MCM SRAM

89C1632

12.20.01 Rev 1

1000558

TABLE 1. PINOUT DESCRIPTION

PIN SYMBOL DESCRIPTION

34-28, 42-36, 62-64, 7, 8 A0-A18 Address Enable

65 WE

WriteEnable

66 OE

Output Enable

3-6 CS1

- CS4 Chip Enable

43-46, 48-56, 58-61, 9-12,

14-17, 19-22, 24-27

I/O0-I/O31 Data Input/Output

2, 67, 68 NC No Connection

1, 18, 35, 52 V

CC

+5V Power Supply

13, 23, 47, 57 V

SS

Ground

TABLE 2. 89C1632 ABSOLUTE MAXIMUM RATINGS

(VOLTAGE REFERENCED TO VSS = 0V)

P

ARAMETER SYMBOL MIN MAX UNITS

Power Supply Voltage Relative to V

SS

V

CC

-0.5 +7.0 V

Voltage Relative to V

SS

for Any Pin Except V

CC

VIN, V

OUT

-0.5 VCC+0.5 V

Power Dissipation P

D

-- 4.0 W

Operating Temperature T

A

-55 +125

°

C

Storage Temperature T

S

-65 +150

°

C

TABLE 3. 89C1632 RECOMMENDED OPERATING CONDITIONS

(VCC = 5.0 + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE NOTED)

P

ARAMETER SYMBOL MIN MAX UNITS

Supply Voltage, (Operating Voltage Range) V

CC

4.5 5.5 V

Input High Voltage V

IH

2.2 VCC + 0.5

(1)

1. VIH (max) = VCC + 2V ac (pulse width < 10ns) for I < 80 mA.

V

Input Low Voltage V

IL

-0.5

(2)

2. VIL (min) = -2.0V ac; (pulse width < 20 ns) for I < 80 mA.

0.8 V

Memory

3

All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

16 Megabit (512K x 32-Bit) MCM SRAM

89C1632

12.20.01 Rev 1

1000558

TABLE 4. 89C1632 CAPACITANCE

(f = 1.0 MHZ, dV = 3.0V, TA = 25 °C)

P

ARAMETER SYMBOL TEST CONDITIONS MAX UNITS

Input Capacitance

1

CS1 - CS4,
OE

, WE

I/O0-7, I/O8-15, I/O16-23, I/O24-31

1. Guaranteed by design.

C

IN

V

IN

= 0 V

7

28

7

pF

Input / Output Capacitance

1

C

OUT

V

I/O

= 0 V 8 pF

TABLE 5. 89C1632 DC ELECTRICAL CHARACTERISTICS

(VCC = 5.0 + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE NOTED)

P

ARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS

Input Leakage Current I

LI

VIN = 0 to V

CC

-8.0 -- +8.0 uA

Output Leakage Current I

LO

CS = VIH, V

OUT

= VSS to V

CC

-8.0 -- +8.0 uA

Average Operating Current
Cycle Time:

20 ns
25 ns
30 ns

I

CC

Min. Cycle, 100% Duty, CS = VIL, I

OUT

= 0 mA
V

IN

= VIH or V

IL

--

--

--

--

800
760
720

mA

Standby Power Supply Current I

SB

CS= VIH, cycle time > 25ns -- -- 240 mA

CMOS Standby Power Supply
Current

I

SB1

CS > VCC - 0.2V, f = 0 MHz, VIN > VCC

- 0.2V or
V

IN <

0.2V

-- -- 60 mA

Output Low Voltage V

OLIOL

= + 8.0 mA -- -- 0.4 V

Output High Voltage V

OHIOH

= -4.0 mA 2.4 -- -- V

TABLE 6. 89C1632 AC OPERATING CONDITIONS AND CHARACTERISTICS

(VCC = 5.0 + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE NOTED)

P

ARAMETER MIN TYP MAX UNITS

Input Pulse Level 0.0 -- 3.0 V

Output Timing Measurement Reference Level -- -- 1.5 V

Input Rise/Fall Time -- -- 3.0 ns

Input Timing Measurement Reference Level -- -- 1.5 V

Memory

4

All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

16 Megabit (512K x 32-Bit) MCM SRAM

89C1632

12.20.01 Rev 1

1000558

TABLE 7. 89C1632 READ CYCLE

(VCC = 5.0 + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE NOTED)

P

ARAMETER SYMBOL MIN TYP MAX UNITS

Read Cycle Time

-20

-25

-30

t

RC

20
25
30

--

--

--

--

--

--

ns

Address Access Time

-20

-25

-30

t

AA

--

--

--

--

--

--

20
25
30

ns

Chip Select to Output

-20

-25

-30

t

CO

--

--

--

--

--

--

20
25
30

ns

Output Enable to Output

-20

-25

-30

t

OE

--

--

--

--

--

--

10
12
14

ns

Output Enable to Low-Z Output

-20

-25

-30

t

OLZ

--

--

--

0
0
0

--

--

--

ns

Chip Enable to Low-Z Output

-20

-25

-30

t

LZ

--

--

--

3
3
3

--

--

--

ns

Output Disable to High-Z Output

-20

-25

-30

t

OHZ

--

--

--

5
6
8

--

--

--

ns

Chip Disable to High-Z Output

-20

-25

-30

t

HZ

--

--

--

5
6
8

--

--

--

ns

Output Hold from Address Change

-20

-25

-30

t

OH

3
3
3

--

--

--

--

--

--

ns

TABLE 8. 89C1632 FUNCTIONAL DESCRIPTION

CS WE OE MODE I/O PIN SUPPLY CURRENT

HX1X

1

Not Select High-Z ISB, I

SB1

Memory

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All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

16 Megabit (512K x 32-Bit) MCM SRAM

89C1632

12.20.01 Rev 1

1000558

L H H Output Disable High-Z I

CC

L H L Read D

OUT

I

CC

LLX1Write D

IN

I

CC

1. X = don’t care.

TABLE 9. 89C1632 WRITE CYCLE

(VCC = 5.0 + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE NOTED)

P

ARAMETER SYMBOL MIN TYP MAX UNITS

Write Cycle Time

-20

-25

-30

t

WC

20
25
30

--

--

--

ns

Chip Select to End of Write

-20

-25

-30

t

CW

14
17
20

--

--

--

ns

Address Set-up Time

-20

-25

-30

t

AS

0
0
0

--

--

--

ns

Address Valid to End of Write

-20

-25

-30

t

AW

14
17
20

--

--

--

ns

Write Pulse Width (OE

High)

-20

-25

-30

t

WP

14
17
20

--

--

--

ns

Write Pulse Width (OE

Low)

-20

-25

-30

t

WP1

20
25
30

--

--

--

ns

Write Recovery Time

-20

-25

-30

t

WR

0
0
0

--

--

--

ns

Write to Output High-Z

-20

-25

-30

t

WHZ

--

--

--

5
7
9

--

--

--

ns

TABLE 8. 89C1632 FUNCTIONAL DESCRIPTION

CS WE OE MODE I/O PIN SUPPLY CURRENT

Memory

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All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

16 Megabit (512K x 32-Bit) MCM SRAM

89C1632

12.20.01 Rev 1

1000558

Data to Write Time Overlap

-25

-30

t

DW

10
12
14

--

--

--

ns

Data Hold from Write Time

-20

-25

-30

t

DH

0
0
0

--

--

--

ns

End Write to Output Low-Z

-20

-25

-30

t

OW

--

--

--

3
3
3

--

--

--

ns

TABLE 9. 89C1632 WRITE CYCLE

(VCC = 5.0 + 10%, TA = -55 TO +125 °C, UNLESS OTHERWISE NOTED)

P

ARAMETER SYMBOL MIN TYP MAX UNITS

Memory

7

All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

16 Megabit (512K x 32-Bit) MCM SRAM

89C1632

12.20.01 Rev 1

1000558

FIGURE 1. AC TEST LOADS

FIGURE 2. TIMING WAVEFORM OF READ CYCLE

(1)

(ADDRESS CONTROLLED)

F

IGURE 3. TIMING WAVEFORM OF READ CYCLE

(2)

(WE = VIH)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

Memory

8

All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

16 Megabit (512K x 32-Bit) MCM SRAM

89C1632

12.20.01 Rev 1

1000558

3. tHZ and t

OHZ

are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or

V

OL

levels.

4. At any given temperature and voltage conditions, t

HZ

(max) is less than tLZ (min) both for a given device and from device to

device.

5. Transition is measured +

200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

6. Device is continuously selected with CS

= VIL.

7. Address valid prior to coincident with CS

transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
cycle.

FIGURE 4. TIMING WAVEFORM OF WRITE CYCLE

(1)

(OE CLOCK)

F

IGURE 5. TIMING WAVEFORM OF WRITE CYCLE

(2)

(OE LOW FIIXED)

Memory

9

All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

16 Megabit (512K x 32-Bit) MCM SRAM

89C1632

12.20.01 Rev 1

1000558

FIGURE 6. TIMING WAVEFORM OF WRITE CYCLE

(3)

(CS CONTROLLED)

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CS

and WE. A write begins at the latest transition CS going low and WE going low.

A write ends at the earliest transition CS

going high or WE going high. tWP is measured from the beginning of write to the end

of write.

3. t

CW

is measured from the later of CS going low to end of write.

4. t

AS

is measured from the address valid to the beginning of write.

5. t

WR

is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

6. If OE

, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase

of the output must not be applied because bus contention can occur.

7. For common I/O applications, minimization of elimination of bus contention conditions is necessary during read and write
cycle.

8. If CS

foes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.

9. D

OUT

is the read data of the new address.

10.When CS

is low, I/O pins are in the output state. The input signals in the opposite phase leading to the output should not

be applied.

Memory

10

All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

16 Megabit (512K x 32-Bit) MCM SRAM

89C1632

12.20.01 Rev 1

1000558

FIGURE 7. SRAM HEAVY ION CROSS SECTION

FIGURE 8. SRAM PROTON SEU CROSS SECTION STATIC

Memory

11

All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

16 Megabit (512K x 32-Bit) MCM SRAM

89C1632

12.20.01 Rev 1

1000558

Q68-04

Note: All dimensions in inches

68 PIN RAD-PAK® QUAD FLAT PACKAGE

SYMBOL

DIMENSION

MIN NOM MAX

A 0.206 0.225 0.244

b 0.015 0.017 0.018

c 0.008 0.009 0.12

D 1.479 1.494 1.509

D1 0.800

e 0.050 BSC

S1 -- 0.339 --

F1 1.239 1.244 1.249

F2 1.429 1.434 1.439

L 2.485 2.510 2.545

L1 2.485 2.500 2.505

L2 1.690 1.700 1.710

A1 0.180 0.195 0.210

N68

Memory

12

All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

16 Megabit (512K x 32-Bit) MCM SRAM

89C1632

12.20.01 Rev 1

1000558

Important Notice:

These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.

The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.

Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.

Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech­nologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.

Memory

13

All data sheets are subject to change without notice

©2001 Maxwell Technologies.

All rights reserved.

16 Megabit (512K x 32-Bit) MCM SRAM

89C1632

12.20.01 Rev 1

1000558

Product Ordering Options

Model Number

Feature

Option Details

89C1632

RP

Q X

-XX

Access Time

Screening Flow

Package

Radiation Feature

Base Product
Nomenclature

20 = 20 ns
25 = 25 ns
30 = 30 ns

Multi Chip Module (MCM)
K = Maxwell Class K
H = Maxwell Class H
E = Engineering (testing @ +25°C

)

I = Industrial (testing @ -55°C,
+25°C, +125°C)

Q = Quad Flat Pack

RP = R

AD-PAK® package

16 Megabit (512K x 32-Bit) MCM
SRAM