Page 1
INTEGRATED CIRCUITS
NOTICE
PLEASE SEE THE P87C552 DA TA SHEET FOR NEW DESIGN-INS
87C552
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM,
capture/compare, high I/O
Product specification
Supersedes data of 1998 Jan 19
IC20 Data Handbook
1998 May 01
Page 2
Philips Semiconductors Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
DESCRIPTION
The 87C552 Single-Chip 8-Bit Microcontroller is manufactured in an
advanced CMOS process and is a derivative of the 80C51
microcontroller family. The 87C552 has the same instruction set as
the 80C51. Three versions of the derivative exist:
•83C552—8k bytes mask programmable ROM
•80C552—ROMless version of the 83C552
•87C552—8k bytes EPROM
The 87C552 contains a 8k × 8 a volatile 256 × 8 read/write data
memory, five 8-bit I/O ports, one 8-bit input port, two 16-bit
timer/event counters (identical to the timers of the 80C51), an
additional 16-bit timer coupled to capture and compare latches, a
15-source, two-priority-level, nested interrupt structure, an 8-input
ADC, a dual DAC pulse width modulated interface, two serial
interfaces (UART and I
oscillator and timing circuits. For systems that require extra
capability , the 87C552 can be expanded using standard TTL
compatible memories and logic.
In addition, the 87C552 has two software selectable modes of power
reduction—idle mode and power-down mode. The idle mode freezes
the CPU while allowing the RAM, timers, serial ports, and interrupt
system to continue functioning. The power-down mode saves the
RAM contents but freezes the oscillator, causing all other chip
functions to be inoperative.
The device also functions as an arithmetic processor having
facilities for both binary and BCD arithmetic plus bit-handling
capabilities. The instruction set consists of over 100 instructions: 49
one-byte, 45 two-byte, and 17 three-byte. With a 16MHz crystal,
58% of the instructions are executed in 0.75µs and 40% in 1.5µs.
Multiply and divide instructions require 3µs.
2
C-bus), a “watchdog” timer and on-chip
FEATURES
•80C51 central processing unit
•8k × 8 EPROM expandable externally to 64k bytes
•An additional 16-bit timer/counter coupled to four capture registers
and three compare registers
•Two standard 16-bit timer/counters
•256 × 8 RAM, expandable externally to 64k bytes
•Capable of producing eight synchronized, timed outputs
•A 10-bit ADC with eight multiplexed analog inputs
•Two 8-bit resolution, pulse width modulation outputs
•Five 8-bit I/O ports plus one 8-bit input port shared with analog
inputs
2
•I
C-bus serial I/O port with byte oriented master and slave
functions
•Full-duplex UART compatible with the standard 80C51
•On-chip watchdog timer
•16MHz speed
•Extended temperature ranges
•OTP package available
87C552
ORDERING INFORMATION
EPROM TEMPERATURE °C AND PACKAGE
S87C552-4A68 0 to +70, Plastic Leaded Chip Carrier 16 SOT188-3
S87C552-4BA 0 to +70, Plastic Quad Flat Pack 16 SOT318-2
S87C552-5A68 –40 to +85, Plastic Leaded Chip Carrier 16 SOT188-3
NOTE:
1. For ROM and ROMless see data sheet 80C552/83C552
1998 May 01 853-1690 19336
2
FREQ
MHz
DRAWING NUMBER
Page 3
Philips Semiconductors Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
BLOCK DIAGRAM
T0 T1 INT0 INT1
XTAL1
XTAL2
EA
ALE
PSEN
3
3
0
WR
RD
3 3 3 3
T0, T1
TWO 16-BIT
TIMER/EVENT
COUNTERS
80C51 CORE
EXCLUDING
ROM/RAM
CPU
V
DD
PROGRAM
MEMORY
8k x 8
EPROM
16
8-BIT INTERNAL BUS
V
SS
DATA
MEMORY
256 x 8 RAM
PWM0 PWM1
DUAL
PWM
87C552
AV
REF
–+
ADC
STADC
ADC0-7 SDA SCL
SERIAL
2
I
C PORT
115
AV
SS
AV
DD
AD0-7
2
A8-15
0
ALTERNATE FUNCTION OF PORT 0
1
ALTERNATE FUNCTION OF PORT 1
2
ALTERNATE FUNCTION OF PORT 2
PARALLEL I/O
PORTS AND
EXTERNAL BUS
P0 P1 P2 P3 TxD RxD P5 P4 CT0I-CT3I T2 RT2 CMSR0-CMSR5
SERIAL
UART
PORT
3 3
3
ALTERNATE FUNCTION OF PORT 3
4
ALTERNATE FUNCTION OF PORT 4
5
ALTERNATE FUNCTION OF PORT 5
8-BIT
PORT
16
T2
16-BIT
COMPARA-
TORS
WITH
REGISTERS
FOUR
16-BIT
CAPTURE
LATCHES
1 1 1 4
T2
16-BIT
TIMER/
EVENT
COUNTERS
COMPARA-
TOR
OUTPUT
SELECTION
CMT0, CMT1
T3
WATCHDOG
TIMER
RST EW
SU00211
1998 May 01
3
Page 4
Philips Semiconductors Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
LOGIC SYMBOL
V
SS
V
DD
XTAL1
XTAL2
V
EA/
PP
ALE/PROG
PSEN
AV
SS
AV
DD
AVref+
AVref–
STADC
PWM0
PWM1
ADC0-7
PORT 5
CMSR0-5
RST
EW
PORT 4
CMT0
CMT1
PORT 0
PORT 1PORT 2PORT 3
RxD/DATA
TxD/CLOCK
ADDRESS AND
CT0I
CT1I
CT2I
CT3I
T2
RT2
SCL
SDA
HIGH ORDER
ADDRESS AND
DATA BUS
INT0
INT1
T0
T1
WR
RD
LOW ORDER
DATA BUS
SU00210
PIN CONFIGURATIONS
Pin Function
1 P5.0/ADC0
2V
3 STADC
4 PWM0
5 PWM1
6EW
7 P4.0/CMSR0
8 P4.1/CMSR1
9 P4.2/CMSR2
10 P4.3/CMSR3
11 P4.4/CMSR4
12 P4.5/CMSR5
13 P4.6/CMT0
14 P4.7/CMT1
15 RST
16 P1.0/CT0I
17 P1.1/CT1I
18 P1.2/CT2I
19 P1.3/CT3I
20 P1.4/T2
21 P1.5/RT2
22 P1.6/SCL
23 P1.7/SDA
87C552
9161
10
PLASTIC
LEADED
CHIP CARRIER
26
Pin Function
24 P3.0/RxD
DD
25 P3.1/TxD
26 P3.2/INT0
27 P3.3/INT1
28 P3.4/T0
29 P3.5/T1
30 P3.6/WR
31 P3.7/RD
32 NC
33 NC
34 XTAL2
35 XTAL1
36 V
SS
37 V
SS
38 NC
39 P2.0/A08
40 P2.1/A09
41 P2.2/A10
42 P2.3/A11
43 P2.4/A12
44 P2.5/A13
45 P2.6/A14
46 P2.7/A15
60
44
4327
Pin Function
47 PSEN
48 ALE/PROG
49 EA/V
50 P0.7/AD7
51 P0.6/AD6
52 P0.5/AD5
53 P0.4/AD4
54 P0.3/AD3
55 P0.2/AD2
56 P0.1/AD1
57 P0.0/AD0
58 AVref–
59 AVref+
60 AV
61 AV
62 P5.7/ADC7
63 P5.6/ADC6
64 P5.5/ADC5
65 P5.4/ADC4
66 P5.3/ADC3
67 P5.2/ADC2
68 P5.1/ADC1
PP
SS
DD
SU00208
PLASTIC QUAD FLAT PACK PIN FUNCTIONS
Pin Function
1 P4.1/CMSR1
2 P4.2/CMSR2
80 65
1
PQFP
24
25 40
64
41
3NC
4 P4.3/CMSR3
5 P4.4/CMSR4
6 P4.5/CMSR5
7
8 P4.7/CMT1
9 RST
10 P1.0/CT0I
11 P1.1/CT1I
12 P1.2/CT2I
13
14 P1.4/T2
15 P1.5/RT2
16 P1.6/SCL
17 P1.7/SDA
18 P3.0/RxD
19 P3.1/TxD
20 P3.2/INT0
NC = Not Connected
IC = Internally Connected (do not use)
P4.6/CMT0
P1.3/CT3I
Pin Function
21 NC
22 NC
23 P3.3/INT1
24 P3.4/T0
25 P3.5/T1
26 P3.6/WR
27 P3.7/RD
28 NC
29 NC
30 NC
31 XTAL2
32 XTAL1
33 IC
34 V
SS
35 V
SS
36 V
SS
37 NC
38 P2.0/A08
39 P2.1/A09
40 P2.2/A10
Pin Function
41 P2.3/A11
42 P2.4/A12
43 NC
44 NC
45 P2.5/A13
46 P2.6/A14
47 P2.7/A15
48 PSEN
49 ALE/PROG
50 EA/V
51 P0.7/AD7
52 P0.6/AD6
53 P0.5/AD5
54 P0.4/AD4
55 P0.3/AD3
56 P0.2/AD2
57
58 P0.0/AD0
59 AVref–
60 AVref+
PP
P0.1/AD1
Pin Function
61 AV
SS
62 NC
63 AV
DD
64 P5.7/ADC7
65 P5.6/ADC6
66 P5.5/ADC5
67 P5.4/ADC4
68 P5.3/ADC3
69 P5.2/ADC2
70 P5.1/ADC1
71 P5.0/ADC0
72 V
DD
73 IC
74 STADC
75 PWM0
76 PWM1
77 EW
78 NC
79 NC
80 P4.0/CMSR0
SU00209
1998 May 01
4
Page 5
Philips Semiconductors Product specification
80C51 8-bit microcontroller
87C552
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
PIN DESCRIPTION
PIN NO.
MNEMONIC PLCC QFP TYPE NAME AND FUNCTION
V
DD
STADC 3 74 I Start ADC Operation: Input starting analog to digital conversion (ADC operation can also
PWM0 4 75 O Pulse Width Modulation: Output 0.
PWM1 5 76 O Pulse Width Modulation: Output 1.
EW 6 77 I Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode.
P0.0-P0.7 57-50 58-51 I/O Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written
P1.0-P1.7 16-23 10-17 I/O Port 1: 8-bit I/O port. Alternate functions include:
P2.0-P2.7 39-46 38-42,
P3.0-P3.7 24-31 18-20,
P4.0-P4.7 7-14 80, 1-2
P5.0-P5.7 68-62, 71-64, I Port 5: 8-bit input port.
RST 15 9 I/O Reset: Input to reset the 87C552. It also provides a reset pulse as output when timer T3
XTAL1 35 32 I Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the
XTAL2 34 31 O Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit
V
SS
PSEN 47 48 O Program Store Enable: Active-low read strobe to external program memory.
2 72 I Digital Power Supply: +5V power supply pin during normal operation, idle and
16-21 10-15 I/O (P1.0-P1.5): Quasi-bidirectional port pins.
22-23 16-17 I/O (P1.6, P1.7): Open drain port pins.
16-19 10-13 I CT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2.
20 14 I T2 (P1.4): T2 event input.
21 15 I RT2 (P1.5): T2 timer reset signal. Rising edge triggered.
22 16 I/O SCL (P1.6): Serial port clock line I2C-bus.
23 17 I/O SDA (P1.7): Serial port data line I2C-bus.
45-47
23-27
24 18 RxD(P3.0): Serial input port.
25 19 TxD (P3.1): Serial output port.
26 20 INT0 (P3.2): External interrupt.
27 23 INT1 (P3.3): External interrupt.
28 24 T0 (P3.4): Timer 0 external input.
29 25 T1 (P3.5): Timer 1 external input.
30 26 WR (P3.6): External data memory write strobe.
31 27 RD (P3.7): External data memory read strobe.
4-8
7-12 80, 1-2
4-6
13, 14 7, 8 O CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2.
1 ADC0-ADC7 (P5.0-P5.7): Alternate function: Eight input channels to ADC.
36, 37 34-36 I Digital ground.
power-down mode.
be started by software).
to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application it uses strong internal pull-ups when emitting 1s. Port 0 is also used to input
the code byte during programming and to output the code byte during verification.
Port 1 is also used to input the lower order address byte during EPROM programming and
verification. A0 is on P1.0, etc.
I/O Port 2: 8-bit quasi-bidirectional I/O port.
Alternate function: High-order address byte for external memory (A08-A15). Port 2 is also
used to input the upper order address during EPROM programming and verification. A8 is
on P2.0, A9 on P2.1, through A12 on P2.4.
I/O Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include:
I/O Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include:
O CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with
timer T2.
overflows.
internal clock generator. Receives the external clock signal when an external oscillator is
used.
when an external clock is used.
1998 May 01
5
Page 6
Philips Semiconductors Product specification
80C51 8-bit microcontroller
87C552
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
PIN DESCRIPTION (Continued)
PIN NO.
MNEMONIC PLCC QFP TYPE NAME AND FUNCTION
ALE/PROG 48 49 O Address Latch Enable: Latches the low byte of the address during accesses to external
EA/V
PP
AV
REF–
AV
REF+
AV
SS
AV
DD
NOTE:
1. To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than V
respectively.
49 50 I External Access: When EA is held at TTL level high, the CPU executes out of the internal
58 59 I Analog to Digital Conversion Reference Resistor: Low-end.
59 60 I Analog to Digital Conversion Reference Resistor: High-end.
60 61 I Analog Ground
61 63 I Analog Power Supply
memory. It is activated every six oscillator periods. During an external data memory
access, one ALE pulse is skipped. ALE can drive up to eight LS TTL inputs and handles
CMOS inputs without an external pull-up. This pin is also the program pulse input (PROG
during EPROM programming.
program ROM provided the program counter is less than 8192. When EA
low level, the CPU executes out of external program memory. EA
This pin also receives the 12.75V programming supply voltage (V
programming.
+ 0.5V or VSS – 0.5V,
DD
is held at TTL
is not allowed to float.
) during EPROM
PP
)
OSCILLA T OR CHARACTERISTICS
XTAL1 and XTAL2 are the input and output, respectively , of an
inverting amplifier . The pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol.
To drive the device from an external clock source, XTAL1 should be
driven while XTAL2 is left unconnected. There are no requirements
on the duty cycle of the external clock signal, because the input to
the internal clock circuitry is through a divide-by-two flip-flop.
However, minimum and maximum high and low times specified in
the data sheet must be observed.
RESET
A reset is accomplished by holding the RST pin high for at least two
machine cycles (24 oscillator periods), while the oscillator is running.
To insure a good power-on reset, the RST pin must be high long
enough to allow the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At power-on, the voltage on
V
and RST must come up at the same time for a proper start-up.
DD
IDLE MODE
In the idle mode, the CPU puts itself to sleep while some of the
on-chip peripherals stay active. The instruction to invoke the idle
mode is the last instruction executed in the normal operating mode
before the idle mode is activated. The CPU contents, the on-chip
RAM, and all of the special function registers remain intact during
this mode. The idle mode can be terminated either by any enabled
interrupt (at which time the process is picked up at the interrupt
service routine and continued), or by a hardware reset which starts
the processor in the same manner as a power-on reset.
POWER-DOWN MODE
In the power-down mode, the oscillator is stopped and the
instruction to invoke power-down is the last instruction executed.
Only the contents of the on-chip RAM are preserved. A hardware
reset is the only way to terminate the power-down mode. The control
bits for the reduced power modes are in the special function register
PCON. Table 1 shows the state of the I/O ports during low current
operating modes.
Table 1. External Pin Status During Idle and Power-Down Modes
MODE
Idle Internal 1 1 Data Data Data Data Data High
Idle External 1 1 Float Data Address Data Data High
Power-down Internal 0 0 Data Data Data Data Data High
Power-down External 0 0 Float Data Data Data Data High
PROGRAM
MEMORY
ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 PORT 4
PWM0/
PWM1
1998 May 01
6
Page 7
Philips Semiconductors Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
Serial Control Register (S1CON) – See Table 2
S1CON (D8H)
CR2 ENS1 STA STO SI AA CR1 CR0
Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.
Table 2. Serial Clock Rates
BIT FREQUENCY (kHz) AT f
CR2 CR1 CR0 6MHz 12MHz 16MHz f
0 0 0 23 47 62.5 256
0 0 1 27 54 71 224
0 1 0 31.25 62.5 83.3 192
0 1 1 37 75 100 160
1 0 0 6.25 12.5 17 960
1 0 1 50 100 133
1 1 0 100 200 267
1 1 1 0.25 < 62.5 0.5 < 62.5 0.67 < 56 96 × (256 – (reload value Timer 1))
0 to 225 0 to 224 0 to 223 Timer 1 in Mode 2.
NOTE:
1. These frequencies exceed the upper limit of 100kHz of the I
2
C-bus specification and cannot be used in an I2C-bus application.
OSC
DIVIDED BY
OSC
1
1
120
60
87C552
ABSOLUTE MAXIMUM RATINGS
Storage temperature range –65 to +150 °C
Voltage on EA/VPP to V
Voltage on any other pin to V
Input, output DC current on any single I/O pin 5.0 mA
Power dissipation (based on package heat transfer limitations, not device power
consumption)
NOTES:
1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.
2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.
3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V
noted.
SS
SS
1, 2, 3
PARAMETER
RATING UNIT
–0.5 to +13 V
–0.5 to +6.5 V
1.0 W
unless otherwise
SS
DEVICE SPECIFICATIONS
SUPPLY VOLTAGE (V) FREQUENCY (MHz)
TYPE MIN MAX MIN MAX TEMPERATURE RANGE (°C)
P87C552-4 4.5 5.5 3.5 16 0 to +70
P87C552-5 4.5 5.5 3.5 16 –40 to +85
1998 May 01
7
Page 8
Philips Semiconductors Product specification
2V
V
V
80C51 8-bit microcontroller
87C552
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
DC ELECTRICAL CHARACTERISTICS
VSS, AVSS = 0V
TEST LIMITS
SYMBOL PARAMETER CONDITIONS MIN MAX UNIT
I
DD
I
ID
I
PD
Inputs
V
IL
V
IL1
V
IL2
V
IH
V
IH1
V
IH2
I
IL
I
TL
±I
IL1
±I
IL2
±I
IL3
Outputs
V
OL
V
OL1
V
OL2
V
OH
V
OH1
V
OH2
R
RST
C
IO
Analog Inputs
AV
DD
AI
DD
AI
ID
AI
PD
Supply current operating: See notes 1 and 2
PCA8XC552-5-16 f
= 16MHz 40 mA
OSC
Idle mode: See notes 1 and 3
87C552 f
= 16MHz 7 mA
OSC
Power-down current: See notes 1 and 4;
<
<
87C552
PD
DD
max
50 µA
Input low voltage, except EA, P1.6, P1.7 –0.5 0.2VDD–0.1 V
Input low voltage to EA –0.5 0.2VDD–0.3 V
Input low voltage to P1.6/SCL, P1.7/SDA
5
–0.5 0.3V
DD
Input high voltage, except XTAL1, RST 0.2VDD+0.9 VDD+0.5 V
Input high voltage, XTAL1, RST 0.7V
Input high voltage, P1.6/SCL, P1.7/SDA
5
0.7V
DD
DD
VDD+0.5 V
6.0 V
Logical 0 input current, ports 1, 2, 3, 4, except P1.6, P1.7 VIN = 0.45V –50 µA
Logical 1-to-0 transition current, ports 1, 2, 3, 4, except P1.6, P1.7 See note 6 –650 µA
Input leakage current, port 0, EA, STADC, EW 0.45V < V
Input leakage current, P1.6/SCL, P1.7/SDA
0V < V
Input leakage current, port 5 0.45V < V
Output low voltage, ports 1, 2, 3, 4, except P1.6, P1.7 IOL = 1.6mA
Output low voltage, port 0, ALE, PSEN, PWM0,
< V
I
0V < V
< 6V
I
< 5.5V
DD
< V
I
IOL = 3.2mA
7
7
DD
DD
10 µA
10 µA
1 µA
0.45 V
0.45 V
PWM1
Output low voltage, P1.6/SCL, P1.7/SDA IOL = 3.0mA
7
0.4 V
Output high voltage, ports 1, 2, 3, 4, except P1.6/SCL, P1.7/SDA
–IOH = 60µA 2.4 V
Output high voltage (port 0 in external bus mode, ALE,
PSEN, PWM0, PWM1)
8
–IOH = 25µA 0.75V
–IOH = 10µA 0.9V
–IOH = 400µA 2.4 V
–IOH = 150µA 0.75V
–IOH = 40µA 0.9V
DD
DD
DD
DD
Output high voltage (RST) –IOH = 400µA 2.4 V
–IOH = 120µA 0.8V
DD
Internal reset pull-down resistor 50 150 kΩ
Pin capacitance Test freq = 1MHz,
T
= 25°C
amb
10 pF
Analog supply voltage:
9
87C552
Analog supply current: operating: Port 5 = 0 to AV
AVDD = VDD±0.2V 4.5 5.5 V
DD
1.2 mA
Idle mode:
87C552 50 µA
Power-down mode: 2V < AVPD < AVDD max
87C552 50 µA
V
V
V
V
V
V
1998 May 01
8
Page 9
Philips Semiconductors Product specification
80C51 8-bit microcontroller
87C552
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
DC ELECTRICAL CHARACTERISTICS (Continued)
TEST LIMITS
SYMBOL PARAMETER CONDITIONS MIN MAX UNIT
Analog Inputs (Continued)
AV
IN
AV
REF
R
REF
C
IA
t
ADS
t
ADC
DL
e
IL
e
OS
e
G
e
A
e
M
CTC
C
t
NOTES FOR DC ELECTRICAL CHARACTERISTICS:
1. See Figures 10 through 15 for I
2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t
V
3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t
V
4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW
EA
5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I
0 while an input voltage above 3.0V will be recognized as a logic 1.
6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition
current reaches its maximum value when V
7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V . In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
single output sinks more than 5mA and no more than two outputs exceed the test conditions.
8. Capacitive loading on ports 0 and 2 may cause the V
address bits are stabilizing.
9. The following condition must not be exceeded: V
10.Conditions: AV
parameters from collected conversion results of ADC. AV
11.The differential non-linearity (DL
12.The ADC is monotonic; there are no missing codes.
13.The integral non-linearity (IL
appropriate adjustment of gain and offset error. (See Figure 1.)
14.The offset error (OS
a straight line which fits the ideal transfer curve. (See Figure 1.)
15.The gain error (Ge) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),
and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 1.)
16.The absolute voltage error (A
ADC and the ideal transfer curve.
17.This should be considered when both analog and digital signals are simultaneously input to port 5.
Analog input voltage AVSS–0.2 AVDD+0.2 V
Reference voltage:
AV
REF–
AV
REF+
Resistance between AV
REF+
and AV
REF–
AVSS–0.2 V
AVDD+0.2 V
10 50 kΩ
Analog input capacitance 15 pF
Sampling time 8t
Conversion time (including sampling time) 50t
Differential non-linearity
Integral non-linearity
Offset error
Gain error
10, 14
10, 15
Absolute voltage error
10, 11, 12
10, 13
10, 16
Channel to channel matching ±1 LSB
Crosstalk between inputs of port 5
test conditions.
DD
= VDD – 0.5V; XTAL2 not connected; EA = RST = Port 0 = EW = VDD; STADC = VSS.
IH
= VDD – 0.5V; XTAL2 not connected; Port 0 = EW = VDD; EA = RST = STADC = VSS.
IH
= RST = STADC = XTAL1 = VSS.
= 0V; AVDD = 5.0V . Measurement by continuous conversion of AVIN = –20mV to 5.12V in steps of 0.5mV , derivating
REF–
) is the difference between the actual step width and the ideal step width. (See Figure 1.)
e
) is the peak difference between the center of the steps of the actual and the ideal transfer curve after
e
) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and
e
) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated
e
17
is approximately 2V .
IN
on ALE and PSEN to momentarily fall below the 0.9VDD specification when the
OH
– 0.2V < AVDD < VDD + 0.2V.
DD
(87C552) = 4.977V . ADC is monotonic with no missing codes.
REF+
0–100kHz –60 dB
= tf = 10ns; VIL = VSS + 0.5V;
r
= tf = 10ns; VIL = VSS + 0.5V;
r
= VDD;
2
C specification, so an input voltage below 1.5V will be recognized as a logic
s of ALE and ports 1 and 3. The noise is due
OL
can exceed these conditions provided that no
OL
CY
CY
µs
µs
±1 LSB
±2 LSB
±2 LSB
±0.4 %
±3 LSB
1998 May 01
9
Page 10
Philips Semiconductors Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
1023
1022
1021
1020
1019
1018
(2)
Offset
error
OS
e
87C552
Gain
error
G
e
Code
Out
7
6
5
4
3
2
1
0
1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024
Offset
error
OS
e
(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential non-linearity (DL
(4) Integral non-linearity (IL
(5) Center of a step of the actual transfer curve.
).
e
).
e
(5)
(4)
(3)
1 LSB
(ideal)
1 LSB =
Figure 1. ADC Conversion Characteristic
(1)
AV
REF+
AVIN (LSB
1024
– AV
ideal
REF–
)
SU00212
1998 May 01
10
Page 11
Philips Semiconductors Product specification
80C51 8-bit microcontroller
87C552
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
AC ELECTRICAL CHARACTERISTICS
SYMBOL FIGURE PARAMETER MIN MAX MIN MAX MIN MAX UNIT
1/t
CLCL
t
LHLL
t
AVLL
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
AVIV
t
PLAZ
Data Memory
t
AVLL
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVWL
t
QVWX
t
DW
t
WHQX
t
RLAZ
t
WHLH
External Clock
t
CHCX
t
CLCX
t
CLCH
t
CHCL
Serial Timing – Shift Register Mode4 (Test Conditions: T
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN
3. t
4. These values are characterized but not 100% production tested.
= 1/f
CLCL
t
= 83.3ns at f
CLCL
= 62.5ns at f
t
CLCL
2 Oscillator frequency 3.5 16 MHz
2 ALE pulse width 127 85 2t
2 Address valid to ALE low 28 8 t
2 Address hold after ALE low 48 28 t
2 ALE low to valid instruction in 234 150 4t
2 ALE low to PSEN low 43 23 t
2 PSEN pulse width 205 143 3t
2 PSEN low to valid instruction in 145 83 3t
2 Input instruction hold after PSEN 0 0 0 ns
2 Input instruction float after PSEN 59 38 t
2 Address to valid instruction in 312 208 5t
2 PSEN low to address float 10 10 10 ns
3, 4 Address valid to ALE low 43 23 t
3 RD pulse width 400 275 6t
3 WR pulse width 400 275 6t
3 RD low to valid data in 252 148 5t
3 Data hold after RD 0 0 0 ns
3 Data float after RD 97 55 2t
3 ALE low to valid data in 517 350 8t
3 Address to valid data in 585 398 9t
3, 4 ALE low to RD or WR low 200 300 138 238 3t
3, 4 Address valid to WR low or RD low 203 120 4t
4 Data valid to WR transition 23 3 t
4 Data before WR 433 288 7t
4 Data hold after WR 33 13 t
4 RD low to address float 0 0 0 ns
3, 4 RD or WR high to ALE high 43 123 23 103 t
5 High time
5 Low time
5 Rise time
5 Fall time
3
3
3
3
6 Serial port clock cycle time 1.0 0.75 12t
6 Output data setup to clock rising edge 700 492 10t
6 Output data hold after clock rising edge 50 8 2t
6 Input data hold after clock rising edge 0 0 0 ns
6 Clock rising edge to input data valid 700 492 10t
= one oscillator clock period.
OSC
OSC
OSC
= 12MHz.
= 16MHz.
1, 2
12MHz CLOCK 16MHz CLOCK VARIABLE CLOCK
20 20 20 ns
20 20 20 ns
20 20 20 ns
20 20 20 ns
= 0°C to +70°C; VSS = 0V; Load Capaciatnce = 80pF)
amb
= 100pF, load capacitance for all other outputs = 80pF.
–40 ns
CLCL
–55 ns
CLCL
–35 ns
CLCL
–100 ns
CLCL
–40 ns
CLCL
–45 ns
CLCL
–105 ns
CLCL
–25 ns
CLCL
–105 ns
CLCL
–40 ns
CLCL
–100 ns
CLCL
–100 ns
CLCL
–165 ns
CLCL
–70 ns
CLCL
–150 ns
CLCL
–165 ns
CLCL
–50 3t
CLCL
–130 ns
CLCL
–60 ns
CLCL
–150 ns
CLCL
–50 ns
CLCL
–40 t
CLCL
CLCL
–133 ns
CLCL
–117 ns
CLCL
+50 ns
CLCL
+40 ns
CLCL
–133 ns
CLCL
µs
1998 May 01
11
Page 12
Philips Semiconductors Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
AC ELECTRICAL CHARACTERISTICS (Continued)
SYMBOL PARAMETER INPUT OUTPUT
I2C Interface (Refer to Figure 9)
t
HD;STA
t
LOW
t
HIGH
t
RC
t
FC
t
SU;DAT1
t
SU;DAT2
t
SU;DAT3
t
HD;DAT
t
SU;STA
t
SU;STO
t
BUF
t
RD
t
FD
STAR T condition hold time ≥ 14 t
SCL low time ≥ 16 t
SCL high time ≥ 14 t
SCL rise time ≤ 1µs –
SCL fall time ≤ 0.3µs < 0.3µs
Data set-up time ≥ 250ns > 20 t
SDA set-up time (before rep. STAR T cond.) ≥ 250ns > 1µs
SDA set-up time (before STOP cond.) ≥ 250ns > 8 t
Data hold time ≥ 0ns > 8 t
Repeated START set-up time ≥ 14 t
STOP condition set-up time ≥ 14 t
Bus free time ≥ 14 t
SDA rise time ≤ 1µs –
SDA fall time ≤ 0.3µs < 0.3µs
NOTES:
1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.
2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1µs.
3. Spikes on the SDA and SCL lines with a duration of less than 3 t
SCL = 400pF.
4. t
= 1/f
CLCL
interface meets the I
= one oscillator clock period at pin XTAL1. For 62ns (42s) < t
OSC
2
C-bus specification for bit-rates up to 100 kbit/s.
5. These values are guaranteed but not 100% production tested.
5
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
will be filtered out. Maximum capacitance on bus-lines SDA and
CLCL
< 285ns (16MHz (24Hz) > f
CLCL
OSC
> 4.0µs
> 4.7µs
> 4.0µs
CLCL
CLCL
> 4.7µs
> 4.0µs
> 4.7µs
> 3.5MHz) the SI01
87C552
1
1
1
2
3
– t
RD
1
CLCL
– t
FC
1
1
1
2
3
1998 May 01
12
Page 13
Philips Semiconductors Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
EXPLANATION OF THE AC SYMBOLS
Each timing symbol has five characters. The first character is always
‘t’ (= time). The other characters, depending on their positions,
indicate the name of a signal or the logical status of that signal. The
designations are:
A – Address
C – Clock
D – Input data
H – Logic level high
I – Instruction (program memory contents)
L – Logic level low, or ALE
t
ALE
PSEN
PORT 0
LHLL
t
t
AVLL
LLPL
t
LLAX
A0–A7 A0–A7
t
LLIV
t
PLIV
t
PLPH
t
PLAZ
t
P – PSEN
Q – Output data
R–RD
signal
t – Time
V – Valid
W– WR
signal
X – No longer a valid logic level
Z – Float
Examples: t
t
PXIZ
PXIX
INSTR IN
= Time for address valid to ALE low.
AVLL
t
= Time for ALE low to PSEN low.
LLPL
87C552
ALE
PSEN
PORT 0
PORT 2
RD
PORT 2
t
AVLL
t
LLAX
A0–A7
FROM RI OR DPL
t
AVWL
t
AVIV
A0–A15 A8–A15
Figure 2. External Program Memory Read Cycle
t
WHLH
t
LLDV
t
LLWL
t
RLAZ
t
AVDV
P2.0–P2.7 OR A8–A15 FROM DPH A0–A15 FROM PCH
t
RLDV
t
RLRH
t
RHDZ
t
RHDX
DATA IN A0–A7 FROM PCL INSTR IN
SU00006
1998 May 01
SU00007
Figure 3. External Data Memory Read Cycle
13
Page 14
Philips Semiconductors Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
ALE
t
WHLH
PSEN
t
WLWH
t
DW
DATA OUT A0–A7 FROM PCL INSTR IN
WR
PORT 0
PORT 2
t
AVLL
t
t
LLAX
A0–A7
FROM RI OR DPL
t
AVWL
LLWL
t
QVWX
P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH
t
WHQX
87C552
INSTRUCTION
ALE
CLOCK
OUTPUT DATA
WRITE TO SBUF
INPUT DATA
CLEAR RI
SU00213
Figure 4. External Data Memory Write Cycle
0.8V
t
t
HIGH
V
IH1
V
IH1
0.8V
t
LOW
r
V
IH1
0.8V 0.8V
t
CLCL
t
f
V
IH1
SU00214
Figure 5. External Clock Drive XTAL1
012345678
t
XLXL
t
t
QVXH
t
XHDV
VALID VALID VALID VALID VALID VALID VALID VALID
XHQX
1230 4567
t
XHDX
SET TI
SET RI
SU00027
Figure 6. Shift Register Mode Timing
1998 May 01
14
Page 15
Philips Semiconductors Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
2.4V
0.45V
NOTE:
AC inputs during testing are driven at 2.4V for a logic ‘1’ and 0.45V for a logic ‘0’.
Timing measurements are made at 2.0V for a logic ‘1’ and 0.8V for a logic ‘0’.
2.0V
0.8V
Test Points
Figure 7. AC Testing Input/Output
2.4V
0.45V 0.45V
NOTE:
The float state is defined as the point at which a port 0 pin sinks 3.2mA or sources 400µA at the voltage test levels.
2.0V
0.8V
Float
Figure 8. AC Testing Input, Float Waveform
2.0V
0.8V
2.0V
0.8V
87C552
SU00215
2.4V
SU00216
START or repeated START condition
SDA
(INPUT/OUTPUT)
SCL
(INPUT/OUTPUT)
t
FDtRC
t
HD;STA
t
LOW
t
RD
t
HIGH
repeated START condition
STOP condition
t
FC
t
SU;DAT1
t
HD;DAT
Figure 9. Timing SIO1 (I2C) Interface
t
t
SU;DAT2
SU;STA
t
SU;STO
0.7 V
0.3 V
t
SU;DAT3
CC
CC
t
BUF
START condition
0.7 V
CC
0.3 V
CC
SU00107A
1998 May 01
15
Page 16
Philips Semiconductors Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
50
40
30
mA
I
DD
20
10
NOTE:
These values are valid only within the frequency
specifications of the device under test.
Figure 10. 16MHz Version Supply Current (IDD) as a Function of Frequency at XTAL1 (f
0
0
f (MHz)
124168
(1)
(2)
(3)
(4)
(1) Maximum operating mode; VDD = 6V
(2) Maximum operating mode; V
(3) Maximum idle mode; V
(4) Maximum idle mode; V
OSC
)
87C552
= 4V
DD
= 6V
DD
= 4V
DD
SU00217
V
DD
P1.6
(NC)
CLOCK SIGNAL
P1.7
V
DD
RST
STADC
XTAL2
XTAL1
V
SS
V
DD
EW
AV
AV
ref–
Figure 11. IDD Test Condition, Active Mode
All other pins are disconnected
1. Active Mode:
a. The following pins must be forced to V
b. The following pins must be forced to V
c. Ports 1.6 and 1.7 should be connected to V
exceed the I
spec of these pins.
OL1
: EA, RST, Port 0, and EW.
DD
: STADC, AVss, and AV
SS
through resistors of sufficiently high value such that the sink current into these pins cannot
DD
ref–
.
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
P0
SS
EA
V
DD
I
DD
V
DD
SU00218
1
1998 May 01
16
Page 17
Philips Semiconductors Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
V
DD
P1.6
P1.7
RST
STADC
(NC)
CLOCK SIGNAL
XTAL2
XTAL1
V
SS
Figure 12. IDD Test Condition, Idle Mode
All other pins are disconnected
2. Idle Mode:
a. The following pins must be forced to V
b. The following pins must be forced to V
c. Ports 1.6 and 1.7 should be connected to V
exceed the I
spec of these pins. These pins must not have logic 0 written to them prior to this measurement.
OL1
: Port 0 and EW.
DD
: RST, STADC, AVss,, AV
SS
through resistors of sufficiently high value such that the sink current into these pins cannot
DD
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
, and EA.
ref–
V
DD
P0
EW
EA
AV
SS
AV
ref–
87C552
V
DD
I
DD
V
DD
SU00219
2
VDD–0.5
0.5V
0.7V
DD
0.2VDD–0.1
t
CHCL
t
CLCX
t
CLCL
Figure 13. Clock Signal Waveform for IDD Tests in Active and Idle Modes
= t
t
CLCH
V
DD
P1.6
P1.7
RST
STADC
(NC)
XTAL2
XTAL1
V
SS
CHCL
= 5ns
AV
Figure 14. IDD Test Condition, Power Down Mode
All other pins are disconnected. V
3. Power Down Mode:
a. The following pins must be forced to V
b. The following pins must be forced to V
c. Ports 1.6 and 1.7 should be connected to V
exceed the I
spec of these pins. These pins must not have logic 0 written to them prior to this measurement.
OL1
: Port 0 and EW.
DD
: RST, STADC, XTAL1, AVss,, AV
SS
through resistors of sufficiently high value such that the sink current into these pins cannot
DD
d. The following pins must be disconnected: XTAL2 and all pins not specified above.
t
CHCX
t
CLCH
V
DD
P0
EW
EA
AV
SS
ref–
= 2V to 5.5V
DD
, and EA.
ref–
I
DD
SU00220
V
DD
V
DD
SU00221
3
1998 May 01
17
Page 18
Philips Semiconductors Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
EPROM CHARACTERISTICS
The 87C552 is programmed by using a modified Quick-Pulse
Programming algorithm. It differs from older methods in the value
used for V
number of the ALE/PROG
The 87C552 contains two signature bytes that can be read and used
by an EPROM programming system to identify the device. The
signature bytes identify the device as an 87C552 manufactured by
Philips.
Table 3 shows the logic levels for reading the signature byte, and for
programming the program memory, the encryption table, and the
lock bits. The circuit configuration and waveforms for quick-pulse
programming are shown in Figures 15 and 16. Figure 17 shows the
circuit configuration for normal program memory verification.
(programming supply voltage) and in the width and
PP
pulses.
Quick-Pulse Programming
The setup for microcontroller quick-pulse programming is shown in
Figure 15. Note that the 87C552 is running with a 4 to 6MHz
oscillator. The reason the oscillator needs to be running is that the
device is executing internal address and program data transfers.
The address of the EPROM location to be programmed is applied to
ports 1 and 2, as shown in Figure 15. The code byte to be
programmed into that location is applied to port 0. RST, PSEN
pins of ports 2 and 3 specified in Table 3 are held at the “Program
Code Data” levels indicated in Table 3. The ALE/PROG
low 25 times as shown in Figure 16.
To program the encryption table, repeat the 25-pulse programming
sequence for addresses 0 through 1FH, using the “Pgm Encryption
Table” levels. Do not forget that after the encryption table is
programmed, verification cycles will produce only encrypted data.
To program the lock bits, repeat the 25-pulse programming
sequence using the “Pgm Lock Bit” levels. After one lock bit is
, and
is pulsed
programmed, further programming of the code memory and
encryption table is disabled. However, the other lock bit can still be
programmed.
Note that the EA
maximum specified V
glitch above that voltage can cause permanent damage to the
device. The V
and overshoot.
Program V erification
If lock bit 2 has not been programmed, the on-chip program memory
can be read out for program verification. The address of the program
memory locations to be red is applied to ports 1 and 2 as shown in
Figure 17. The other pins are held at the “Verify Code Data” levels
indicated in Table 3. The contents of the address location will be
emitted on port 0. External pull-ups are required on port 0 for this
operation.
If the encryption table has been programmed, the data presented at
port 0 will be the exclusive NOR of the program byte with one of the
encryption bytes. The user will have to know the encryption table
contents in order to correctly decode the verification data. The
encryption table itself cannot be read out.
Reading the Signature Bytes
The signature bytes are read by the same procedure as a normal
verification of locations 030H and 031H, except that P3.6 and P3.7
need to be pulled to a logic low. The values are:
(030H) = 15H indicates manufactured by Philips Components
(031H) = 94H indicates 87C552
Program/Verify Algorithms
Any algorithm in agreement with the conditions listed in Table 3, and
which satisfies the timing specifications, is suitable.
87C552
/VPP pin must not be allowed to go above the
level for any amount of time. Even a narrow
PP
source should be well regulated and free of glitches
PP
Table 3. EPROM Programming Modes
MODE RST PSEN ALE/PROG EA/V
Read signature 1 0 1 1 0 0 0 0
Program code data 1 0 0* V
Verify code data 1 0 1 1 0 0 1 1
Pgm encryption table 1 0 0* V
Pgm lock bit 1 1 0 0* V
Pgm lock bit 2 1 0 0* V
NOTES:
1. 0 = Valid low for that pin; 1 = valid high for that pin.
= 12.75V ±0.25V.
2. V
PP
= 5V ±10% during programming and verification.
3. V
DD
* ALE/PROG
minimum of 10µs.
Trademark phrase of Intel Corporation.
receives 25 programming pulses while VPP is held at 12.75V . Each programming pulse is low for 100 µs (±10µs) and high for a
PP
PP
PP
PP
PP
P2.7 P2.6 P3.7 P3.6
1 0 1 1
1 0 1 0
1 1 1 1
1 1 0 0
1998 May 01
18
Page 19
Philips Semiconductors Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
V
DD
P0
/V
EA
PP
ALE/PROG
PSEN
P2.7
P2.6
P2.0-P2.4
4-6MHz
A0-A7
P1
1
1
1
RST
P3.6
P3.7
XTAL2
XTAL1
V
SS
87C552
Figure 15. Programming Configuration
87C552
+5V
PGM DATA
+12.75V
25 100µs PULSES TO GROUND
0
1
0
A8-A12
SU00222
ALE/PROG:
ALE/PROG:
1
0
1
0
25 PULSES
100µs+1010µs MIN
SU00018
Figure 16. PROG Waveform
+5V
V
DD
P0
/V
EA
PP
ALE/PROG
PSEN
P2.7
P2.6
P2.0-P2.4
PGM DATA
1
1
0
0 ENABLE
0
A8-A12
4-6MHz
A0-A7
P1
1
1
1
RST
P3.6
P3.7
XTAL2
XTAL1
87C552
1998 May 01
V
SS
Figure 17. Program Verification
19
SU00223
Page 20
Philips Semiconductors Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS
T
= 21°C to +27°C, VDD = 5V±10%, VSS = 0V
amb
SYMBOL
V
PP
I
PP
1/t
CLCL
t
AVGL
t
GHAX
t
DVGL
t
GHDX
t
EHSH
t
SHGL
t
GHSL
t
GLGH
t
AVQV
t
ELQZ
t
EHQZ
t
GHGL
Programming supply voltage 12.5 13.0 V
Programming supply current 50 mA
Oscillator frequency 4 6 MHz
Address setup to PROG low 48t
Address hold after PROG 48t
Data setup to PROG low 48t
Data hold after PROG 48t
P2.7 (ENABLE) high to V
VPP setup to PROG low 10 µs
VPP hold after PROG 10 µs
PROG width 90 110 µs
Address to data valid 48t
ENABLE low to data valid 48t
Data float after ENABLE 0 48t
PROG high to PROG low 10 µs
PARAMETER MIN MAX UNIT
PP
48t
87C552
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
CLCL
PROGRAMMING* VERIFICATION*
P1.0–P1.7
P2.0–P2.4
PORT 0
t
DVGL
t
ALE/PROG
EA/V
PP
P2.7
ENABLE
* FOR PROGRAMMING VERIFICATION SEE FIGURE 17.
FOR VERIFICATION CONDITIONS SEE TABLE 3.
AVGL
t
EHSH
t
GLGH
t
SHGL
ADDRESS ADDRESS
t
AVQV
DATA IN DATA OUT
t
GHDX
t
GHAX
t
GHGL
LOGIC 0
t
GHSL
LOGIC 1 LOGIC 1
t
ELQV
Figure 18. EPROM Programming and Verification
t
EHQZ
SU00020
1998 May 01
Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I
2
C system provided the system conforms to the
I2C specifications defined by Philips. This specification can be ordered using the
code 9398 393 40011.
20
Page 21
Philips Semiconductors Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
PLCC68: plastic leaded chip carrier; 68 leads; pedestal SOT188-3
87C552
1998 May 01
21
Page 22
Philips Semiconductors Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT318-2
87C552
1998 May 01
22
Page 23
Philips Semiconductors Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
NOTES
87C552
1998 May 01
23
Page 24
Philips Semiconductors Product specification
80C51 8-bit microcontroller
8K/256 OTP, 8 channel 10 bit A/D, I2C, PWM, capture/compare, high I/O
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
87C552
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
Date of release: 05-98
Document order number: 9397 750 05367
1998 May 01
24
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