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SN54HCT374, SN74HCT374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS005B – MARCH 1984 – REVISED MA Y 1997
D
Inputs Are TTL-Voltage Compatible
D
Eight D-Type Flip-Flops in a Single Package
D
High-Current 3-State True Outputs Can
Drive up to 15 LSTTL Loads
D
Full Parallel Access for Loading
D
Package Options Include Plastic
Small-Outline (DW) and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
description
These 8-bit flip-flops feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The eight flip-flops of the ’HCT374 are
edge-triggered D-type flip-flops. On the positive
transition of the clock (CLK) input, the Q outputs
are set to the logic levels that were set up at the
data (D) inputs.
An output-enable (OE
outputs in either a normal logic state (high or low
logic levels) or the high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly. The
high-impedance state and increased drive
provide the capability to drive bus lines without
interface or pullup components.
) input places the eight
SN54HCT374 ...J OR W PACKAGE
SN74HCT374 . . . DW OR N PACKAGE
SN54HCT374 . . . FK PACKAGE
2D
2Q
3Q
3D
4D
(TOP VIEW)
OE
1
1Q
2
1D
3
2D
4
2Q
5
3Q
6
3D
7
4D
8
4Q
9
GND
10
(TOP VIEW)
1D1QOE
3212019
4
5
6
7
8
910111213
4Q
GND
20
19
18
17
16
15
14
13
12
11
CLK
CC
V
5Q
V
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLK
8Q
18
17
16
15
14
5D
CC
8D
7D
7Q
6Q
6D
OE
does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54HCT374 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HCT374 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
INPUTS
OE CLK D
L ↑ H H
L ↑ LL
L H or L X Q
H X X Z
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
OUTPUT
Q
0
Copyright 1997, Texas Instruments Incorporated
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SN54HCT374, SN74HCT374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS005B – MARCH 1984 – REVISED MA Y 1997
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
OE
CLK
1D
2D
3D
4D
5D
6D
7D
8D
1
11
3
4
7
8
13
14
17
18
EN
C1
1D
logic diagram (positive logic)
1
OE
11
CLK
12
15
16
19
2
1Q
5
2Q
6
3Q
9
4Q
5Q
6Q
7Q
8Q
C1
1D
1D
3
To Seven Other Channels
absolute maximum ratings over operating free-air temperature range
2
1Q
‡
Supply voltage range, VCC –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
(VI < 0 or VI > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IK
Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, IO (VO = 0 to VCC) ±35 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND ±70 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θ
(see Note 2): DW package 97°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
JA
N package 67°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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UNIT
PARAMETER
TEST CONDITIONS
V
UNIT
V
V
V
or V
4.5 V
V
V
V
V
V
4.5 V
V
V
UNIT
f
Clock frequenc
MH
twPulse duration, CLK high or lo
ns
tsuSetup time, data before CLK↑
ns
thHold time, data after CLK↑
ns
SN54HCT374, SN74HCT374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS005B – MARCH 1984 – REVISED MA Y 1997
recommended operating conditions
SN54HCT374 SN74HCT374
MIN NOM MAX MIN NOM MAX
V
V
V
V
V
t
t
T
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or VCC.
Supply voltage 4.5 5 5.5 4.5 5 5.5 V
CC
High-level input voltage VCC = 4.5 V to 5.5 V 2 2 V
IH
Low-level input voltage VCC = 4.5 V to 5.5 V 0 0.8 0 0.8 V
IL
Input voltage 0 V
I
Output voltage 0 V
O
Input transition (rise and fall) time 0 500 0 500 ns
Operating free-air temperature –55 125 –40 85 °C
A
TA = 25°C SN54HCT374 SN74HCT374
MIN TYP MAX MIN MAX MIN MAX
4.4 4.499 4.4 4.4
3.98 4.3 3.7 3.84
0.001 0.1 0.1 0.1
0.17 0.26 0.4 0.33
3 10 10 10 pF
I
I
I
∆I
C
OH
OL
I
OZ
CC
i
CC
CC
=
I
IH
=
or
I
IH
VI = VCC or 0 5.5 V ±0.1 ±100 ±1000 ±1000 nA
VO = VCC or 0 5.5 V ±0.01 ±0.5 ±10 ±5 µA
VI = VCC or 0, IO = 0 5.5 V 8 160 80 µA
One input at 0.5 V or 2.4 V,
†
Other inputs at 0 or V
IL
IL
IOH = –20 µA
IOH = –6 mA
IOL = 20 µA
IOL = 6 mA
CC
5.5 V 1.4 2.4 3 2.9 mA
4.5 V
to 5.5 V
CC
CC
0 V
0 V
CC
CC
V
V
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
TA = 25°C SN54HCT374 SN74HCT374
CC
MIN MAX MIN MAX MIN MAX
clock
y
w
p
4.5 V 0 31 0 21 0 25
5.5 V
4.5 V 16 24 20
5.5 V
4.5 V 20 30 25
5.5 V 17 27 23
4.5 V 10 10 10
5.5 V 10 10 10
0 36 0 23 0 28
14 22 18
z
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SN54HCT374, SN74HCT374
PARAMETER
V
UNIT
f
MH
tpdCLK
Any Q
ns
t
OE
Any Q
ns
t
OE
Any Q
ns
ttAny Q
ns
PARAMETER
V
UNIT
tpdCLK
Any Q
ns
t
OE
Any Q
ns
ttAny Q
ns
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS005B – MARCH 1984 – REVISED MA Y 1997
switching characteristics over recommended operating free-air temperature range, CL = 50 pF
(unless otherwise noted) (see Figure 1)
FROM TO
(INPUT) (OUTPUT)
max
en
dis
CC
4.5 V 31 36 21 25
5.5 V 36 40 23 28
4.5 V 30 36 54 45
5.5 V 25 32 49 41
4.5 V 26 30 45 38
5.5 V 23 27 41 34
4.5 V 23 30 45 38
5.5 V 22 27 41 34
4.5 V 10 12 18 15
5.5 V 9 11 16 14
switching characteristics over recommended operating free-air temperature range, CL = 150 pF
(unless otherwise noted) (see Figure 1)
FROM TO
(INPUT) (OUTPUT)
en
CC
4.5 V 40 46 69 58
5.5 V 35 41 62 52
4.5 V 34 40 60 50
5.5 V 29 36 54 45
4.5 V 18 42 63 53
5.5 V 16 38 57 48
TA = 25°C SN54HCT374 SN74HCT374
MIN TYP MAX MIN MAX MIN MAX
z
TA = 25°C SN54HCT374 SN74HCT374
MIN TYP MAX MIN MAX MIN MAX
operating characteristics, TA = 25°C
PARAMETER TEST CONDITIONS TYP UNIT
C
Power dissipation capacitance per flip-flop No load 85 pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SN54HCT374, SN74HCT374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS005B – MARCH 1984 – REVISED MA Y 1997
PARAMETER MEASUREMENT INFORMATION
V
From Output
Under Test
(see Note A)
Test
Point
C
L
LOAD CIRCUIT
CC
S1
R
L
S2
PARAMETER C
t
t
PZH
t
PZL
t
PHZ
t
PLZ
t
en
t
dis
tpd or t
R
1 kΩ
1 kΩ
L
50 pF
150 pF
50 pF
50 pF
150 pF
L
or
Closed Open
Closed Open
or
S1
Open Closed
Open Closed
Open Open––
S2
High-Level
Pulse
Low-Level
Pulse
Input
In-Phase
Output
Out-of-
Phase
Output
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
1.3 V
t
t
1.3 V
t
w
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
1.3 V
PLH
90% 90%
t
r
PHL
1.3 V 1.3 V
10% 10%
t
f
VOLTAGE WAVEFORMS
1.3 V
1.3 V
t
PHL
t
PLH
3 V
0 V
3 V
0 V
1.3 V1.3 V
10%10%
90%90%
t
f
t
r
Reference
Input
t
su
Data
Input
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
3 V
0 V
V
V
V
V
OH
OL
OH
OL
Output
Control
(Low-Level
Enabling)
Output
Waveform 1
(See Note B)
Output
Waveform 2
(See Note B)
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
2.7 V 2.7 V
VOLTAGE WAVEFORMS
t
PZL
t
PZH
VOLTAGE WAVEFORMS
t
r
1.3 V
1.3 V
1.3 V
1.3 V
t
h
1.3 V
1.3 V1.3 V
10%
90%
0.3 V0.3 V
t
PLZ
t
PHZ
3 V
0 V
3 V
0 V
t
f
3 V
0 V
≈ V
CC
V
OL
V
OH
≈ 0 V
NOTES: A. CL includes probe and test-fixture capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns.
D. For clock inputs, f
E. The outputs are measured one at a time with one input transition per measurement.
F. t
G. t
H. t
PLZ
PZL
PLH
and t
and t
and t
PHZ
PZH
PHL
is measured when the input duty cycle is 50%.
max
are the same as t
are the same as ten.
are the same as tpd.
dis
.
Figure 1. Load Circuit and Voltage Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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