Datasheet 83c576, 87576 DATASHEETS

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Page 1

INTEGRATED CIRCUITS

83C576/87C576

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

Product specification Supersedes data of 1998 Jan 06 IC20 Data Handbook

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1998 Jun 04

Page 2

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

83C576/87C576

FEA TURES

•80C51 based architecture

– 8k × 8 ROM (83C576) – 8k × 8 EPROM (87C576) – 256 × 8 RAM – 10-bit, 6 channel A/D – Three 16-bit counter/timers – 2 PWM outputs – Programmable Counter Array – Universal Peripheral Interface – Enhanced UART – Oscillator fail detect – Low active reset – 4 analog comparators – Watchdog timer – Low V – Power-on detect

detect

•Memory addressing capability

– 64k ROM and 64k RAM

•Power control modes:

– Idle mode – Power-down mode

•CMOS and TTL compatible

•6 to 16MHz

•Extended temperature ranges

•OTP available

•That can be programmed in circuit

•Software Reset

•15 source, 2 level interrupt structure

•Lower EMI noise

•Programmable I/O pins

•Serial on-board programming

•Schmitt trigger inputs on Port 1

DESCRIPTION

The Philips 83C576/87C576 is a high-performance microcontroller fabricated with Philips high-density CMOS technology. The Philips CMOS technology combines the high speed and density characteristics of HMOS with the low power attributes of CMOS. Philips epitaxial substrate minimizes latch-up sensitivity.

The 8XC576 contains an 8k × 8 ROM (83C576) EPROM (87C576), a 256 × 8 RAM, 32 I/O lines, three 16-bit counter/timers, a Programmable Counter Array (PCA), a 10-bit, 6 channel A/D, 2 PWM outputs, an 8-bit UPI interface, a fifteen-source, two-priority level nested interrupt structure, an enhanced UART, four analog comparators, power-fail detect and oscillator fail detect circuits, and on-chip oscillator and clock circuits.

In addition, the 8XC576 has a low active reset, and a software reset. There is also a fully configurable watchdog timer, and internal power on clear circuit. The part includes idle mode and power-down mode states for reduced power consumption.

ORDERING INFORMATION

ROM EPROM

P83C576EBPN P87C576EBPN OTP 0 to +70, 40-Pin Plastic Dual In-line Package 16 SOT129-1 P83C576EBAA P87C576EBAA OTP 0 to +70, 44-Pin Plastic Leaded Chip Carrier 16 SOT187-2 P83C576EBBB P87C576EBBB OTP 0 to +70, 44-Pin Plastic Quad Flat Pack 16 SOT307-2 P83C576EFPN P87C576EBPN OTP –40 to +85, 40-Pin Plastic Dual In-line Package 16 SOT129-1 P83C576EFAA P87C576EFAA OTP –40 to +85, 44-Pin Plastic Leaded Chip Carrier 16 SOT187-2 P83C576EFBB P87C576EFBB OTP –40 to +85, 44-Pin Plastic Quad Flat Pack 16 SOT307-2 P83C576EHPN P87C576EHPN OTP –40 to +125, 40-Pin Plastic Dual In-line Package 16 SOT129-1 P83C576EHAA P87C576EHAA OTP –40 to +125, 44-Pin Plastic Leaded Chip Carrier 16 SOT187-2 P83C576EHBB P87C576EHBB OTP –40 to +125, 44-Pin Plastic Quad Flat Pack 16 SOT307-2

NOTE:

1. OTP - One Time Programmable EPROM.

TEMPERATURE RANGE °C AND PACKAGE

FREQ (MHz)

DRAWING

NUMBER

1998 Jun 04 853-2067 19495

Page 3

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

BLOCK DIAGRAM

P0.0-P0.7 P2.0-P2.7

83C576/87C576

PSEN

WATCHDOG

ALE

RST

TIMING

CONTROL

XTAL1 XTAL2

UPI

CONTROL

LOW

VOLTAGE

DETECT

RAM ADDR REGISTER

TIMER

AND

INSTRUCTION

OSCILLATOR

B A

CLK AND OSC

POWER

DETECT

RAM

FAILURE DETECT

ACC

TMP2

DRIVERS

PSW

PORT 1

LATCH

PORT 1

DRIVERS

PORT 0

LATCH

ALU

TMP1

TIMERS

10-BIT

ANALOG TO DIGITAL

CONVERTER

PORT 2

DRIVERS

PORT 2

LATCH

SFRs

PCA

STACK

POINTER

PORT 3

LATCH

PORT 3

DRIVERS

ROM/

EPROM

PROGRAM

ADDRESS

BUFFER

INCRE-

MENTER

PROGRAM COUNTER

DPTR

COMPARATOR

BLOCK

PWM

1998 Jun 04

P1.0-P1.5

+AV

P3.0-P3.7

–AV

SU00255B

Page 4

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

LOGIC SYMBOL

XTAL1

XTAL2

ADDRESS AND

DATA BUS

PORT 0

83C576/87C576

DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7

CMP3+ CMP2+ CMP1+

CMPR–

CMP0+ CMP0–

PIN CONFIGURA TIONS 44-pin Plastic Quad Flat Pack

44 34

PQFP

12 22

Pin Function

1 ADIN3/P1.3 2 ADIN4/P1.4 3 ADIN5/P1.5 4 RST 5 RxD/P3.0 6 NC* 7 TXD/P3.1

0/P3.2/CMP3+

8 INT

1/P3.3/CMP2+

9 INT 10 T0/P3.4/CMP1+ 11 T1/P3.5/CMPR–

/P3.6/CMP0+

12 WR 13 RD

/P3.7CMP0– 14 XTAL2 15 XTAL1

* NO INTERNAL CONNECTION

Pin Function

16 V

17 NC* 18 P2.0/A8/CEX0/CMP0 19 P2.1/A9/CEX1/CMP1 20 P2.2/A10/CEX2/CMP2 21 P2.3/A11/CEX3/CMP3 22 P2.4/A12/T2EX/A0 23 P2.5/A13/T2/CS 24 P2.6/A14/CEX4/PWM0 25 P2.7/A15/PWM1/ECI 26 PSEN 27 ALE/PROG 28 NC*

29 EA

30 P0.7/AD7/DB7

EA/V

PSEN

ALE/PROG RxD TxD

INT0 INT1

T0 T1

SECONDARY FUNCTIONS

Pin Function

31 P0.6/AD6/DB6 32 P0.5/AD5/DB5 33 P0.4/AD4/DB4 34 P0.3/AD3/DB3 35 P0.2/AD2/DB2 36 P0.1/AD1/DB1 37 P0.0/AD0/DB0 38 V 39 NC* 40 +V 41 –V 42 ADIN0/P1.0 43 ADIN1/P1.1 44 ADIN2/P1.2

RST

PORT 3

REF

/AV

SU00253B

ADIN0 ADIN1

PORT 1PORT 2

SECONDARY FUNCTIONS

ADDRESS BUS

ADIN2 ADIN3 ADIN4 ADIN5 PWM1/ECI CEX4/PWM0 T2/CS# T2EX/A0 CEX3/CMP3 CEX2/CMP2 CEX1/CMP1 CEX0/CMP0

SU00254A

Plastic Leaded Chip Carrier

6140

LCC

18 28

Pin Function

1 NC* 2+V

/AV

REF

3–V 4 ADIN0/P1.0 5 ADIN1/P1.1 6 ADIN2/P1.2 7 ADIN3/P1.3 8 ADIN4/P1.4

9 ADIN5/P1.5 10 RST 11 RxD/P3.0 12 NC* 13 TxD/P3.1 14 INT 15 INT

* NO INTERNAL CONNECTION

/AV

REF

0/P3.2/CMP3+ 1/P3.3/CMP2+

Pin Function

16 T0/P3.4/CMP1+ 17 T1/P3.5/CMPR–

/P3.6/CMP0+

18 WR 19 RD

/P3.7/CMP0– 20 XTAL2 21 XTAL1 22 V

23 NC* 24 P2.0/A8/CEX0/CMP0 25 P2.1/A9/CEX1/CMP1 26 P2.2/A10/CEX2/CMP2 27 P2.3/A11/CEX3/CMP3 28 P2.4/A12/T2EX/A0 29 P2.5/A13/T2/CS 30 P2.6/A14/CEX4/PWM0

Pin Function

31 P2.7/A15/PWM1/ECI 32 PSEN 33 ALE/PROG 34 NC*

35 EA

36 P0.7/AD7/DB7 37 P0.6/AD6/DB6 38 P0.5/AD5/DB5 39 P0.4/AD4/DB4 40 P0.3/AD3/DB3 41 P0.2/AD2/DB2 42 P0.1/AD1/DB1 43 P0.0/AD0/DB0 44 V

SU00252A

1998 Jun 04

Page 5

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

PIN DESCRIPTIONS

PIN NUMBER

MNEMONIC

P0.0-0.7 39-32 43-36 37-30 I/O Port 0: Port 0 is a bidirectional I/O port. Port 0 is also the multiplexed low-order address and

P1.0-P1.5 3-8 5-9 42-44

P2.0-P2.7 21-28 24-31 18-25 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port. Port 2 emits the high-order address byte

DIP LCC QFP TYPE NAME AND FUNCTION

20 22 16 I Ground: 0V reference. 40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation.

data bus during accesses to external program and data memory (see Note 5). In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also receives code bytes during parallel EPROM programming and outputs code bytes during verification. External pull-ups are required during program verification. During reset, the port register is loaded with 1’s. Port 0 has 4 output modes selected on a per bit basis by writing to the P0M1 and P0M2 Special Function Registers as follows:

P0M1.x P0M2.x Mode Description

0 0 Open drain (default). See Note 1. 0 1 W eak pullup. See Note 2. 1 0 High impedance. See Note 3.

1 1 Push-pull. See Note 4. Port 0 is also the data I/O port for the Universal Peripheral Interface (UPI). When the UPI is enabled, port 0 must be configured as High-Z by the user. Input/Output through P0 is controlled by pin CS

I/O Port 1: Port 1 is a 6-bit bidirectional I/O port with Schmitt trigger inputs. Port 1 receives the control

1-3

3 4 42 I/O P1.0/ADIN0 4 5 43 I/O P1.1/ADIN1 5 6 44 I/O P1.2/ADIN2 6 7 1 I/O P1.3/ADIN3 7 8 2 I/O P1.4/ADIN4 8 9 3 I/O P1.5/ADIN5

21 24 18 P2.0 CEX0 PCA module 0 external I/O 22 25 19 P2.1 CEX1 PCA module 1 external I/O 23 26 20 P2.2 CEX2 PCA module 2 external I/O 24 27 21 P2.3 CEX3 PCA module 3 external I/O 25 28 22 P2.4 T2EX timer 2 capture input 26 29 23 P2.5 T2 timer 2 external I/O — clock-out (programmable) 27 30 24 P2.6 CEX4 PCA module 4 external I/O 28 31 25 P2.7 ECI PCA count input

signals during program memory verification and parallel EPROM programming. During reset, port 1 is configured as a high impedance analog input port. Digital push-pull outputs are enabled by writing 1’s to the P1M1 register. The programmer must take care to prevent digital outputs from switching while an A/D conversion is in progress. Port 1 has 3 output modes selected on a per bit basis by writing to the P1M1 and P1M2 special function registers as follows:

P1M1.X P1M2.X Mode Description

0 0 A/D only. (High impedance)

0 1 Digital input only. High impedance (default).

1 X Push-pull. Port 1 pins also serve alternate functions as follows:

during accesses to external program and data memory that use 16-bit addresses (MOVX @DPTR) (see Note 5). In this application, it uses strong internal pull-ups when emitting 1s. Port 2 receives the high-order address byte during program verification and parallel EPROM programming. During reset, the port 2 pullups are turned on synchronously, and the port register is loaded with 1’s. Port 2 has the following output modes which can be selected on a per bit basis by writing to P2M1 and P2M0:

P2M1.X P2M2.X Mode Description

0 0 Open drain. See Note 1.

0 1 W eak pullup (default). See Note 2.

1 0 High impedance. See Note 3.

1 1 Push-pull. See Note 4. Port 2 pins serve alternate functions as follows:

, WR, RD, and A0. Output is push-pull when enabled.

CMP0 comparator 0 output CMP1 comparator 1 output CMP2 comparator 2 output CMP3 comparator 3 output A0 UPI address input CS UPI chip select input PWM0 Pulse width modulator 0 output PWM1 Pulse width modulator 1 output

83C576/87C576

1998 Jun 04

Page 6

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

PIN DESCRIPTIONS (Continued)

PIN NUMBER

MNEMONIC DIP LCC QFP TYPE NAME AND FUNCTION

/AV

REF

–V

/AV

REF

P3.0-P3.7 10-17 11,

RST 9 10 4 I Reset: A low on this pin synchronously resets all port pins to a high state. The pin must be

ALE/PROG 30 33 27 I/O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address

PSEN 29 32 26 O Program Store Enable: The read strobe to external program memory. When the device is

EA/V

XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator XTAL2 18 20 14 O Crystal 2: Output from the inverting oscillator amplifier.

NOTES:

1. When Open Drain mode is selected, ports 0 and 2 have weak pulldowns to guarantee positive leakage current (see DC electrical characteristic I

2. When Weak Pullup mode is selected, ports bits that have 1’s written to them can be used as inputs but will source current when externally pulled low (see DC electrical characteristic IIL).

3. When High Impedance mode is selected, all pullups and pulldowns are turned off. The only current sourced or sunk by the pin is the parasitic leakage current (see DC electrical characteristic I

4. When Push-Pull mode is selected, strong pullups are on continuously when emitting 1’s (see DC electrical characteristic V

5. When Open-Drain, Weak Pull-up, or Push-pull mode is selected.

1 2 40 I A/D positive power supply

2 3 41 I A/D 0V reference

I/O Port 3: Port 3 is an 8-bit bidirectional I/O port. Port 3 pins that have 1s written to them can

13-195,7-13

be used as inputs but will source current when externally pulled low (see DC Electrical Characteristics: I high until written to by software. Port 3 has the following output modes which can be

). During reset all pins will be synchronously driven high and will remain

selected on a per bit basis by writing to P3M1 and P3M2:

P3M1.X P3M2.X Mode Description

0 0 Open drain. See Note 1. 0 1 W eak pullup (default). See Note 2. 1 0 High impedance. See Note 3. 1 1 Push-pull. See Note 4.

Port 3 pins serve alternate functions as follows:

10 11 5 I P3.0 RxD Serial receive port

11 13 7 O P3.1 TxD Serial transmit port (enabled only when transmitting serial data)

12 14 8 I P3.2 INT0 External interrupt 0

CMP3+ Comparator 3 positive input

13 15 9 I P3.3 INT1 External interrupt 1

CMP2+ Comparator 2 positive input

14 16 10 I P3.4 T0 Timer/counter 0 input

CMP1+ Comparator 1 positive input

15 17 11 I P3.5 T1 Timer/counter 1 input

CMPR– Common reference to comparators 1, 2, 3

16 18 12 O P3.6 WR External data memory write strobe

CMP0+ Comparator 0 positive input

17 19 13 O P3.7 RD External data memory read strobe

CMP0– Comparator 0 negative input

held low with the oscillator running for 24 oscillator cycles to initialize the internal registers. An internal diffused resistor to V capacitor to V with a slow rising input voltage.

. RST has a Schmitt trigger input stage to provide additional noise immunity

permits a power on reset using only an external

during an access to external memory. In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. ALE is switched off if the bit 0 in the AUXR register (8EH) is set. This pin is also the program pulse input (PROG

) during parallel EPROM programming. (See also I n t e r n a l Re s e t o n pa g e 2 4. )

executing code from the external program memory, PSEN cycle, except that two PSEN memory. PSEN

is not activated during fetches from internal program memory.

activations are skipped during each access to external data

31 35 29 I External Access Enable/Programming Supply Voltage: EA must be externally held low

to enable the device to fetch code from external program memory locations 0000H to 1FFFH. If EA

is held high, the device executes from internal program memory unless the

program counter contains an address greater than 1FFFH. This pin also receives the

12.75V programming supply voltage (V voltage during reset the device enters the in-circuit programming mode.

) during EPROM programming. If this pin is at V

circuits.

or ILC, as applicable.

83C576/87C576

is activated twice each machine

1998 Jun 04

Page 7

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

Table 1. 87C576 Special Function Registers

SYMBOL DESCRIPTION

ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H ADC0H# A/D Channel 0 MSB AAH 00H

ADC1H# A/D Channel 1 MSB ABH 00H ADC2H# A/D Channel 2 MSB ACH 00H ADC3H# A/D Channel 3 MSB ADH 00H ADC4H# A/D Channel 4 MSB AEH 00H ADC5H# A/D Channel 5 MSB AFH 00H ADC0L# A/D Channel 0 2-LSBits 9AH 00H ADC1L# A/D Channel 1 2-LSBits 9BH 00H ADC2L# A/D Channel 2 2-LSBits 9CH 00H ADC3L# A/D Channel 3 2-LSBits 9DH 00H ADC4L# A/D Channel 4 2-LSBits 9EH 00H ADC5L# A/D Channel 5 2-LSBits 9FH 00H

ADCON# A/D Control B1H ADF ADCE AD8M ADCS# A/D Channel Select B2H 00H

DIRECT

ADDRESS

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB

AMOD1

AMOD0

ASCA2 ASCA1

83C576/87C576

RESET VALUE

ASCA0 00H

AUXR# Auxiliary 8EH – – – – SRST TXI LO AO xxxx0000B B* B register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H CCAP0H# Module 0 Capture High FAH xxxxxxxxB

CCAP1H# Module 1 Capture High FBH xxxxxxxxB CCAP2H# Module 2 Capture High FCH xxxxxxxxB CCAP3H# Module 3 Capture High FDH xxxxxxxxB CCAP4H# Module 4 Capture High FEH xxxxxxxxB CCAP0L# Module 0 Capture Low EAH xxxxxxxxB CCAP1L# Module 1 Capture Low EBH xxxxxxxxB CCAP2L# Module 2 Capture Low ECH xxxxxxxxB CCAP3L# Module 3 Capture Low EDH xxxxxxxxB CCAP4L# Module 4 Capture Low EEH xxxxxxxxB

CCAPM0# Module 0 Mode DAH – ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B CCAPM1# Module 1 Mode DBH – ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B CCAPM2# Module 2 Mode DCH – ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B CCAPM3# Module 3 Mode DDH – ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B CCAPM4# Module 4 Mode DEH – ECOM CAPP CAPN MAT TOG PWM ECCF x0000000B

DF DE DD DC DB DA D9 D8

CCON*# PCA Counter Control D8H CF CR – CCF4 CCF3 CCF2 CCF1 CCF0 00x00000B CH# PCA Counter High F9H 00H CL# PCA Counter Low E9H 00H

CMOD# PCA Counter Mode D9H CIDL WDTE – – – CPS1 CPS0 ECF 00xxx000B

C7 C6 C5 C4 C3 C2 C1 C0 CMP*# Comparator C0H EC3DP EC2DP EC1DP EC0DP C3RO C2RO C1RO C0RO 00H CMPE# Comparator Enable 92H DPTR: Data Pointer (2 bytes)

DPH Data Pointer High 83H 00H DPL Data Pointer Low 82H 00H

IE0*# Interrupt Enable 0 A8H EA EC ET2 ES ET1 EX1 ET0 EX0 00H IE1*# Interrupt Enable 1 E8H EOB EIB EAD EC4 EC3 EC2 EC1 EC0 00H

* SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs.

EC3TDC EC2TDC EC1TDC EC0TDC

AF AE AD AC AB AA A9 A8

EC3O EC2O EC1O EC0O 00H

1998 Jun 04

Page 8

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

Table 1. 87C576 Special Function Registers (Continued)

SYMBOL DESCRIPTION

IP0* Interrupt Priority 0 B8H – PPC PT2 PS PT1 PX1 PT0 PX0 x0000000B IP1*# Interrupt Priority 1 F8H POB PIB PAD PC4 PC3 PC2 PC1 PC0 00H

P0* Port 0 80H AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FFH

P1* Port 1 90H – – ADIN5 ADIN4 ADIN3 ADIN2 ADIN1 ADIN0 FFH

P2* Port 2 A0H ECI CEX4 T2 T2EX CEX3 CEX2 CEX1 CEX0 FFH

P3* Port 3 B0H RD WR T1 T0 INT1 INT0 TxD RxD FFH

P0M1# Port 0 Output Mode 1 84H 00H P0M2# Port 0 Output Mode 2 85H 00H P1M1# Port 1 Output Mode 1 94H 00H P1M2# Port 1 Output Mode 2 95H 3FH P2M1# Port 2 Output Mode 1 A4H 00H P2M2# Port 2 Output Mode 2 A5H FFH P3M1# Port 3 Output Mode 1 B4H 00H P3M2# Port 3 Output Mode 2 B5H FFH

PCON Power Control 87H

PSW* Program Status Word D0H CY AC F0 RS1 RS0 OV – P 00H PWCON# PWM Control BCH – – – – PWMF PWMP# PWM Prescaler BDH 00H

PWM0# PWM Register 0 BEH 00H PWM1# PWM Register 1 BFH 00H

RACAP2H# RACAP2L#

Timer 2 Capture High CBH 00H Timer 2 Capture Low CAH 00H

DIRECT

ADDRESS

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB

BF BE BD BC BB BA B9 B8

87 86 85 84 83 82 81 80

97 96 95 94 93 92 91 90

A7 A6 A5 A4 A3 A2 A1 A0

B7 B6 B5 B4 B3 B2 B1 B0

SMOD1

SMOD0

D7 D6 D5 D4 D3 D2 D1 D0

OSF1POF1LVF

WDT0F

EN/CLR

83C576/87C576

PD IDL 00xxxx00B

PWE1 PWE0 00H

RESET VALUE

SADDR# Slave Address A9H 00H SADEN# Slave Address Mask B9H 00H

SBUF Serial Data Buffer 99H xxxxxxxxB

9F 9E 9D 9C 9B 9A 99 98 SCON* Serial Control 98H SP Stack Pointer 81H 07H

TCON* Timer Control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H

T2CON* Timer 2 Control C8H TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2 CP/RL2 00H T2MOD# Timer 2 Mode Control C9H – – – – – – T2OE2DCEN xxxxxxx0B

* SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs.

1. Reset value depends on reset source.

2. Programmable clock-out

1998 Jun 04

SM0/FE

8F 8E 8D 8C 8B 8A 89 88

CF CE CD CC CB CA C9 C8

SM1 SM2 REN TB8 RB8 TI RI 00H

Page 9

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

Table 1. 87C576 Special Function Registers (Continued)

SYMBOL DESCRIPTION

TH0 Timer High 0 8CH 00H TH1 Timer High 1 8DH 00H TH2# Timer High 2 CDH 00H TL0 Timer Low 0 8AH 00H TL1 Timer Low 1 8BH 00H TL2# Timer Low 2 CCH 00H

TMOD Timer Mode 89H GATE C/T M1 M0 GATE C/T M1 M0 00H UCS# UPI Control/Status 86H

DIRECT

ADDRESS

BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION MSB LSB

ST7 ST6 ST5 ST4 UE AF IBF

83C576/87C576

RESET VALUE

OBE/OBF

00H

WDCON#Watchdog Timer Control WDL#

WFEED1# Watchdog Feed 1 C2H xxH WFEED2# Watchdog Feed 2 C3H xxH

* SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs.

1. Reset value depends on reset source.

The 8XC576 has a number of failure detect circuits to prevent abnormal operating conditions. these failure detect circuits generate resets as shown in Figure 1.

Watchdog Timer Reload

POWER ON CLEAR / POWER ON FLAG

An on-chip Power On Detect Circuit resets the 8XC576 and sets the Power Off Flag (PCON.4) on power up or if V momentarily. The POF can only be cleared by software. The RST pin is not driven by the power on detect circuit. The POF can be read by software to determine that a power failure has occurred and can also be set by software.

LOW VOLTAGE DETECT

An on-chip Low Voltage Detect circuit sets the Low Voltage Flag (PCON.3) if V Characteristics) and resets the 8XC576 if the Low Voltage Reset Enable bit (WDCON.4) is set. If the LVRE is cleared, the reset is disabled but LVF will still be set if V driven by the low voltage detect circuit. The LVF can be read by software to determine that V cleared by software.

drops below V

LOW

was low. The LVF can be set or

OSCILLATOR FAIL DETECT

An on-chip Oscillator Fail Detect circuit sets the Oscillator Fail Flag (PCON.5) if the oscillator frequency drops below OSCF for one or more cycles (see AC Electrical Characteristics: OSCF) and resets the 8XC576 if the Oscillator Fail Reset Enable bit (WDCON.3) is set. If OFRE is cleared, the reset is disabled but OSF will still be set if the oscillator fails. The RST pin is not driven by the oscillator fail detect circuit. The OSF can be read by software to determine that an oscillator failure has occurred. The OSF can be set or cleared by software.

C4H PRE2 PRE1 PRE0 LVRE OFRE DPD C1H 00H

LOW ACTIVE RESET

One of the most notable features on this part is the low active reset. The low active reset operates exactly the same as high active reset with the exception that the part is put into the reset mode by applying a low level to the reset pin. For power-on reset it is also necessary to invert the power-on reset circuit; connecting the 8.2K resistor from the reset pin to V

drops to zero

(see DC Electrical

is low. The RST pin is not

reset pin to ground. Figure 1 shows the reset related circuitry. When reset the port pins on the 8XC576 are driven high

synchronously. The 8XC576 also has Low voltage detection circuitry that will, if

enabled, force the part to reset when V set level. Low Voltage Reset is enabled by a normal reset. Low Voltage Reset can be disabled by clearing LVRE (bit 4 in the WDCON SFR) then executing a watchdog feed sequence (A5H to WFEED1 followed immediately by 5AH to WFEED2). In addition there is a flag (LVF) that is set if a low voltage condition is detected. The LVF flag is set even if the Low Voltage detection circuitry is disabled. Notice that the Low voltage detection circuitry does not drive the RST# pin so the LVF flag is the only way that the microcontroller can determine if it has been reset due to a low voltage condition.

The 8XC576 has an on-chip power-on detection circuit that sets the POF (PCON.4) flag on power up or if the V drops to 0V . This flag can be used to determine if the part is being started from a power-on (cold start) or if a reset has occurred due to another condition (warm start).

The 8XC576 can be reset in software by setting the RST bit of the AUXR register (AUXR.3). See Figure 1 for reset diagram.

WDRUN

and the 10µf capacitor from the

WDMOD

(on the part) fails below a

level momentarily

11111111B

1998 Jun 04

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Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

83C576/87C576

VLOW

(LOW V

REFERENCE)

– – – SRST TXI LO AO

POWER-ON DETECT

–

RST

WATCHDOG FEED

SMOD1 SMOD0 OSF LVF WDTOF PD IDL

OSC FREQ BELOW OSCF

(MIN FREQUENCY)

SHADOW REGISTER

FOR WDCON

PRE2 PRE1 PRE0 LVRE OFRE DPD WDRUN WDMOD

CIDL WDTE – – – CPS1 CPS0 ECF

–

POF

SHADOW REGISTER

AUXR

(8EH)

PCON

(87H)

8xC576 INTERNAL RESET

WDTE

PCA WATCHDOG WATCHDOG TIMER

WDCON

(C4H)

CMOD

(D9H)

SU00515B

Figure 1. Reset Circuitry

TIMERS

The 8XC576 has four on-chip timers. Timers 0 and 1 are identical in every way to Timers 0 and 1 on the

80C51. Timer 2 on the 8XC576 is identical to the 80C52 Timer 2 (described

in detail in the 80C52 overview) with the exception that it is an up or down counter. To configure the Timer to count down the DCEN bit in the T2MOD special function register must be set and a low level must be present on the T2EX pin (P1.1).

The Pulse Width Modulator (PWM) system can be used as a timer by disabling its outputs and monitoring its counter overflow flag, the PWMF bit in the PWCON register (see the PWM section for details).

The Watchdog timer operation and implementation is similar to the 8XC550 (for additional information see the 8XC550 datasheet) with the exception that the reset values of the WDCON and WDL special function registers have been changed. The changes in these registers cause the watchdog timer to be enabled with a timeout of 16384 × T

when the part is reset. The watchdog can be disabled

OSC

by executing a valid feed sequence and then clearing WDRUN (bit 2 in the WDCON SFR). In timer mode, the timer is controlled by toggling the WDRUN bit. The timeout flag, WDTOF, is set when the timer overflows and must be cleared in software.

PROGRAMMABLE COUNTER ARRAY (PCA)

The Programmable Counter Array is a special Timer that has five 16-bit capture/compare modules associated with it. Each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator . Each module has a pin associated with it in port 2. Module 0 is connected to P2.0(CEX0), module 1 to P2.1(CEX1), etc. The basic PCA configuration is shown in Figure 2.

The PCA timer is a common time base for all five modules and can be programmed to run at: 1/12 the oscillator frequency, 1/4 the oscillator frequency , the Timer 0 overflow, or the input on the ECI pin (P2.7). The timer count source is determined from the CPS1 and CPS0 bits in the CMOD SFR as follows (see Figure 3):

CPS1 CPS0 PCA Timer Count Source

0 0 1/12 oscillator frequency 0 1 1/4 oscillator frequency 1 0 Timer 0 overflow 1 1 External Input at ECI pin (P2.7)

In the CMOD SFR are three additional bits associated with the PCA. They are CIDL which allows the PCA to stop during idle mode, WDTE which enables or disables the watchdog function on module 4, and ECF which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set when the PCA timer overflows. These functions are shown in Figure 3.

The watchdog timer function is implemented in module 4 as implemented in other parts that have a PCA that are available on the market. However, if a watchdog timer is required in the target application, it is recommended to use the hardware watchdog timer that is implemented on the 87C576 separately from the PCA (see Figure 15).

The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module (refer to Figure 6). To run the PCA the CR bit (CCON.6) must be set by software. The PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set, The CF bit can only be cleared by software. Bits 0 through 4 of the CCON register are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags

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Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

83C576/87C576

also can only be cleared by software. The PCA interrupt system shown in Figure 4.

Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module 0, CCAPM1 for module 1, etc. (see Figure 7). The registers contain the bits that control the mode that each module will operate in. The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module. PWM (CCAPMn.1) enables the pulse width modulation mode. The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the module’s capture/compare register. The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the module’s capture/compare register.

The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. Figure 8 shows the CCAPMn settings for the various PCA functions.

There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output.

PCA Capture Mode

To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 2) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the module’s capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated. Refer to Figure 9.

16-bit Software Timer Mode

The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMn register. The PCA timer will be compared to the module’s capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (see Figure 10).

High Speed Output Mode

In this mode the CEX output (on port 2) associated with the PCA module will toggle each time a match occurs between the PCA counter and the module’s capture registers. To activate this mode the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR must be set (see Figure 11).

Pulse Width Modulator Mode

All of the PCA modules can be used as PWM outputs. Figure 12 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the modules will have the same frequency of output because they all share the PCA timer. The duty cycle of each module is independently variable using the module’s capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module’s CCAPLn SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPLn is reloaded with the value in CCAPHn. the allows updating the PWM without glitches. The PWM and ECOM bits in the module’s CCAPMn register must be set to enable the PWM mode.

PCA Interrupt System

The PCA on most 80C51 family devices provides a single interrupt source, EC (IE.6). The 8xC576 expands the flexibility of the PCA by providing additional interrupt sources for each of the five PCA modules, EC0 (IE1.0) through EC4 (IE1.4), in addition to the original interrupt source EC (IE.6). Any of these sources can be enabled at any time. It is possible for both a module source (EC0 through EC4) to be enabled at the same time that the single source, EC, is enabled. In this case, a module event will generate an interrupt for both the module source and the single source, EC.

MODULE FUNCTIONS:

16-BIT CAPTURE 16-BIT TIMER 16-BIT HIGH SPEED OUTPUT 8-BIT PWM WATCHDOG TIMER (MODULE 4 ONLY)

1998 Jun 04

16 BITS

PCA TIMER/COUNTER

TIME BASE FOR PCA MODULES

16 BITS

MODULE 0

MODULE 1

MODULE 2

MODULE 3

MODULE 4

Figure 2. Programmable Counter Array (PCA)

P2.0/CEX0

P2.1/CEX1

P2.2/CEX2

P2.3/CEX3

P2.6/CEX4

SU00578

Page 12

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

OSC/12

83C576/87C576

TO PCA

MODULES

OSC/4

TIMER 0

OVERFLOW

EXTERNAL INPUT

(P2.7/ECI)

IDLE

PCA TIMER/COUNTER

OVERFLOW

CH CL

16–BIT UP COUNTER

00 01

DECODE

CIDL WDTE –– –– –– CPS1 CPS0 ECF

CF CR CCF4 CCF3 CCF2 CCF1 CCF0––

Figure 3. PCA Timer/Counter

CF CR CCF4 CCF3 CCF2 CCF1 CCF0––

CMOD

(D9H)

CCON

(D8H)

CCON

(D8H)

INTERRUPT

SU00516

MODULE 0

MODULE 1

MODULE 2

MODULE 3

MODULE 4

CMOD.0 ECF

CCAPMn.0 ECCFn

Figure 4. PCA Interrupt System

IE1.0

EC0

IE1.1

EC1

IE0.6

IE1.2

EC2

IE1.3

EC3

IE1.4

EC4

IE0.7

TO INTERRUPT PRIORITY DECODER

SU00579

1998 Jun 04

Page 13

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

83C576/87C576

CMOD Address = OD9H

Reset Value = 00XX X000B

CIDL WDTE – – – CPS1 CPS0 ECF

Bit:

76543210

Symbol Function

CIDL Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode.

CIDL = 1 programs it to be gated off during idle. WDTE Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it. – Not implemented, reserved for future use.*

CPS1 PCA Count Pulse Select bit 1. CPS0 PCA Count Pulse Select bit 0.

CPS1 CPS0 Selected PCA Input**

0 0 0 Internal clock, f 0 1 1 Internal clock, f

OSC OSC

÷ 12

÷ 4 1 0 2 Timer 0 overflow 1 1 3 External clock at ECI/P2.7 pin (max. rate = f

OSC

÷ 8)

ECF PCA Enable Counter Overflow interrupt:

ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables that function of CF.

NOTE:

* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the

new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

= oscillator frequency

** –f

OSC

SU00686A

Figure 5. CMOD: PCA Counter Mode Register

CCON Address = OD8H

Reset Value = 00X0 0000B

Bit Addressable

CF CR – CCF4 CCF3 CCF2 CCF1 CCF0

Bit:

76543210

Symbol Function CF PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is

set. CF may be set by either hardware or software but can only be cleared by software.

CR PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA

counter off.

– Not implemented, reserved for future use*.

CCF4 PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF3 PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF2 PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF1 PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF0 PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software.

NOTE:

* User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the

new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

SU00036

Figure 6. CCON: PCA Counter Control Register

1998 Jun 04

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Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

83C576/87C576

CCAPMn Address CCAPM0 0DAH

Not Bit Addressable

Bit:

Symbol Function – Not implemented, reserved for future use*.

ECOMn Enable Comparator. ECOMn = 1 enables the comparator function. CAPPn Capture Positive, CAPPn = 1 enables positive edge capture. CAPNn Capture Negative, CAPNn = 1 enables negative edge capture. MATn Match. When MATn = 1, a match of the PCA counter with this module’s compare/capture register causes the CCFn bit

TOGn Toggle. When TOGn = 1, a match of the PCA counter with this module’s compare/capture register causes the CEXn

PWMn Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output. ECCFn Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt.

NOTE:

*User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

in CCON to be set, flagging an interrupt.

pin to toggle.

CCAPM1 0DBH CCAPM2 0DCH CCAPM3 0DDH CCAPM4 0DEH

– ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

76543210

Figure 7. CCAPMn: PCA Modules Compare/Capture Registers

Reset Value = X000 0000B

SU00037

ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn MODULE FUNCTION

–

X 0 0 0 0 0 0 0 No operation X X 1 0 0 0 0 X 16-bit capture by a positive-edge trigger on CEXn X X 0 1 0 0 0 X 16-bit capture by a negative trigger on CEXn X X 1 1 0 0 0 X 16-bit capture by a transition on CEXn X 1 0 0 1 0 0 X 16-bit Software Timer X 1 0 0 1 1 0 X 16-bit High Speed Output X 1 0 0 0 0 1 0 8-bit PWM X 1 0 0 1 X 0 X Watchdog Timer

Figure 8. PCA Module Modes (CCAPMn Register)

1998 Jun 04

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Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

83C576/87C576

CEXn

WRITE TO

CCAPnL

WRITE TO

CCAPnH

CF CR CCF4 CCF3 CCF2 CCF1 CCF0––

(TO CCFn)

CAPTURE

–– ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

0 000

Figure 9. PCA Capture Mode

CF CR CCF4 CCF3 CCF2 CCF1 CCF0––

RESET

CCAPnL

(TO CCFn)

MATCH

ENABLE

CCAPnH

16–BIT COMPARATOR

CCON

(D8H)

PCA TIMER/COUNTER

CH CL

CCAPnH CCAPnL

CCAPMn, n= 0 to 4

(DAH – DEH)

PCA INTERRUPT

SU00749

CCON

(D8H)

PCA INTERRUPT

CH CL

PCA TIMER/COUNTER

–– ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

0000

Figure 10. PCA Compare Mode

CCAPMn, n= 0 to 4

(DAH – DEH)

SU00750

1998 Jun 04

Page 16

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

83C576/87C576

WRITE TO

CCAPnL

WRITE TO

CCAPnH

RESET

ENABLE

CF CR CCF4 CCF3 CCF2 CCF1 CCF0––

CCAPnH CCAPnL

16–BIT COMPARATOR

CH CL

PCA TIMER/COUNTER

–– ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

MATCH

(TO CCFn)

1000

Figure 11. PCA High Speed Output Mode

CCAPnH

CCON

(D8H)

PCA INTERRUPT

TOGGLE

CCAPMn, n: 0..4

(DAH – DEH)

CEXn

SU00751

CCAPnL

ENABLE

OVERFLOW

–– ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

8–BIT

COMPARATOR

PCA TIMER/COUNTER

CL < CCAPnL

CL >= CCAPnL

0000

Figure 12. PCA PWM Mode

CCAPMn, n: 0..4

(DAH – DEH)

SU00752

CEXn

1998 Jun 04

Page 17

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

83C576/87C576

WATCHDOG TIMER

The watchdog timer is not directly loadable by the user. Instead, the value to be loaded into the main timer is held in an autoload register or is part of the mask ROM programming. In order to cause the main timer to be loaded with the appropriate value, a special sequence of software action must take place. This operation is referred to as feeding the watchdog timer.

To feed the watchdog, two instructions must be sequentially executed successfully. No intervening instruction fetches are allowed, so interrupts should be disabled before feeding the watchdog. The instructions should move A5H to the WFEED1 register and then 5AH to the WFEED2 register. If WFEED1 is correctly loaded and WFEED2 is not correctly loaded, then an immediate underflow will occur.

The watchdog timer subsystem has two modes of operation. Its principal function is a watchdog timer. In this mode it protects the system from incorrect code execution by causing a system reset when the watchdog timer underflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count. If the user does not employ the watchdog function, the watchdog subsystem can be used as a timer. In this mode, reaching the terminal count sets a flag. In most other respects, the timer mode possesses the characteristics of the watchdog mode. This is done to protect the integrity of the watchdog function.

The watchdog timer subsystem consists of a prescaler and a main counter. The prescaler has 8 selectable taps of f the final stages and the output of a selected tap provides the clock to the main counter. The main counter is the section that is loaded as a result of the software feeding the watchdog and it is the section that causes the system reset (watchdog mode) or time-out flag to be set (timer mode) if allowed to reach its terminal count.

Programming the Watchdog Timer

Both the EPROM and ROM devices have a set of SFRs for holding the watchdog autoload values and the control bits. The watchdog time-out flag is present in the PCON register and operates the same in all versions. In the EPROM device, the watchdog parameters (autoload value and control) are always taken from the SFRs. In the ROM device, the watchdog parameters can be mask programmed or taken from the SFRs. The selection to take the watchdog parameters from the SFRs or from the mask programmed values is controlled by EA (external access). When EA is high (internal ROM access), the watchdog parameters are taken from the mask programmed values. If the watchdog is mask programmed to the timer mode, then the autoload values and the pre-scaler taps are taken from the SFRs. When EA is low (external access), the watchdog parameters are taken from the SFRs. The user should be able to leave code in his program which initializes the watchdog SFRs even though he has migrated to the mask ROM part. This allows no code changes from EPROM prototyping to ROM coded production parts. The run control bit only functions in timer mode and does not require a feed sequence to modify.

Watchdog Detailed Operation

EPROM Device (and ROMless Operation: EA = 0)

In the ROMless operation (ROM part, EA = 0) and in the EPROM device, the watchdog operates in the following manner (see Figure 15).

Whether the watchdog is in the watchdog or timer mode, when external RESET is applied, the following takes place:

•Watchdog mode bit set to watchdog mode.

•Watchdog is running.

•Autoload register set to 00 (min. count).

•Watchdog time-out flag is unchanged.

•Prescaler is cleared.

•Prescaler tap set to the highest divide.

•Autoload takes place.

The watchdog can be fed even though it is in the timer mode. Note that the operational concept is for the watchdog mode of

operation, when coming out of a hardware reset, the software should load the autoload registers, set the mode to watchdog, clear the watchdog timeout flag, and then feed the watchdog (cause an autoload). The watchdog will now be starting at a known point.

If the watchdog is in the watchdog mode and running and happens to underflow at the time the external RESET is applied, the watchdog time-out flag will be set.

When the watchdog is in the watchdog mode and the watchdog underflows, the following action takes place (see Figure 17):

•Autoload takes place.

•Watchdog time-out flag is set

•Mode bit unchanged.

•Watchdog run bit unchanged.

•Autoload register unchanged.

•Prescaler tap unchanged.

•All other device action same as external reset.

Note that if the watchdog underflows, the program counter will start from 00H as in the case of an external reset. The watchdog time-out flag can be examined to determine if the watchdog has caused the reset condition. The watchdog time-out flag bit must be cleared by software.

When the watchdog is in the timer mode and the timer software underflows, the following action takes place:

•Autoload takes place.

•Watchdog time-out flag is set

•Mode bit unchanged.

•Watchdog run bit unchanged.

•Autoload register unchanged.

•Prescaler tap unchanged.

Mask ROM Device (EA = 1)

In the mask ROM device, the watchdog mode bit (WDMOD) is mask programmed and the bit in the watchdog command register is read only and reflects the mask programmed selection. If the mask programmed mode bit selects the timer mode, then the watchdog run bit (WDRUN) operates as described under EPROM Device. If the mask programmed bit selects the watchdog mode, then the watchdog run bit has no effect on the timer operation (see Figure 16).

Watchdog Function

The watchdog consists of a programmable prescaler and the main timer. The prescaler derives its clock from the on-chip oscillator. The prescaler consists of a divide by 2 followed by a 13 stage upcounter with taps from stage 6 through stage 13. This is shown in Figure 18.

1998 Jun 04

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Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

83C576/87C576

The tap selection is programmable. The watchdog main counter is a down counter clocked (decremented) each time the programmable prescaler overflows. The watchdog generates an underflow signal (and is autoloaded) when the watchdog is at count 0 and the prescaler clock decrements the watchdog. The watchdog is 8 bits long and the autoload value can range from 0 to FFH. (The autoload value of 0 is permissible since the prescaler is cleared upon autoload).

This leads to the following user design equations. Definitions :t

OSC

is the oscillator period, N is the selected prescaler tap value, W is the main counter autoload value, t time-out value (when the autoload value is 0), t time-out value (when the autoload value is FFH), t

is the minimum watchdog

MIN

is the maximum

MAX

is the design

time-out value. t

= t

MIN

OSC

MIN

× 2 × 64 × 128 × 256

PRESCALER

× 2

× (W + 1)

MIN

MAX

tD = t (where prescaler = 0, 1, 2, 3, 4, 5, 6, or 7)

Note that the design procedure is anticipated to be as follows. A t

will be chosen either from equipment or operation

MAX

considerations and will most likely be the next convenient value higher than t

. (If the watchdog were inadvertently to start from 00H,

an underflow would be guaranteed, barring other anomalies, to occur within t

MAX

The software must be written so that a feed operation takes place

seconds from the last feed operation. Some tradeoffs may

every t

need to be made. It is not advisable to include feed operations in minor loops or in subroutines unless the feed operation is a specific subroutine.

Watchdog Control Register (WDCON) Address C4H

The following bits of this register are read only in the ROM part when EA

is high: WDMOD, DPD, OFRE, LVRE, PRE0, PRE1, and PRE2. That is, the register will reflect the mask programmed values. In the ROM part with EA

high, these bits are taken from mask coded bits and are not readable by the program. WDRUN is read only in the ROM part when EA

is high and WDMOD is in the watchdog mode. When WDMOD is in the timer mode, WDRUN functions normally .

The parameters written into WDMOD, DPD, OFRE, LVRE, PRE0, PRE1, and PRE2 by the program are not applied directly to the watchdog timer subsystem. The watchdog timer subsystem is directly controlled by a second register which stores these bits. The transfer of these bits from the user register to the second control register takes place when the watchdog is fed. This prevents random code execution from directly foiling the watchdog function. This does not affect the operation where these bits are taken from mask coded values.

The reset values of the WDCON and WDL registers will be such that the timer resets to the watchdog mode with a timeout period of 2 × 64 × 128 × t

. The watchdog timer does not generate an interrupt.

OSC

Additional bits in WDCON are used to disable reset generation by the oscillator fail and low voltage detect circuits. WDCON can be written by software only by executing a valid watchdog feed sequence.

WDCON Register Bit Definitions

WDCON.7 PRE2 Prescaler Select 2, reset to 1 WDCON.6 PRE1 Prescaler Select 1, reset to 1 WDCON.5 PRE0 Prescaler Select 0, reset to 1 WDCON.4 LVRE Low Voltage Reset Enable, reset to 1

(enabled)

WDCON.3 OFRE Oscillator Fail Reset Enable, reset to 1

(enabled) WDCON.2 DPD Disable Power Down WDCON.1 WDRUN Watchdog Run, reset to 1 (enabled) WDCON.0 WDMOD Watchdog Mode, reset to 1 (watchdog

mode)

Enhanced UART

The UART operates in all of the usual modes that are described in the first section of this book for the 80C51. In addition the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The 8XC576 UART also fully supports multiprocessor communication as does the standard 80C51 UART.

When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bit in the SCON register. The FE bit shares the SCON.7 bit with SM0 and the function of SCON.7 is determined by PCON.6 (SMOD0) (see Figure

20). If SMOD0 is set then SCON.7 functions as FE. SCON.7 functions as SM0 when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 19.

The serial port transmitter data can be inverted by setting the TXI (AUXR.2) bit. For normal operation, the TXI bit should be cleared.

Automatic Address Recognition

Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the “Given” address or the “Broadcast” address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 21.

The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address.

Mode 0 is the Shift Register mode and SM2 is ignored.

1998 Jun 04

Page 19

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

TXD

TXI

INT. BUS

WRITE TO LATCH

Figure 13. TXI (AUXR.2) Bit Inverts the TxD Pin (P3.1) When Set

P3.1

LATCH

PROGRAMMABLE OUTPUT BUFFER

83C576/87C576

P3.1

SU00711

WRITE TO CCAP4H

WRITE TO CCAP4L

WATCHDOG FEED SEQUENCE

MOV WFEED1,#0A5H MOV WFEED2,#5AH

RESET

ENABLE

CIDL WDTE –– –– –– CPS1 CPS0 ECF

CCAP4H CCAP4L

16–BIT COMPARATOR

CH CL

PCA TIMER/COUNTER

–– ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

MATCH

X000

Figure 14. PCA Watchdog Timer

WDL (C1H)

WDTOF (PCON.2)

CMOD (D9H)

RESET

CCAPM4 (DEH)

SU00042

OSC/2

1998 Jun 04

PRESCALER

PRE2 PRE1 PRE0 LVRE OFRE DPD WDRUN WDMOD

8–BIT DOWN

COUNTER

Figure 15. Watchdog Timer in 87C576 and 80C576 / 83C576 (EA = 0)

RESET

SHADOW REGISTER

FOR WDCON

WDCON

(C4H)

SU00657C

Page 20

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

83C576/87C576

ROM–CODE

WATCHDOG FEED SEQUENCE

MOV WFEED1,#0A5H MOV WFEED2,#5AH

Figure 16. Watchdog Timer of 83C576 in Watchdog Mode (EA = 1, WDMOD = 1)

WATCHDOG FEED SEQUENCE

MOV WFEED1,#0A5H MOV WFEED2,#5AH

PRESCALEROSC/2

PRE2 PRE1 PRE0 LVRE OFRE DPD WDRUN WDMOD

8–BIT DOWN

COUNTER

WDL (C1H)

CONTENT WDL WDCON

RESET WDTOF (PCON.2)

WDCON

(C4H)

ROM–CODE

CONTENT WDCON

ADDRESS

2031H 2030H

SU00658C

ADDRESS

2030H

PRESCALEROSC/2

PRE2 PRE1 PRE0 LVRE OFRE DPD WDRUN WDMOD

8–BIT DOWN

COUNTER

Figure 17. Watchdog Timer of 83C576 in Timer Mode (EA = 1, WDMOD = 0)

WDTOF (PCON.2)

WDCON

(C4H)

SU00659C

1998 Jun 04

Page 21

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

83C576/87C576

OSC/2 ÷64

PRE2 PRE1

PRE0

DECODE

÷64 ÷128 ÷256 ÷512 ÷1024 ÷2048 ÷4096 ÷8192

000 001 010 011 100 101 110 111

÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2

TO WATCHDOG

DOWN COUNTER

SU00660

Figure 18. Watchdog Prescaler

SCON Address = 98H

Reset Value = 0000 0000B

Bit Addressable

SM0/FE SM1 SM2 REN TB8 RB8 Tl Rl

Bit: 76543210

(SMOD0/1)*

Symbol Function FE Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid

frames but should be cleared by software. The SMOD0 bit must be set to enable access to the FE bit.

SM0 Serial Port Mode Bit 0, (SMOD0 must = 0 to access bit SM0) SM1 Serial Port Mode Bit 1

SM0 SM1 Mode Description Baud Rate**

0 0 0 shift register f

OSC

/12 0 1 1 8-bit UART variable 1 0 2 9-bit UART f

OSC

/64 or f

OSC

/32

1 1 3 9-bit UART variable

SM2 Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then Rl will not be set unless the

received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1 then Rl will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0.

REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8 In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.

In Mode 0, RB8 is not used.

Tl Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the

other modes, in any serial transmission. Must be cleared by software.

Rl Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in

the other modes, in any serial reception (except see SM2). Must be cleared by software.

NOTE:

*SMOD0/1 is located at PCON.6, PCON.7 **f

= oscillator frequency

OSC

Figure 19. SCON: Serial Port Control Register

SU00766

1998 Jun 04

Page 22

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

D0 D1 D2 D3 D4 D5 D6 D7 D8

83C576/87C576

START

BIT

SM0 / FE SM1 SM2 REN TB8 RB8 TI RI

SMOD1 SMOD0 – POF LVF GF0 GF1 IDL

0 : SCON.7 = SM0 1 : SCON.7 = FE

Figure 20. UART Framing Error Detection

Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slave’s address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to be used and which bits are “don’t care”. The SADEN mask can be logically ANDed with the SADDR to create the “Given” address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme:

Slave 0 SADDR = 1100 0000

SADEN = 1111 1101 Given = 1100 00X0

Slave 1 SADDR = 1100 0000

SADEN = 1111 1110 Given = 1100 000X

In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000.

In a more complex system the following could be used to select slaves 1 and 2 while excluding slave 0:

Slave 0 SADDR = 1100 0000

SADEN = 1111 1001 Given = 1100 0XX0

DATA BYTE

SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR)

SM0 TO UART MODE CONTROL

Slave 1 SADDR = 1110 0000

SADEN = 1111 1010 Given = 1110 0X0X

Slave 2 SADDR = 1110 0000

SADEN = 1111 1100 Given = 1110 00XX

In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary t make bit 2 = 1 to exclude slave 2.

The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are treated as don’t-cares. In most cases, interpreting the don’t-cares as ones, the broadcast address will be FF hexadecimal.

Upon reset SADDR (SFR address 0A9H) and SADEN (SFR address 0B9H) are loaded with 0s. This produces a given address of all “don’t cares” as well as a Broadcast address of all “don’t cares”. this effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature.

Analog Comparators

Four analog comparators are provided on chip. Three comparators have a common negative reference CMPR- and independent positive inputs CMP1+, CMP2+, CMP3+ on port 3. The fourth comparator has independent positive and negative inputs CMP0+ and CMP0- on port 2. The CMP register contains an output and enable bit for each comparator. Figure 22 shows the connection of the comparators.

When the comparator is enabled, the port should be configured by the user as high impedance.

ONLY IN

MODE 2, 3

SCON

(98H)

PCON

(87H)

STOP

BIT

SU00044

1998 Jun 04

Page 23

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

D0 D1 D2 D3 D4 D5 D6 D7 D8

83C576/87C576

SM0 SM1 SM2 REN TB8 RB8 TI RI

1 1

RECEIVED ADDRESS D0 TO D7

PROGRAMMED ADDRESS

IN UART MODE 2 OR MODE 3 AND SM2 = 1: INTERRUPT IF REN=1, RB8=1 AND “RECEIVED ADDRESS” = “PROGRAMMED ADDRESS” – WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES – WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS.

Figure 21. UART Multiprocessor Communication, Automatic Address Recognition

CMP Register Bit Definitions

CMP.7 enable comparator 3 CMP.6 enable comparator 2 CMP.5 enable comparator 1, CMP.4 enable comparator 0 CMP.3 comparator 3 output (read only) CMP.2 comparator 2 output (read only) CMP.1 comparator 1 output (read only) CMP.0 comparator 0 output (read only)

All comparators are disabled automatically in power down mode. In idle mode unused comparators should be disabled by software to save power. A comparator can generate an interrupt that will terminate idle mode when used to drive a PCA capture input.

The CMPE register contains bits to enable each comparator to drive external output pins or internal PCA capture inputs. When the comparator is configured for external output, the user must also configure the output port in one of its output modes. The comparator output is wire-ORed with the corresponding port SFR bit, so the SFR bit must also be set by software to enable the output.

CMPE Register Bit Definitions

CMPE.7 enables comparator 3 to drive CEX3 CMPE.6 enables comparator 2 to drive CEX2 CMPE.5 enables comparator 1 to drive CEX1 CMPE.4 enables comparator 0 to drive CEX0 CMPE.3 enables comparator 3 output on P2.3 CMPE.2 enables comparator 2 output on P2.2 CMPE.1 enables comparator 1 output on P2.1 CMPE.0 enables comparator 0 output on P2.0

When 1s are written to CMPE bits 7-4, the comparator outputs will drive the corresponding capture input. When 1s are written to CMPE bits 3-0 the comparator output will also drive the corresponding port 2 pin. If the comparator’s enabled to drive the capture input but not the port pin, then the port pin can be used for general purpose I/O. When a comparator output is enabled, the user will need to configure the port for one of its output modes.

There are two special function registers associated with the comparators. They are CMP which contains the comparator enables

1 0

11 X

COMPARATOR

and a bit that can be read by software to determine the state of each comparator’s output, and CMPE which controls whether the output from each comparator drives the associated output pin or a capture input associated with one of the PCA modules.

The CMP registers bits 0–3 can be read by software to determine the state of the output of each comparator. To do this the associated comparator must be enabled but the output in port 2 can be disabled. This allows easy polling of the comparator output value without the need to use up a port pin.

The CMPE register allows the comparator to drive the associated PCA module capture input, so that on compare a capture can be generated in the PCA. Bits 0–3 of this register enable the comparator output to drive the associated port 2 output circuitry. Used as a comparator output, the output mode for this port must be configured for output by the user and the port output SFR bit latch must be set. If the comparator is not enabled to drive the port 2 circuitry, the associated port 2 pin can be used for other I/O. This includes when a comparator is enabled to drive the capture input to a PCA module.

Reduced EMI Mode

There are two bits in the AUXR register that can be set to reduce the internal clock drive and disable the ALE output. AO (AUXR.0) when set turns off the ALE output. LO (AUXR.1) when set reduces the drive of the internal clock circuitry. Both bits are cleared on Reset. With LO set the 8XC576 will still operate at 12MHz, and will have reduced EMI in the range above 100MHz.

8XC576 Reduced EMI Mode

AUXR (0X8E)

–– –– –– –– RST TXI LO AO

AO: Turns off ALE output. LO: Reduces drive of internal clock circuitry. 8XC576 spec’d to

12MHz when LO set. TXI: Inverts TxD when set. RST: Software reset.

SCON

(98H)

SU00045

1998 Jun 04

Page 24

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

83C576/87C576

EC3TDC EC2TDC EC1TDC EC0TDC EC3OD * EC2OD * EC1OD * EC0OD *

P3.6 / CMP0+ P3.7 / CMP0–

P3.4 / CMP1+

P3.3 / CMP2+

P3.2 / CMP3+ P3.5 / CMPR–

* : WILL DISABLE PULLUPS ON RELEVANT PINS

–

ENABLE

+ –

ENABLE

+ –

ENABLE

–

ENABLE

EC3DP * EC2DP * EC1DP * EC0DP * C3RO C2RO C1RO C0RO

Figure 22. Analog Comparators

INTERNAL RESET

Internal resets (see Figure 1) generated by the power on, low voltage, software (SRST), watchdog and oscillator fail detect circuits are self timed to guarantee proper initialization of the 8XC576. Reset will be held approximately 24 oscillator periods after normal conditions are detected by all enabled detect circuits. Internal resets do not drive RST

but will cause missing pulses on ALE.

Analog to Digital Converter

The 8XC576 has a 6 channel10 bit successive approximation A/D converter with separate result registers for each channel. Operating modes are provided for single or multiple channel conversions and multiple conversions of a single channel without software intervention. The ADC can also be operated in 8 bit mode with faster conversion times. Registers ADC0H–ADC5H contain the MSBs and ADC0L–ADC5L bits 6 and 7 contain the 2 LSBs of the conversion result for each channel. The ADCS register determines which channels are converted in multiple channel modes. If the ADCS bit corresponding to a channel is set, that channel is converted, else if the bit is clear the channel is skipped.

A/D Channel Select (ADCS) Register (Reset Value = 00H)

ADCS5 ADCS.5 – A/D channel 5 select bit ADCS4 ADCS.4 – A/D channel 4 select bit ADCS3 ADCS.3 – A/D channel 3 select bit ADCS2 ADCS.2 – A/D channel 2 select bit ADCS1 ADCS.1 – A/D channel 1 select bit ADCS0 ADCS.0 – A/D channel 0 select bit

A/D Control (ADCON) Register (Reset Value = 00H)

ADF ADCON.7 – A/D conversion complete flag ADCE ADCON.6 – A/D conversion enable AD8M ADCON.5 – A/D 8-bit mode

CMPE

P2.0 / CMP0

TO CEX0 INPUT OF

PCA MODULE 0

P2.1 / CMP1

TO CEX1 INPUT OF

PCA MODULE 1

P2.2 / CMP2

TO CEX2 INPUT OF

PCA MODULE 2

P2.3 / CMP3

TO CEX3 INPUT OF

PCA MODULE 3

CMP

(C0H)

SU00517C

AMOD1 ADCON.4 –A/D mode select bit 1 AMOD0 ADCON.3 –A/D mode select bit 0 ASCA2 ADCON.2 – A/D channel address bit 2 ASCA1 ADCON.1 – A/D channel address bit 1 ASCA0 ADCON.0 – A/D channel address bit 0

AMOD1 AMOD0

0 0 Single Conversion Mode – channel selected by bits

ASCA2..0 in ADCON is converted, the result placed in the associated result registers; ADF is set on completion.

0 1 Mulitple Channel Scan Mode – all channels selected

in the ADCS register are converted starting with the channel addressed by bits ASCA2..0 in ADON, conversion results are placed in the corres ponding result r egisters for each channel. ADF is set when the last conversion is completed.

1 0 Single Channel Multiple Conversion – channel

selected by bits ASCA2..0 in ADCON is converted 6 times and all 6 results are saved in ADC0H–ADC5H and ADC0L–ADC5L, ADF is set when all conversions are complete.

1 1 Multiple Channel Continuous – same as Multiple

Channel Scan mode but repeats as long as ADCE=1, ADF is set when all channels have been converted once. Hardware will prevent the ADC from wiriting to the result registers while they are being read.

Flag ADF is set upon completion of a conversion, if the ADC interrupt enable bit EAD is set, the program will vector to the ADC interrupt location when ADF is set.

(92H)

1998 Jun 04

Page 25

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

83C576/87C576

PWMs

The pulse width modulator system of the 8XC576 contains two PWM output channels. These channels generate pulses of programmable length and interval. The prescaler and counter are common to both PWM channels.

The prescaler is loaded with the complement of the PWMP register during counter overflow, internal reset, and when EN/CLR# = 0. The repetition frequency is defined by the 8-bit prescaler which clocks the counter. The prescaler division factor = PWMP+1. Reading the PWMP gives the current reload value. The actual count of the prescaler cannot be read.

The 8-bit counter counts from 0–254 inclusive. The value of the counter is compared to the contents of the compare registers PWM0 and PWM1. When the counter compares to the compare register, that register’s output goes LOW. When the counter reaches zero the output is set HIGH unless PWMn = 00H. The duty cycle of each channel is defined by the contents of its compare register and is in the range of 0 to 1, programmed in increments of 1/255.

The outputs can be set continuously low by loading PWMn with 00H and continuously high by loading with FFH.

The PWM counter is enabled with bit EN/CLR# of the PWCON register. Output to the port pin is separately enabled by setting the PWEn bits in the PWCON register. The counter remains active if EN/CLR# is set even if both PWEn bits are reset. The PWM function is reset by a chip reset. In idle mode, the PWM will function as configured by PWCON. In power-down the state of the PWM will freeze when the internal clock stops. If the chip is awakened with an external interrupt, the PWM will continue to function from its state when power-down was entered. The EN/CLR# bit of PWCON will clear the counter and load the contents of the PWMP into the prescaler when set LOW. If PWEn is set at this time the output will go HIGH unless PWMn is 00H.

The repetition frequency is given by:



PWM

(510  (1  PWMP))

An oscillator frequency of 12MHz results in a repetition range of 92Hz to 23.5KHz.

The high/low ratio of PWMn is PWMn/(255–PWMn) for PWMn values except 255. A PWMn value of 255 results in a high PWMn output.

In order for the PWMn output to be used as a standard I/O pin, PWMn must be reset. The PWM counter can still be used as an internal timer by setting EN/CLR#.

OSC

Pulse Width Modulator Control Register Bit Definitions (PWCON = BCH)

PWMF PWCON.3 Counter overflow flag, EN/CLR PWE1 PWCON.1 PWM1 output to P2.7 pin enable

PWE0 PWCON.0 PWM0 output to P2.6 pin enable

Auxiliary Register Bit Definitions (AUXR =8EH)

RST AUXR.3 Software reset bit TXI AUXR.2 SIO TxD invert LO AUXR.1 Low Speed, reduces internal clock drive AO AUXR.0 ALE Off, when set turns off ALE

Interrupt Enable 0 (IE0) Register

EA IE0.7 Enable all interrupts EC IE0.6 Enable PCA interrupt ET2 IE0.5 Enable Timer 2 interrupt ES IE0.4 Enable Serial I/O interrupt ET1 IE0.3 Enable Timer 1 interrupt EX1 IE0.2 Enable External interrupt 1 ET0 IE0.1 Enable Timer 0 interrupt EX0 IE0.0 Enable External interrupt 0

Interrupt Enable 1 (IE1) Register

EOB IE1.7 Enable OBE interrupt EIB IE1.6 Enable IBF interrupt EAD IE1.5 Enable ADC interrupt EC4 IE1.4 Enable PCA module 4 interrupt EC3 IE1.3 Enable PCA module 3 interrupt EC2 IE1.2 Enable PCA module 2 interrupt EC1 IE1.1 Enable PCA module 1 interrupt EC0 IE1.0 Enable PCA module 0 interrupt

Interrupt Priority 0 (IP0) Register

PPC IP0.6 PCA interrupt priority PT2 IP0.5 Timer 2 interrupt priority PS IP0.4 Serial I/O interrupt priority PT1 IP0.3 Timer 1 interrupt priority PX1 IP0.2 External interrupt 1 priority PT0 IP0.1 Timer 0 interrupt priority PX0 IP0.0 External interrupt 0 priority

Interrupt Priority 1 (IP1) Register

POB IP1.7 OBE interrupt priority PIB IP1.6 IBF interrupt priority PAD IP1.5 ADC interrupt priority PC4 IP1.4 PCA module 4 interrupt priority PC3 IP1.3 PCA module 3 interrupt priority PC2 IP1.2 PCA module 2 interrupt priority PC1 IP1.1 PCA module 1 interrupt priority PC0 IP1.0 PCA module 0 interrupt priority

PWCON.2 Counter enable and counter/prescaler

IP0.7 (reserved)

must be cleared by software reset when Low

1998 Jun 04

Page 26

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

83C576/87C576

OSC

INTERNAL

BUS

1/2

PWMP

REG

8-BIT

PRESCALER

Figure 23. Block Diagram of PWMs

PCA Interrupt System

Priority Source Flag Vector

1 INT0 IE0 03H

highest priority

2 ADC ADF 3BH 3 TIMER 0 TF0 0BH 4 INT1 IE1 13H 5 TIMER 1 TF1 1BH 6 SERIAL RI,TI 23H 7 PCA0 CC0 43H 8 PCA1 CC1 4BH 9 PCA2 CC2 53H

10 PCA3 CC3 5BH

11 PCA4 CC4 63H 12 PCA ECF 33H 13 TIMER 2 TF2/EXF2 2BH 14 UPI IBF 6BH 15 UPI OBE 73H

lowest priority

Power Control (PCON) Register

SMOD1 PCON.7 double baud rate bit SMOD0 PCON.6 SCON.7 access control OSF PCON.5 oscillator fail flag POF PCON.4 power off flag LVF PCON.3 low voltage flag WDTOF PCON.2 watchdog timeout flag PD PCON.1 power down mode bit IDL PCON.0 idle mode bit

UNIVERSAL PERIPHERAL INTERF ACE

UPI mode allows the 8XC576 to function as a slave processor connected to a host CPU bus via port 0. The interface consists of port 0 input and output buffer registers and the UPI control/status register (UCS). UPI mode is enabled by setting the UPI enable bit (UE) in the UCS. When operating in UPI mode, port 0 pins should be programmed to High-Z (P0M1=1 and P0M2=0) by user firmware. Access to port 0 is controlled by inputs WR and WR are the external read and write strobes controlled by the host CPU. CS

is the chip select input, normally a decoded address

, RD, CS, and A0. RD

8-BIT

COUNTER

PWM0

PWM1

from the host CPU bus, which qualifies RD have no effect when CS

8-BIT

DETECT

8-BIT

DETECT

OUTPUT BUFFER

P2.6

P2.7

SU00256A

and WR (these pins

=1). The A0 pin is an address input from the host CPU which selects either the port 0 output buffer or the UCS register to be output during a read operation. During a write operation, the value of the A0 pin is latched in the AF flag in the UCS register. The following is a summary of the UPI data control inputs:

RD WR A0

0 0 1 0 read port 0 output buffer,

clear OBF/set OBE 0 0 1 1 read UPI control/ status register 0 1 0 0 write data to input buffer set IBF, clear AF 0 1 0 1 write command to input buffer set IBF, AF 1 x x x disable input/output

UPI Control Status Register (UCS, Reset value = 00H)

UCS.7 ST7 User defined status bit UCS.6 ST6 User defined status bit UCS.5 ST5 User defined status bit UCS.4 ST4 User defined status bit UCS.3 UE UPI Enable bit – if UE=1, UPI is enabled

(read only AF, IBF, and OBE/OBF), if UE=0, UPI is disabled and port 0 functions normally .

UCS.2 AF Address Flag – contains status of the A0

(address) pin during the last write. If A0=0, the input buffer should be interpreted as data by the 8XC576 software, if A0=1, the input buffer should be interpreted as a command.

USC.1 IBF Input Buffer Full flag – set by hardware on

trailing (rising) edge of WR

when CS=0, cleared by hardware when port 0 SFR is read (by the 8XC576 software).

USC.0 OBE/OBF Output Buffer Full flag – set by hardware

during writes (by 8XC576 software) to the port 0 SFR, set/cleared by hardware on the trailing (rising) edge of RD

when CS=0 and

A0=0.

NOTE: This bit is defined as OBE (1=empty) when read by the MCU, and, as OBF (—full) when read by the external host.

The IBF and OBF flag bits reflect the status of the input/output buffers. The host CPU writes to the 8XC576 by driving data on the external bus connected to port 0 and strobing the WR

=0. The WR strobe latches port 0 data in the input buffer and

CS sets the IBF flag on the trailing (rising) edge. When the 8XC576 reads from port 0 in UPI mode, it reads from the input buffer and

pin while

1998 Jun 04

Page 27

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

83C576/87C576

clears the IBF. When the 8XC576 writes to port 0 in UPI mode, it writes to the output buffer which sets the OBF and clears the OBE flag. The host CPU can read the output buffer or the UCS register enabling the port 0 drivers, the OBF flag is cleared and the OBE flag is set when the output buffer is read.

When the UPI is enabled, the AF, IBF, and OBE/OBF flags are read-only , and thus can only be modified by specific hardware events.

The UPI runs in idle mode. It can interrupt the part out of Idle mode for all UPI write and data read operations. It will not interrupt out of idle mode for a UCS register read operation.

OSCILLA T OR CHARACTERISTICS

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier . The pins can be configured for use as an on-chip oscillator, as shown in the Logic Symbol, page 4.

To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed.

IDLE MODE

In idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the

idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which starts the processor in the same manner as a power-on reset. Also see UPI section.

POWER-DOWN MODE

In the power-down mode, the oscillator is stopped and the instruction to invoke power-down is the last instruction executed. Only the contents of the on-chip RAM are preserved. The control bits for the reduced power modes are in the special function register PCON. Power-down mode can be terminated with either a hardware reset or external interrupt. With an external interrupt INT0 must be enabled and configured as level sensitive. Holding the pin low restarts to oscillator and bringing the pin back high completes the exit.

Power-down mode can be disabled by the DPD bit in the WDCON register. Reset and waking up from power-down will also enable the DPD bit, therefore, the DPD bit must be cleared again before the power-down mode.

or INT1

DESIGN CONSIDERATIONS

At power-on, the voltage on VCC must come up with RST low for a proper start-up.

Table 2 shows the state of I/O ports during low current operating modes.

Table 2. External Pin Status During Idle and Power-Down Modes

MODE PROGRAM MEMORY ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3

Idle Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power-down Internal 0 0 Data Data Data Data Power-down External 0 0 Float Data Data Data

1998 Jun 04

Page 28

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

ROM CODE SUBMISSION

When submitting ROM code for the 83C576, the following must be specified:

1. 8k byte user ROM data

2. 32 byte ROM encryption key

3. ROM security bits

4. The watchdog timer parameters. (See Watchdog Timer Specifications for definition of WDL and WDCON bits.)

83C576/87C576

ADDRESS

0000H to 1FFFH DATA 7:0 User ROM Data 2000H to 201FH KEY 7:0 ROM Encryption Key

2020H SEC

2030H WDCON

2031H WDL 7:0 Watchdog autoload value

Security Bit 1: When programmed, this bit has two effects on masked ROM parts:

1. External MOVC is disabled, and

2. EA is latched on Reset. Security Bit 2: When programmed, this bit inhibits Verify User ROM.

If the ROM code file does not include the options, the following information must be included with the ROM code. For each of the following, check the appropriate box and send to Philips along with the code:

Security Bit #1: Security Bit #2: Encryption: Watchdog/T imer Modes:

 Enabled  Disabled  Enabled  Disabled  No  Yes If Yes, must send key file.

CONTENT BIT(S) COMMENT

FFH = no encryption

0 ROM Security Bit 1

0 = enable security 1 = disable security

1 ROM Security Bit 2

0 = enable security 1 = disable security

7:5 PRE2:0

4 LVRE 3 OFRE 2 DPD 1 WDRUN = 0, not ROM coded 0 WDMOD

(see specification)

 Watchdog Mode  Timer Mode

Prescaler Value:

Autoload Value (range 0–255):

Low Voltage Reset (Value 0 or 1):

Oscillator Fail Reset (Value 0 or 1):

Power-Down (Value 0 or 1):

1998 Jun 04

(Value = 64, 128, 256, 512, 1024, 2048, 4096, 8192)

Value

Page 29

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

83C576/87C576

ABSOLUTE MAXIMUM RATINGS

Operating temperature under bias –55 to +125 °C Storage temperature range –65 to +150 °C Voltage on EA/VPP pin to V Voltage on any other pin to V Maximum IOL per I/O pin 15 mA Power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 W

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V noted.

1, 2, 3

PARAMETER

RATING UNIT

0 to +13.0 V

–0.5 to +6.5 V

unless otherwise

1998 Jun 04

Page 30

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

DC ELECTRICAL CHARACTERISTICS

= 0°C to +70°C, –40°C to +85°C, and –40°C to +125°C; VCC = 5V ±10%, VSS = 0V

amb

TEST LIMITS

SYMBOL PARAMETER CONDITIONS MIN TYP

IL1

IL2

IH1

HYS Hysteresis voltage (Port 1) 200 mV V

OL1

OH1

OH2

RST

LOW

NOTES:

1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V.

2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V . In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I single output sinks more than 5mA and no more than two outputs exceed the test conditions.

3. Capacitive loading on ports 0 and 2 may cause the V address bits are stabilizing.

4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when V

5. I

6. See Figures 34 through 37 for I

7. Load capacitance for port 0, ALE, and PSEN

8. Under steady state (non-transient) conditions, I

If I test conditions.

9. 20pF MAX for CERDIP package; 15pF MAX for all other packages.

Input low voltage (except Port 1, EA) –0.5 0.2VCC–0.1 V Input low voltage (EA) –0.5 0.2VCC–0.45 V Input low voltage (Port 1) –0.5 0.3V Input high voltage (except Port 1, XTAL1, RST) IIH < 2mA 0.2VCC+0.9 VCC+0.5 V Input high voltage (XTAL1, RST, Port 1) IIH < 2mA 0.7V

Output voltage low (Ports 1, 2, 3) IOL = 1.6mA 0.45 V Output voltage low (Ports 0, ALE, PSEN

)

IOL = 3.2mA 0.45 V Output voltage high (Ports 1, 2, 3 in push-pull mode) IOH = –1.6mA VCC–1.0 V Output voltage high (Port 0, ALE, PSEN) IOH = –3.2mA VCC–0.7 V Output voltage high in weak pullup mode (Port 0, 2, 3) IOH = –10µA VCC–1.0 V Offset voltage comparator inputs –35 +35 mV Common mode range comparator inputs 0 V Logical 0 input current (Ports 0, 2, 3) (weak pull-up) VIN = 0.45V –250 µA Input pulldown current (Port 0, Port2 in open drain mode) 0.45 < VIN < V Input leakage current (EA, P0. 2. 3 High-Z) 0.45 < VIN < V Input leakage current comparator/ADC inputs 0 < VIN < V Power supply current:

Active mode @ 16MHz

See note 6

CC CC

2 40 µA –10 +10 µA –1.0 +1.0 µA

Idle mode @ 16MHz Power-down mode

Internal reset pull-up resistor VIN = 0V 50 200 kΩ Low VCC detect voltage 3.75 4.25 V Pin capacitance

MAX at other frequencies can be determined from Figure 33.

Maximum I Maximum I Maximum total I

exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed

per port pin: 10mA

per 8-bit port: 26mA

is between VIH and VIL.

test conditions.

for all outputs: 71mA

f = 1MHz 15 pF

s of ALE and ports 1 and 3. The noise is due

can exceed these conditions provided that no

on ALE and PSEN to momentarily fall below the 0.9VCC specification when the

= 100pF, load capacitance for all other outputs = 80pF.

must be externally limited as follows:

83C576/87C576

8 5

MAX UNIT

VCC+0.5 V

30 12

mA mA

µA

1998 Jun 04

Page 31

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

A/D CONVERTER DC ELECTRICAL CHARACTERISTICS

= 0°C to +70°C, –40°C to +85°C, and –40°C to +125°C; VCC = 5V ±10%, VSS = 0V

amb

TEST LIMITS SYMBOL PARAMETER CONDITIONS MIN MAX UNIT Static Characteristics

R Resolution Monotonic with no missing codes 10 Bits IL DL FS OS

e e

Integral non-linearity error Differential non-linearity error Full Scale error Offset error

2, 8

2, 6, 8

Dynamic Characteristics

ADC

ADS

Conversion time (including sampling time) 48t Sampling tme 8t

Analog Input Characteristics

AV C M C

CTC

Analog input voltage AVSS – 0.2 AVDD + 0.2 V Analog input capacitance 15 pF Channel-to-channel matching Crosstalk between inputs of port 1

Power Requirements

AVCC/V AI

Analog supply and reference voltage AVCC = VCC ± 0.2 4.0 6.0 V

REF+

Analog supply current: operating: (16MHz) AVCC = 6.0V 1.2 mA

NOTES:

1. The following condition must not be exceeded: V

2. Conditions: AV

3. The differential non-linearity (DL

= 0V; AVCC = 4.997V; VCC = 5.0V.

4. The ADC is monotonic; there are no missing codes.

5. The integral non-linearity (IL appropriate adjustment of gain and offset error. (See Figure 24).

6. The offset error (OS a straight line which fits the ideal transfer curve. (See Figure 24).

) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and

7. Guaranteed by design.

8. To meet Error Specification, analog input voltage must be less than 1V/ms.

(AV

ń1023) 1000

Slew Rate

MAX

4 (12ńOsc Freq (MHz))

For 16MHz @ 5.0V slew rate = 1.6V/ms.

2, 5, 8

2, 3, 4, 7, 8

– 0.2V < AVDD < VDD + 0.2V.

) is the difference between the actual step width and the ideal step width. (See Figure 24).

0–100kHz –60 dB

(Vńms)

83C576/87C576

±2 LSB ±1 LSB ±3 LSB ±2 LSB

±1 LSB

µs µs

1998 Jun 04

Page 32

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

83C576/87C576

Code

Out

1023

1022

1021

1020

1019

1018

Offset

error OS

Full Scale

(2)

(5)

(4)

(1)

error

Gain error

1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024

Offset

error OS

(1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential non-linearity (DL (4) Integral non-linearity (IL (5) Center of a step of the actual transfer curve.

(3)

1 LSB (ideal)

1 LSB =

Figure 24. ADC Conversion Characteristic

AVIN (LSB

REF+

1024

– AV

ideal

REF–

)

SU00710

1998 Jun 04

Page 33

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

83C576/87C576

AC ELECTRICAL CHARACTERISTICS

= 0°C to +70°C, –40°C to +85°C, and –40°C to +125°C; VCC = 5V ±10%, VSS = 0V

amb

SYMBOL FIGURE PARAMETER MIN MAX UNIT

1/t

CLCL

25 Oscillator frequency: Speed Version

8XC576 E 6 16 MHz OSCF Oscillator fail detect frequency 0.6 5.5 MHz TR Comparator response time 10 µs t

LHLL

AVLL

LLAX

LLIV

LLPL

PLPH

PLIV

PXIX

PXIZ

AVIV

PLAZ

25 ALE pulse width 2t 25 Address valid to ALE low t 25 Address hold after ALE low t 25 ALE low to valid instruction in 4t 25 ALE low to PSEN low t 25 PSEN pulse width 3t 25 PSEN low to valid instruction in 3t 25 Input instruction hold after PSEN 0 ns 25 Input instruction float after PSEN t 25 Address to valid instruction in 5t 25 PSEN low to address float 10 ns

Data Memory

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

AVDV

LLWL

AVWL

QVWX

WHQX

RLAZ

WHLH

26, 27 RD pulse width 6t 26, 27 WR pulse width 6t 26, 27 RD low to valid data in 5t 26, 27 Data hold after RD 0 ns 26, 27 Data float after RD 2t 26, 27 ALE low to valid data in 8t 26, 27 Address to valid data in 9t 26, 27 ALE low to RD or WR low 3t 26, 27 Address valid to WR low or RD low 4t 26, 27 Data valid to WR transition t 26, 27 Data hold after WR t 26, 27 RD low to address float 0 ns 26, 27 RD or WR high to ALE high t

External Clock

CHCX

CLCX

CLCH

CHCL

29 High time 20 ns 29 Low time 20 ns 29 Rise time 20 ns 29 Fall time 20 ns

Shift Register

XLXL

QVXH

XHQX

XHDX

XHDV

28 Serial port clock cycle time 12t 28 Output data setup to clock rising edge 10t 28 Output data hold after clock rising edge 2t 28 Input data hold after clock rising edge 0 ns 28 Clock rising edge to input data valid 10t

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN

= 100pF, load capacitance for all other outputs = 80pF.

3. Interfacing the 83C576/87C576 to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers.

1, 2

VARIABLE CLOCK

–40 ns

CLCL

–40 ns

CLCL

–30 ns

CLCL

–100 ns

CLCL

–30 ns

CLCL

–45 ns

CLCL

–105 ns

CLCL

–25 ns

CLCL

–105 ns

CLCL

–100 ns

CLCL

–100 ns

CLCL

–165 ns

CLCL

–60 ns

CLCL

–150 ns

CLCL

–165 ns

CLCL

–50 3t

CLCL

–130 ns

CLCL

–50 ns

CLCL

–50 ns

CLCL

–40 t

CLCL

–133 ns

CLCL

–60 ns

CLCL

+50 ns

CLCL

+40 ns

CLCL

–133 ns

CLCL

1998 Jun 04

Page 34

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

UPI AC ELECTRICAL CHARACTERISTICS

= 0°C to +70°C, –40°C to +85°C, and –40°C to +125°C; VCC = 5V ±10%, VSS = 0V

amb

SYMBOL

CS, A setup to RD 0 ns CS, A hold after RD 35 ns RD pulse width 35 ns CS, A to data out delay 45 ns RD to data out delay 35 ns RD to data float delay (guaranteed by design) 30 ns CS, A setup to WR 0 ns CS, A hold after WR 15 ns WR pulse width 45 ns Data setup to WR 5 ns Data hold after WR 25 ns

PARAMETER MIN MAX UNIT

83C576/87C576

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A – Address C – Clock D – Input data H – Logic level high I – Instruction (program memory contents) L – Logic level low, or ALE

ALE

PSEN

PORT 0

LHLL

AVLL

LLPL

LLAX

A0–A7 A0–A7

AVIV

LLIV

PLIV

PLPH

PLAZ

PXIX

INSTR IN

P – PSEN Q – Output data

signal

R–RD t – Time V – Valid W– WR

signal X – No longer a valid logic level Z – Float Examples: t

PXIZ

= Time for address valid to ALE low.

AVLL

=Time for ALE low to PSEN low.

LLPL

1998 Jun 04

PORT 2

A0–A15 A8–A15

SU00006

Figure 25. External Program Memory Read Cycle

Page 35

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

ALE

PSEN

LLDV

PORT 0

PORT 2

AVLL

LLAX

A0–A7

FROM RI OR DPL

AVWL

LLWL

RLAZ

AVDV

P2.0–P2.7 OR A8–A15 FROM DPF A0–A15 FROM PCH

RLDV

RLRH

WHLH

RHDZ

RHDX

DATA IN A0–A7 FROM PCL INSTR IN

83C576/87C576

ALE

PSEN

PORT 0

PORT 2

AVLL

LLAX

A0–A7

FROM RI OR DPL

AVWL

Figure 26. External Data Memory Read Cycle

WHLH

LLWL

QVWX

P2.0–P2.7 OR A8–A15 FROM DPF A0–A15 FROM PCH

WLWH

WHQX

DATA OUT A0–A7 FROM PCL INSTR IN

Figure 27. External Data Memory Write Cycle

SU00025

SU00069

1998 Jun 04

Page 36

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

83C576/87C576

INSTRUCTION

ALE

CLOCK

OUTPUT DATA

WRITE TO SBUF

INPUT DATA

CLEAR RI

012345678

XLXL

QVXH

XHDV

VALID VALID VALID VALID VALID VALID VALID VALID

XHQX

1230 4567

XHDX

SET TI

SET RI

SU00027

Figure 28. Shift Register Mode Timing

VCC–0.5

0.45V

0.7V

0.2VCC–0.1

CHCL

CLCX

CLCL

CHCX

CLCH

SU00009

Figure 29. External Clock Drive

VCC–0.5

0.45V

NOTE: AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.

0.2V

+0.9

–0.1

SU00010

Figure 30. AC Testing Input/Output

+0.1V

LOAD

–0.1V

NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded V

TIMING

REFERENCE

POINTS

OH/VOL

–0.1V

+0.1V

level occurs. IOH/IOL ≥ ±20mA.

SU00011

Figure 31. Float Waveform

1998 Jun 04

Page 37

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

AO, CS

D0–D7

Figure 32. UPI Read/Write Cycles

t t

RR WW

t t

DF WD

t t

RA WA

SU00518

83C576/87C576

(mA)

045 10 151620

FREQUENCY (MHz)

MAX ACTIVE

TYP ACTIVE

MAX IDLE

TYP IDLE

SU00245

Figure 33. ICC vs. FREQ

Valid only within frequency specifications of the device under test

1998 Jun 04

(NC)

CLOCK SIGNAL

RST

XTAL2

XTAL1

SU00661

Figure 34. ICC Test Condition, Active Mode

All other pins are disconnected

Page 38

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

RST

83C576/87C576

(NC)

CLOCK SIGNAL

XTAL2

XTAL1

SU00662

Figure 35. ICC Test Condition, Idle Mode

All other pins are disconnected

VCC–0.5

0.45V

0.7V

0.2VCC–0.1

CHCL

CLCX

CLCL

CHCX

CLCH

SU00009

Figure 36. Clock Signal Waveform for ICC Tests in Active and Idle Modes

(NC)

= t

CLCH

RST

XTAL2

XTAL1

CHCL

= 5ns

1998 Jun 04

SU00663A

Figure 37. ICC Test Condition, Power Down Mode

All other pins are disconnected. V

= 2V to 5.5V

Page 39

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

83C576/87C576

EPROM CHARACTERISTICS

To put the 87C576 in the parallel EPROM programming mode, PSEN must be held high during power up, then driven low with reset active. The 87C576 is programmed by using a modified Quick-Pulse Programming algorithm.

The 87C576 contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an 87C576 manufactured by Philips.

Table 3 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 38 and 39. Figure 40 shows the circuit configuration for normal program memory verification.

On-Board Programming (OBP)

The On-Board Programming facility consists of a series of internal hardware resources coupled with internal firmware to facilitate remote programming of the 87C576 through the serial port.

The OBP function is invoked by having the EA voltage level at the time that the part exits reset. The OBP function only requires that the TxD, RxD, V connected to an external circuit in order to use this feature.

The OBP feature provides for the use of a wide range of baud rates independent of the oscillator frequency used. It is also adaptable to a wide range of oscillator frequencies. The OBP facility provides for both auto-echo and no-echo of received characters. The OBP feature requires that an initial character, an uppercase U, be sent to the 87C576 to establish the baud rate to be used.

Once baud rate initialization has been performed, the OBP facility only accepts Intel Hex records. The record-type field of these hex records are used to indicate either commands or data for the OBP facility. The maximum number of data bytes in a record is limited to 16 (decimal). These commands/data are summarized below:

Record Type

00 Data record, programs the part with data indicated in

01 EOF record, no operation 02 Specify timing parameters

03 Program security bits

04 Display contents of USER EPROM array

05 Verify security bit status

Command/Data Function

record starting with load address in the record

– rec length = 3 bytes – load address = 0000 – 1st byte = timer count for 50µs programming pulse – 2nd byte = timer count for 10µs delay between pulses – 3rd byte = 0AH

– rec length = 1 byte – load address = 0000 – 1st byte = sec bit values (xxxx xxB2B1)

– rec length = 00 – load address = 0000

, VCC, and VPP pins be

/VPP pin at the V

Quick-Pulse Programming (Parallel)

The setup for microcontroller quick-pulse programming is shown in Figure 38. Note that the 87C576 is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers.

The address of the EPROM location to be programmed is applied to ports 3 and 2, as shown in Figure 38. The code byte to be programmed into that location is applied to port 0. RST, PSEN pins of ports 2 and 1 specified in Table 3 are held at the ‘Program Code Data’ levels indicated in Table 3. The ALE/PROG low 25 times as shown in Figure 39.

To program the encryption table, repeat the 25 pulse programming sequence for addresses 0 through 1FH, using the ‘Pgm Encryption Table’ levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data.

To program the security bits, repeat the 25 pulse programming sequence using the ‘Pgm Security Bit’ levels. After one security bit is programmed, further programming of the code memory and encryption table is disabled. However, the other security bit can still be programmed.

Note that the EA maximum specified V glitch above that voltage can cause permanent damage to the device. The V and overshoot.

/VPP pin must not be allowed to go above the

level for any amount of time. Even a narrow

source should be well regulated and free of glitches

and

is pulsed

Program V erification

If security bit 2 has not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory locations to be read is applied to ports 3 and 2 as shown in Figure 40. The other pins are held at the ‘Verify Code Data’ levels indicated in Table 3. The contents of the address location will be emitted on port 0. External pull-ups are required on port 0 for this operation.

If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out.

Reading the Signature Bytes

The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P1.0 and P1.1 need to be pulled to a logic low. The values are: (030H) = 15H indicates manufactured by Philips (B6H) = B6H indicates 87C576

Program/Verify Algorithms

Any algorithm in agreement with the conditions listed in Table 3, and which satisfies the timing specifications, is suitable.

Trademark phrase of Intel Corporation.

1998 Jun 04

Page 40

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

Table 3. EPROM Programming Modes

MODE RST PSEN ALE/PROG EA/V

Read signature 0 0 1 1 0 0 0 0 Program code data 0 0 0* V Verify code data 0 0 1 1 0 0 1 1 Pgm encryption table 0 0 0* V Pgm security bit 1 0 0 0* V Pgm security bit 2 0 0 0* V

NOTES:

1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin. = 12.75V ±0.25V.

2. V

= 5V±10% during programming and verification.

3. V

* ALE/PROG

minimum of 10µs.

receives 5 programming pulses while VPP is held at 12.75V . Each programming pulse is low for 50µs (±10µs) and high for a

PP PP PP

P2.7 P2.6 P1.1 P1.0

1 0 1 1

1 0 1 0 1 1 1 1 1 1 0 0

83C576/87C576

1998 Jun 04

Page 41

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

83C576/87C576

ALE/PROG:

1 0

4–6MHz

+5V

PGM DATA

+12.75V 5 50µs PULSES TO GROUND 0

A8–A12

SU00257B

A0–A7

+5V

0 1 1

RST P1.0

P1.1 XTAL2

XTAL1 AV

87C576

ALE/PROG

PSEN

P2.7

P2.6

P2.0–P2.4

Figure 38. Programming Configuration

5 PULSES

1 0

50µs+1010µs MIN

4–6MHz

A0–A7

SU00664

Figure 39. PROG Waveform

+5V

0 1 1

RST P1.0

P1.1 XTAL2

XTAL1 AV

87C576

ALE/PROG

PSEN

P2.0–P2.4

P2.7

P2.6

+5V

PGM DATA

1 1 0 0 ENABLE

A8–A12

SU00258B

Figure 40. Program Verification

1998 Jun 04

Page 42

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS

= 21°C to +27°C, VCC = 5V±10%, VSS = 0V (See Figure 41)

amb

SYMBOL

1/t

CLCL

AVGL

GHAX

DVGL

GHDX

EHSH

SHGL

GHSL

GLGH

AVQV

ELQZ

EHQZ

GHGL

Programming supply voltage 12.5 13.0 V Programming supply current 50 mA Oscillator frequency 4 12 MHz Address setup to PROG low 48t Address hold after PROG 48t Data setup to PROG low 48t Data hold after PROG 48t P2.7 (ENABLE) high to V VPP setup to PROG low 10 µs VPP hold after PROG 10 µs PROG width 40 60 µs Address to data valid 48t ENABLE low to data valid 48t Data float after ENABLE 0 48t PROG high to PROG low 10 µs

PARAMETER MIN MAX UNIT

48t

CLCL CLCL CLCL CLCL CLCL

83C576/87C576

CLCL CLCL CLCL

PROGRAMMING* VERIFICATION*

P3.0–P3.7 P2.0–P2.4

PORT 0

DVGL

ALE/PROG

EA/V

P2.7 ENABLE

* FOR PROGRAMMING VERIFICATION SEE FIGURE 38.

FOR VERIFICATION CONDITIONS SEE FIGURE 40.

EHSH

SHGL

AVGL

GLGH

ADDRESS ADDRESS

AVQV

DATA IN DATA OUT

GHAX

GHGL

GHSL

LOGIC 0

GHDX

LOGIC 1 LOGIC 1

ELQV

Figure 41. EPROM Programming and Verification

EHQZ

SU00207

1998 Jun 04

Page 43

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1

83C576/87C576

1998 Jun 04

Page 44

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

PLCC44: plastic leaded chip carrier; 44 leads SOT187-2

83C576/87C576

1998 Jun 04

Page 45

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2

83C576/87C576

1998 Jun 04

Page 46

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

8K/256 OTP/ROM, 6 channel 10-bit A/D, 4 comparators, failure detect circuitry, watchdog timer

Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

[1]

83C576/87C576

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1998

Date of release: 06-98

Document order number: 9397 750 04024

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1998 Jun 04