Datasheet 80c552, 83c552 DATASHEETS

INTEGRATED CIRCUITS

80C552/83C552

Single-chip 8-bit microcontroller

Product specification
Supersedes data of 1998 Jan 06
IC20 Data Handbook

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1998 Aug 13

Philips Semiconductors Product specification

Single-chip 8-bit microcontroller

80C552/83C552

Single-chip 8-bit microcontroller with 10-bit A/D, capture/compare timer, high-speed outputs, PWM

2

• I

C-bus serial I/O port with byte oriented

master and slave functions

• Full-duplex UART compatible with the

standard 80C51

• On-chip watchdog timer

• Three speed ranges:

– 3.5 to 16MHz
– 3.5 to 24MHz (ROM, ROMless only)
– 3.5 to 30MHz (ROM, ROMless only)

• Three operating ambient temperature

ranges:

– P83C552xBx: 0°C to +70°C
– P83C552xFx: –40°C to +85°C

(XTAL frequency max. 24 MHz)

– P83C552xHx: –40°C to +125°C

(XTAL frequency max. 16 MHz)

DESCRIPTION

The 80C552/83C552 (hereafter generically
referred to as 8XC552) Single-Chip 8-Bit
Microcontroller is manufactured in an
advanced CMOS process and is a derivative
of the 80C51 microcontroller family. The
8XC552 has the same instruction set as the
80C51. Three versions of the derivative exist:

• 83C552—8k bytes mask programmable

ROM

• 80C552—ROMless version of the 83C552

FEATURES

• 80C51 central processing unit

• 8k × 8 ROM expandable externally to 64k

bytes

• ROM code protection

• An additional 16-bit timer/counter coupled

to four capture registers and three compare
registers

• Two standard 16-bit timer/counters

• 256 × 8 RAM, expandable externally to 64k

bytes

• Capable of producing eight synchronized,

timed outputs

• A 10-bit ADC with eight multiplexed analog

inputs

• Two 8-bit resolution, pulse width

modulation outputs

• Five 8-bit I/O ports plus one 8-bit input port

shared with analog inputs

• 87C552—8k bytes EPROM (described in a

separate chapter)

The 8XC552 contains a non-volatile 8k × 8
read-only program memory (83C552), a
volatile 256 × 8 read/write data memory, five
8-bit I/O ports, one 8-bit input port, two 16-bit
timer/event counters (identical to the timers of
the 80C51), an additional 16-bit timer coupled
to capture and compare latches, a 15-source,
two-priority-level, nested interrupt structure,
an 8-input ADC, a dual DAC pulse width
modulated interface, two serial interfaces
(UART and I

2

C-bus), a “watchdog” timer and
on-chip oscillator and timing circuits. For
systems that require extra capability, the
8XC552 can be expanded using standard
TTL compatible memories and logic.

In addition, the 8XC552 has two software
selectable modes of power reduction—idle
mode and power-down mode. The idle mode
freezes the CPU while allowing the RAM,
timers, serial ports, and interrupt system to
continue functioning. The power-down mode
saves the RAM contents but freezes the
oscillator, causing all other chip functions to
be inoperative.

The device also functions as an arithmetic
processor having facilities for both binary and
BCD arithmetic plus bit-handling capabilities.
The instruction set consists of over 100
instructions: 49 one-byte, 45 two-byte, and
17 three-byte. With a 16MHz (24MHz)
crystal, 58% of the instructions are executed
in 0.75µs (0.5µs) and 40% in 1.5µs (1µs).
Multiply and divide instructions require 3µs
(2µs).

LOGIC SYMBOL

ADC0-7

CMSR0-5

CMT0
CMT1

V

SS

V

DD

XTAL1
XTAL2

EA

ALE

PSEN

AV

SS

AV

DD

AVref+
AVref–

STADC

PWM0
PWM1

RST

EW

LOW ORDER

ADDRESS AND

PORT 0

CT0I
CT1I

CT2I
CT3I
T2

PORT 1PORT 2PORT 3

RT2
SCL
SDA

PORT 5

PORT 4

ADDRESS AND

RxD/DATA

TxD/CLOCK

INT0
INT1

T0
T1
WR
RD

DATA BUS

HIGH ORDER

DATA BUS

1998 Aug 13

2

Philips Semiconductors Product specification

Single-chip 8-bit microcontroller

PIN CONFIGURATIONS
Plastic Leaded Chip Carrier

P4.2/CMSR2

P4.1/CMSR1

P4.0/CMSR0

765432168 6798 66 65 64 63 62

RST

P1.4/T2

10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

27

P3.4/T0

P3.5/T1

P3.3/INT1

P4.3/CMSR3
P4.4/CMSR4
P4.5/CMSR5

P4.6/CMT0
P4.7/CMT1

P1.0/CT0I
P1.1/CT1I
P1.2/CT2I
P1.3/CT3I

P1.5/RT2

P1.6/SCL

P1.7/SDA

P3.0/RxD

P3.1/TxD

P3.2/INT0

DD

EW

PWM1

PWM0

STADC

V

P5.0/ADC0

P5.1/ADC1

P5.2/ADC2

PLASTIC LEADED CHIP CARRIER

XTAL1

37 3828 29

SS

V

V

30 31 32 33 34 35 36

NC*

NC*

P3.7/RD

P3.6/WR

XTAL2

P5.4/ADC4

P5.3/ADC3

39 40 41 42 43

SS

NC*

P2.0/A08

P5.5/ADC5

P5.6/ADC6

P2.1/A09

P2.2/A10

DD

AV

P5.7/ADC7

61

60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

44

P2.3/A11

P2.4/A12

80C552/83C552

AV

SS

AV

REF+

AV

REF–

P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7

EA
ALE

PSEN

P2.7/A15
P2.6/A14
P2.5/A13

SU00932

* Do not connect.

1998 Aug 13

3

Philips Semiconductors Product specification

Single-chip 8-bit microcontroller

Plastic Quad Flat Pack

P4.0/SMSR0

NC*

NC*

78 77 76 75 74 73 72 71 7080 79 69 68 67 66 65

NC*

RST

P1.4/T2

NC*
NC*

1
2
3
4
5
6
7
8

9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24

27 28 29 30 31 32 33

P3.5/T1

P3.7/RD

P3.6/WR

P4.1/CMSR1
P4.2/CMSR2

P4.3/CMSR3
P4.4/CMSR4
P4.5/CMSR5

P4.6/CMT0
P4.7/CMT1

P1.0/CT0I
P1.1/CT1I
P1.2/CT2I

P1.3/CT3I

P1.5/RT2
P1.6/SCL

P1.7/SDA

P3.0/RxD
P3.1/TxD

P3.2/INT0

P3.3/INT1

PP3.4/T0

* Do not connect.
IC = Internally connected (do not use).

EW

PWM1

PWM0

STADC

DD

V

IC

P5.0/ADC0

PLASTIC QUAD FLAT PACK

34 3525 26

IC

NC*

NC*

NC*

XTAL2

V

XTAL1

P5.1/ADC1

P5.2/ADC2

36 37 38 39 40

SSVSSVSS

P5.3/ADC3

P5.4/ADC4

NC*

P2.0/A08

P5.5/ADC5

P5.6/ADC6

64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41

P2.1/A09

P2.2/A10

80C552/83C552

P5.7/ADC7
AV

DD

NC*
AV

SS

AV

REF+

AV

REF–

P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5

P0.6/AD6

P0.7/AD7

EA
ALE
PSEN
P2.7/A15
P2.6/A14
P2.5/A13
NC*
NC*
P2.4/A12
P2.3/A11

SU00931

1998 Aug 13

4

Philips Semiconductors Product specification

Single-chip 8-bit microcontroller

BLOCK DIAGRAM

T0 T1 INT0 INT1

3 3 3 3

XTAL1

T0, T1

XTAL2

EA

ALE

PSEN

3

3

0

2

WR

RD

AD0-7

A8-15

TWO 16-BIT

TIMER/EVENT

COUNTERS

PARALLEL I/O

PORTS AND

EXTERNAL BUS

80C51 CORE

EXCLUDING

ROM/RAM

CPU

SERIAL

UART
PORT

V

DD

PROGRAM

MEMORY

8k x 8 ROM

8-BIT

PORT

V

8-BIT INTERNAL BUS

16

FOUR
16-BIT

CAPTURE

LATCHES

SS

DATA

MEMORY

256 x 8 RAM

16-BIT
TIMER/
EVENT

COUNTERS

80C552/83C552

PWM0 PWM1

DUAL
PWM

T2

16

COMPARA-

REGISTERS

T2

16-BIT

TORS
wITH

AV

SS

AV

DD

COMPARA-

OUTPUT

SELECTION

AV

REF

–+

ADC

TOR

STADC

ADC0-7 SDA SCL

SERIAL

2

C PORT

I

T3

WATCHDOG

TIMER

115

P0 P1 P2 P3 TxD RxD P5 P4 CT0I-CT3I T2 RT2 CMSR0-CMSR5

0

ALTERNATE FUNCTION OF PORT 0

1

ALTERNATE FUNCTION OF PORT 1

2

ALTERNATE FUNCTION OF PORT 2

3 3

3

ALTERNATE FUNCTION OF PORT 3

4

ALTERNATE FUNCTION OF PORT 4

5

ALTERNATE FUNCTION OF PORT 5

1 1 1 4

CMT0, CMT1

RST EW

1998 Aug 13

5

Philips Semiconductors Product specification

()

Single-chip 8-bit microcontroller

ORDERING INFORMATION

PHILIPS

PART ORDER NUMBER

PART MARKING

ROMless ROM

P80C552EBA P83C552EBA/xxx S80C552-4A68 S83C552-4A68 S87C552-4A68 SOT188-2

P80C552EBB P83C552EBB/xxx S80C552-4B S83C552-4B S87C552-4BA SOT318-2

P80C552EFA P83C552EFA/xxx S80C552-5A68 S83C552-5A68 S87C552-5A68 SOT188-2

P80C552EFB P83C552EFB/xxx S80C552-5B S83C552-5B SOT318-2

P80C552EHA P83C552EHA/xxx S80C552-6A68 S83C552-6A68 SOT188-2

P80C552EHB P83C552EHB/xxx S80C552-6B S83C552-6B SOT318-2

P80C552IBA P83C552IBA/xxx S80C552-AA68 S83C552-AA68 SOT188-2

P80C552IBB P83C552IBB/xxx S80C552-AB S83C552-AB SOT318-2

P80C552IFA P83C552IFA/xxx S80C552-BA68 S83C552-BA68 SOT188-2

P80C552IFB P83C552IFB/xxx S80C552-BB S83C552-BB SOT318-2

P80C552KBA P83C552KBA/xxx S80C552-CA68 S83C552-CA68 SOT188-2

P80C552KBB P83C552KBB/xxx S80C552-CB S83C552-CB SOT318-2

NOTE:

1. xxx denotes the ROM code number.

2. For EPROM device specification, refer to

1

NORTH AMERICA PHILIPS

PART ORDER NUMBER

ROMless ROM EPROM

87C552

datasheet.

DRAWING

NUMBER

2

80C552/83C552

TEMPERATURE (°C)

AND PACKAGE

0 to +70,

Plastic Leaded Chip Carrier

0 to +70,

Plastic Quad Flat Pack

–40 to +85,

Plastic Leaded Chip Carrier

–40 to +85,

Plastic Quad Flat Pack

–40 to +125,

Plastic Leaded Chip Carrier

–40 to +125,

Plastic Quad Flat Pack

0 to +70,

Plastic Leaded Chip Carrier

0 to +70,

Plastic Quad Flat Pack

–40 to +85,

Plastic Leaded Chip Carrier

–40 to +85,

Plastic Quad Flat Pack

0 to +70,

Plastic Leaded Chip Carrier

0 to +70,

Plastic Quad Flat Pack

FREQ
(MHz)

16

16

16

16

16

16

24

24

24

24

30

30

1998 Aug 13

6

Philips Semiconductors Product specification

Single-chip 8-bit microcontroller

80C552/83C552

PIN DESCRIPTION

PIN NO.

MNEMONIC PLCC QFP TYPE NAME AND FUNCTION

V

DD

STADC 3 74 I Start ADC Operation: Input starting analog to digital conversion (ADC operation can also

PWM0 4 75 O Pulse Width Modulation: Output 0.
PWM1 5 76 O Pulse Width Modulation: Output 1.
EW 6 77 I Enable Watchdog Timer: Enable for T3 watchdog timer and disable power-down mode.

P0.0-P0.7 57-50 58-51 I/O Port 0: Port 0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written

P1.0-P1.7 16-23 10-17 I/O Port 1: 8-bit I/O port. Alternate functions include:

P2.0-P2.7 39-46 38-42,

P3.0-P3.7 24-31 18-20,

P4.0-P4.7 7-14 80, 1-2

P5.0-P5.7 68-62, 71-64, I Port 5: 8-bit input port.

RST 15 9 I/O Reset: Input to reset the 8XC552. It also provides a reset pulse as output when timer T3

XTAL1 35 32 I Crystal Input 1: Input to the inverting amplifier that forms the oscillator, and input to the

XTAL2 34 31 O Crystal Input 2: Output of the inverting amplifier that forms the oscillator. Left open-circuit

2 72 I Digital Power Supply: +5V power supply pin during normal operation, idle and

16-21 10-15 I/O (P1.0-P1.5): Quasi-bidirectional port pins.
22-23 16-17 I/O (P1.6, P1.7): Open drain port pins.
16-19 10-13 I CT0I-CT3I (P1.0-P1.3): Capture timer input signals for timer T2.

20 14 I T2 (P1.4): T2 event input.
21 15 I RT2 (P1.5): T2 timer reset signal. Rising edge triggered.
22 16 I/O SCL (P1.6): Serial port clock line I2C-bus.
23 17 I/O SDA (P1.7): Serial port data line I2C-bus.

45-47

23-27
24 18 RxD(P3.0): Serial input port.
25 19 TxD (P3.1): Serial output port.
26 20 INT0 (P3.2): External interrupt.
27 23 INT1 (P3.3): External interrupt.
28 24 T0 (P3.4): Timer 0 external input.
29 25 T1 (P3.5): Timer 1 external input.
30 26 WR (P3.6): External data memory write strobe.
31 27 RD (P3.7): External data memory read strobe.

4-8

7-12 80, 1-2

4-6

13, 14 7, 8 O CMT0, CMT1 (P4.6, P4.7): Timer T2 compare and toggle outputs on a match with timer T2.

1 ADC0-ADC7 (P5.0-P5.7): Alternate function: Eight input channels to ADC.

power-down mode.

be started by software). This pin must not float.

This pin must not float.

to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed
low-order address and data bus during accesses to external program and data memory. In
this application it uses strong internal pull-ups when emitting 1s.

Port 1 is also used to input the lower order address byte during EPROM programming and
verification. A0 is on P1.0, etc.

I/O Port 2: 8-bit quasi-bidirectional I/O port.

Alternate function: High-order address byte for external memory (A08-A15).

I/O Port 3: 8-bit quasi-bidirectional I/O port. Alternate functions include:

I/O Port 4: 8-bit quasi-bidirectional I/O port. Alternate functions include:

O CMSR0-CMSR5 (P4.0-P4.5): Timer T2 compare and set/reset outputs on a match with

timer T2.

overflows.

internal clock generator. Receives the external clock signal when an external oscillator is
used.

when an external clock is used.

1998 Aug 13

7

Philips Semiconductors Product specification

Single-chip 8-bit microcontroller

80C552/83C552

PIN DESCRIPTION (Continued)

PIN NO.

MNEMONIC PLCC QFP TYPE NAME AND FUNCTION

V

SS

PSEN 47 48 O Program Store Enable: Active-low read strobe to external program memory.
ALE 48 49 O Address Latch Enable: Latches the low byte of the address during accesses to external

EA 49 50 I External Access: When EA is held at TTL level high, the CPU executes out of the internal

AV

REF–

AV

REF+

AV

SS

AV

DD

NOTE:

1. To avoid “latch-up” effect at power-on, the voltage on any pin at any time must not be higher or lower than V
respectively.

36, 37 34-36 I Two Digital ground pins.

memory. It is activated every six oscillator periods. During an external data memory
access, one ALE pulse is skipped. ALE can drive up to eight LS TTL inputs and handles
CMOS inputs without an external pull-up.

program ROM provided the program counter is less than 8192. When EA

low level, the CPU executes out of external program memory. EA is not allowed to float.
58 59 I Analog to Digital Conversion Reference Resistor: Low-end.
59 60 I Analog to Digital Conversion Reference Resistor: High-end.
60 61 I Analog Ground
61 63 I Analog Power Supply

is held at TTL

+ 0.5V or VSS – 0.5V,

DD

OSCILLATOR
CHARACTERISTICS

XTAL1 and XTAL2 are the input and output,
respectively, of an inverting amplifier. The
pins can be configured for use as an on-chip
oscillator, as shown in the logic symbol,
page 2.

To drive the device from an external clock
source, XTAL1 should be driven while XTAL2
is left unconnected. There are no
requirements on the duty cycle of the
external clock signal, because the input to
the internal clock circuitry is through a
divide-by-two flip-flop. However, minimum
and maximum high and low times specified in
the data sheet must be observed.

RESET

A reset is accomplished by holding the RST
pin high for at least two machine cycles (24
oscillator periods), while the oscillator is
running. To insure a good power-on reset, the
RST pin must be high long enough to allow
the oscillator time to start up (normally a few
milliseconds) plus two machine cycles. At
power-on, the voltage on V
come up at the same time for a proper
start-up.

and RST must

DD

IDLE MODE

In the idle mode, the CPU puts itself to sleep
while some of the on-chip peripherals stay
active. The instruction to invoke the idle
mode is the last instruction executed in the
normal operating mode before the idle mode
is activated. The CPU contents, the on-chip
RAM, and all of the special function registers
remain intact during this mode. The idle
mode can be terminated either by any
enabled interrupt (at which time the process
is picked up at the interrupt service routine
and continued), or by a hardware reset which
starts the processor in the same manner as a
power-on reset.

POWER-DOWN MODE

In the power-down mode, the oscillator is
stopped and the instruction to invoke
power-down is the last instruction executed.
Only the contents of the on-chip RAM are
preserved. A hardware reset is the only way
to terminate the power-down mode. The
control bits for the reduced power modes are
in the special function register PCON. Table 1
shows the state of the I/O ports during low
current operating modes.

ROM CODE PROTECTION
(83C552)

The 83C552 has an additional security
feature. ROM code protection may be
selected by setting a mask–programmable
security bit (i.e., user dependent). This
feature may be requested during ROM code
submission. When selected, the ROM code
is protected and cannot be read out at any
time by any test mode or by any instruction in
the external program memory space.

The MOVC instructions are the only
instructions that have access to program
code in the internal or external program
memory. The EA
RESET and is “don’t care” after RESET
(also if the security bit is not set). This
implementation prevents reading internal
program code by switching from external
program memory to internal program memory
during a MOVC instruction or any other
instruction that uses immediate data.

input is latched during

Table 1. External Pin Status During Idle and Power-Down Modes

MODE

Idle Internal 1 1 Data Data Data Data Data 1
Idle External 1 1 Float Data Address Data Data 1
Power-down Internal 0 0 Data Data Data Data Data 1
Power-down External 0 0 Float Data Data Data Data 1

1998 Aug 13

PROGRAM

MEMORY

ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 PORT 4

8

PWM0/

PWM1

Philips Semiconductors Product specification

Single-chip 8-bit microcontroller

80C552/83C552

Serial Control Register (S1CON) – See Table 2

S1CON (D8H)

Bits CR0, CR1 and CR2 determine the serial clock frequency that is generated in the master mode of operation.

CR2 ENS1 STA STO SI AA CR1 CR0

Table 2. Serial Clock Rates

BIT FREQUENCY (kHz) AT f

CR2 CR1 CR0 6MHz 12MHz 16MHz 24MHz

0 0 0 23 47 62.5 94 117 1 256
0 0 1 27 54 71 107
0 1 0 31 63 83.3 125
0 1 1 37 75 100 150
1 0 0 6.25 12.5 17 25 31 960
1 0 1 50 100 133
1 1 0 100 200 267

1
1

1 1 1 0.24 < 62.5 0.49 < 62.5 0.65 < 55.6 0.98 < 50.0 1.22 < 52.1 96 × (256 – (reload value Timer 1))

0 < 255 0 < 254 0 < 253 0 <251 0 < 250 reload value Timer 1 in Mode 2.

NOTES:

1. These frequencies exceed the upper limit of 100kHz of the I

2. At f

= 24MHz/ 30MHz the maximum I2C bus rate of 100kHz cannot be realized due to the fixed divider rates.

OSC

2

C-bus specification and cannot be used in an I2C-bus application.

OSC

200
400

2

1
1
1

1
1

30MHz

134
156
188

250
500

2

1
1
1

1
1

f

DIVIDED BY

OSC

224
192
160

120

60

ABSOLUTE MAXIMUM RATINGS

1, 2, 3

PARAMETER RATING UNIT

Storage temperature range –65 to +150 °C
Voltage on any other pin to V

SS

–0.5 to +6.5 V
Input, output DC current on any single I/O pin 5.0 mA
Power dissipation

1.0 W

(based on package heat transfer limitations, not device power consumption)

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section
of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging ef fects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise
noted.

DEVICE SPECIFICATIONS

SUPPLY VOLTAGE (V) FREQUENCY (MHz)

TYPE MIN MAX MIN MAX TEMPERATURE RANGE (°C)

P83(0)C552EBx 4.5 5.5 3.5 16 0 to +70
P83(0)C552EFx 4.5 5.5 3.5 16 –40 to +85
P83(0)C552EHx 4.5 5.5 3.5 16 –40 to +125
P83(0)C552IBx 4.5 5.5 3.5 24 0 to +70
P83(0)C552IFx 4.5 5.5 3.5 24 –40 to +85
P83(0)C552KBx 4.5 5.5 3.5 30 0 to +70

1998 Aug 13

9

Philips Semiconductors Product specification

8

Single-chip 8-bit microcontroller

80C552/83C552

DC ELECTRICAL CHARACTERISTICS

VSS, AVSS = 0V; VDD, AVDD = 5V ± 10%

TEST LIMITS

SYMBOL P ARAMETER CONDITIONS MIN MAX UNIT

I

DD

I

ID

I

PD

Inputs

V

IL

V

IL1

V

IL2

V

IH

V

IH1

V

IH2

I

IL

I

TL

±I

IL1

±I

IL2

±I

IL3

Outputs

V

OL

V

OL1

V

OL2

V

OH

V

OH1

V

OH2

R

RST

C

IO

Supply current operating: See notes 1 and 2

P83(0)C552EBx f
P83(0)C552EFx f
P83(0)C552EHx f
P83(0)C552IBx f
P83(0)C552IFx f
P83(0)C552KBx f

= 16MHz 45 mA

OSC

= 16MHz 45 mA

OSC

= 16MHz 40 mA

OSC

= 24MHz 55 mA

OSC

= 24MHz 55 mA

OSC

= 30MHz 68 mA

OSC

Idle mode: See notes 1 and 3

P83(0)C552EBx f
P83(0)C552EFx f
P83(0)C552EHx f
P83(0)C552IBx f
P83(0)C552IFx f
P83(0)C552KBx f

= 16MHz 10 mA

OSC

= 16MHz 10 mA

OSC

= 16MHz 9 mA

OSC

= 24MHz 12.5 mA

OSC

= 24MHz 12.5 mA

OSC

= 30MHz 15 mA

OSC

Power-down current: See notes 1 and 4;

2V < VPD < VDD max
P83(0)C552xBx 50 µA
P83(0)C552xFx 50 µA
P83(0)C552xHx 150 µA

Input low voltage, except EA, P1.6, P1.7 –0.5 0.2VDD–0.1 V
Input low voltage to EA –0.5 0.2VDD–0.3 V
Input low voltage to P1.6/SCL, P1.7/SDA

5

–0.5 0.3V

DD

Input high voltage, except XTAL1, RST, P1.6/SCL, P1.7/SDA 0.2VDD+0.9 VDD+0.5 V
Input high voltage, XTAL1, RST 0.7V
Input high voltage, P1.6/SCL, P1.7/SDA

5

0.7V

DD
DD

VDD+0.5 V

6.0 V
Logical 0 input current, ports 1, 2, 3, 4, except P1.6, P1.7 VIN = 0.45V –50 µA
Logical 1-to-0 transition current, ports 1, 2, 3, 4, except P1.6, P1.7 See note 6 –650 µA

0V < V

DD

< V

I

< 6V

I

< 5.5V

< V

I

7
7
7

DD

DD

10 µA
10 µA

1 µA

0.45 V

0.45 V

0.4 V

Input leakage current, port 0, EA, STADC, EW 0.45V < V
Input leakage current, P1.6/SCL, P1.7/SDA

0V < V

Input leakage current, port 5 0.45V < V

Output low voltage, ports 1, 2, 3, 4, except P1.6, P1.7 IOL = 1.6mA
Output low voltage, port 0, ALE, PSEN, PWM0, PWM1 IOL = 3.2mA
Output low voltage, P1.6/SCL, P1.7/SDA IOL = 3.0mA
Output high voltage, ports 1, 2, 3, 4, except P1.6/SCL, P1.7/SDA –IOH = 60µA 2.4 V

Output high voltage (port 0 in external bus mode, ALE,
PSEN, PWM0, PWM1)

–IOH = 25µA 0.75V
–IOH = 10µA 0.9V

–IOH = 400µA
–IOH = 150µA 0.75V

–IOH = 40µA 0.9V

DD

DD

2.4 V

DD

DD

Output high voltage (RST) –IOH = 400µA 2.4 V

–IOH = 120µA 0.8V

DD

Internal reset pull-down resistor 50 150 kΩ
Pin capacitance Test freq = 1MHz,

T

= 25°C

amb

10 pF

V

V
V

V
V

V

1998 Aug 13

10

Philips Semiconductors Product specification

Single-chip 8-bit microcontroller

80C552/83C552

DC ELECTRICAL CHARACTERISTICS (Continued)

TEST LIMITS
SYMBOL PARAMETER CONDITIONS MIN MAX UNIT
Analog Inputs

AI

DD

AI

ID

AI

PD

AV

IN

AV

REF

R

REF

C

IA

t

ADS

t

ADC

DL

e

IL

e

OS

e

G

e

A

e

M

CTC

C

t

NOTES FOR DC ELECTRICAL CHARACTERISTICS:

1. See Figures 10 through 15 for I

2. The operating supply current is measured with all output pins disconnected; XTAL1 driven with t
V

3. The idle mode supply current is measured with all output pins disconnected; XTAL1 driven with t
V

4. The power-down current is measured with all output pins disconnected; XTAL2 not connected; Port 0 = EW
EA

5. The input threshold voltage of P1.6 and P1.7 (SIO1) meets the I
0 while an input voltage above 3.0V will be recognized as a logic 1.

6. Pins of ports 1 (except P1.6, P1.7), 2, 3, and 4 source a transition current when they are being externally driven from 1 to 0. The transition
current reaches its maximum value when VIN is approximately 2V .

7. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V
to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the
worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V . In such cases, it may be desirable to qualify
ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. I
single output sinks more than 5mA and no more than two outputs exceed the test conditions.

8. Capacitive loading on ports 0 and 2 may cause the V
address bits are stabilizing.

9. The following condition must not be exceeded: V

10.Conditions: AV
continuous conversion of AV

11.The differential non-linearity (DL

12.The ADC is monotonic; there are no missing codes.

Analog supply current: operating: (16MHz) Port 5 = 0 to AV
Analog supply current: operating: (24MHz, 30MHz) Port 5 = 0 to AV

DD
DD

Idle mode:

P83(0)C552EBx 50 µA
P83(0)C552EFx 50 µA
P83(0)C552EHx 100 µA
P83(0)C552IBx 50 µA
P83(0)C552IFx 50 µA
P83(0)C552KBx 50 µA

Power-down mode: 2V < AVPD < A VDD max

P83(0)C552xBx 50 µA
P83(0)C552xFx 50 µA

P83(0)C552xHx 100 µA
Analog input voltage AVSS–0.2 AVDD+0.2 V
Reference voltage:

AV

REF–

AV

REF+

Resistance between AV

REF+

and AV

REF–

AVSS–0.2 V

AVDD+0.2 V

10 50 kΩ
Analog input capacitance 15 pF
Sampling time 8t
Conversion time (including sampling time) 50t
Differential non-linearity
Integral non-linearity
Offset error
Gain error

10, 14

10, 15

Absolute voltage error

10, 11, 12

10, 13

10, 16

Channel to channel matching ±1 LSB
Crosstalk between inputs of port 5

test conditions.

DD

= VDD – 0.5V; XTAL2 not connected; EA = RST = Port 0 = EW = VDD; STADC = VSS.

IH

= VDD – 0.5V; XTAL2 not connected; Port 0 = EW = VDD; EA = RST = STADC = VSS.

IH

= RST = STADC = XTAL1 = VSS.

= 0V; AVDD = 5.0V, AV

REF–

= –20mV to 5.12V in steps of 0.5mV .

IN

) is the difference between the actual step width and the ideal step width. (See Figure 1.)

e

17

0–100kHz –60 dB

= tf = 10ns; VIL = VSS + 0.5V;

r

= tf = 10ns; VIL = VSS + 0.5V;

r

= VDD;

2

C specification, so an input voltage below 1.5V will be recognized as a logic

s of ALE and ports 1 and 3. The noise is due

OL

can exceed these conditions provided that no

OL

on ALE and PSEN to momentarily fall below the 0.9VDD specification when the

OH

– 0.2V < AVDD < VDD + 0.2V.

DD

(80C552, 83C552) = 5.12V . ADC is monotonic with no missing codes. Measurement by

REF+

1.2 mA

1.0 mA

CY

CY

±1 LSB
±2 LSB
±2 LSB

±0.4 %

±3 LSB

µs
µs

1998 Aug 13

11

Philips Semiconductors Product specification

Single-chip 8-bit microcontroller

13.The integral non-linearity (IL
appropriate adjustment of gain and offset error. (See Figure 1.)

14.The offset error (OS
a straight line which fits the ideal transfer curve. (See Figure 1.)

15.The gain error (G
and the straight line which fits the ideal transfer curve. Gain error is constant at every point on the transfer curve. (See Figure 1.)

e

) is the relative difference in percent between the straight line fitting the actual transfer curve (after removing offset error),

e

16.The absolute voltage error (A
ADC and the ideal transfer curve.

) is the peak difference between the center of the steps of the actual and the ideal transfer curve after

e

) is the absolute difference between the straight line which fits the actual transfer curve (after removing gain error), and

) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated

e

80C552/83C552

17.This should be considered when both analog and digital signals are simultaneously input to port 5.

Offset

error
OS

1023

1022

1021

1020

1019

Gain
error

G

e

e

Code

Out

1018

7

6

5

4

3

2

1

0

1 2 3 4 5 6 7 1018 1019 1020 1021 1022 1023 1024

Offset

error
OS

e

(1) Example of an actual transfer curve.
(2) The ideal transfer curve.
(3) Differential non-linearity (DL
(4) Integral non-linearity (IL
(5) Center of a step of the actual transfer curve.

(2)

(1)

(5)

(4)

(3)

1 LSB
(ideal)

AVIN (LSB

AV

1 LSB =

).

e

).

e

REF+

1024

– AV

ideal

REF–

)

1998 Aug 13

Figure 1. ADC Conversion Characteristic

12

Philips Semiconductors Product specification

Single-chip 8-bit microcontroller

AC ELECTRICAL CHARACTERISTICS

1, 2

80C552/83C552

16 MHz version

16MHz CLOCK VARIABLE CLOCK

SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT

1/t

CLCL

t

LHLL

t

AVLL

t

LLAX

t

LLIV

t

LLPL

t

PLPH

t

PLIV

t

PXIX

t

PXIZ

t

AVIV

t

PLAZ

Data Memory

t

RLRH

t

WLWH

t

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVWL

t

QVWX

t

DW

t

WHQX

t

RLAZ

t

WHLH

External Clock

t

CHCX

t

CLCX

t

CLCH

t

CHCL

Serial Timing – Shift Register Mode4 (Test Conditions: T

t

XLXL

t

QVXH

t

XHQX

t

XHDX

t

XHDV

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN

3. t

4. These values are characterized but not 100% production tested.

= 1/f

CLCL

t

= 83.3ns at f

CLCL

= 62.5ns at f

t

CLCL

2 Oscillator frequency 3.5 16 MHz
2 ALE pulse width 85 2t
2 Address valid to ALE low 8 t
2 Address hold after ALE low 28 t
2 ALE low to valid instruction in 150 4t
2 ALE low to PSEN low 23 t
2 PSEN pulse width 143 3t
2 PSEN low to valid instruction in 83 3t

–40 ns

CLCL

–55 ns

CLCL

–35 ns

CLCL

–100 ns

CLCL

–40 ns

CLCL

–45 ns

CLCL

–105 ns

CLCL

2 Input instruction hold after PSEN 0 0 ns
2 Input instruction float after PSEN 38 t
2 Address to valid instruction in 208 5t

–25 ns

CLCL

–105 ns

CLCL

2 PSEN low to address float 10 10 ns

3 RD pulse width 275 6t
4 WR pulse width 275 6t
3 RD low to valid data in 148 5t

–100 ns

CLCL

–100 ns

CLCL

–165 ns

CLCL

3 Data hold after RD 0 0 ns
3 Data float after RD 55 2t
3 ALE low to valid data in 350 8t

3 Address to valid data in 398 9t
3, 4 ALE low to RD or WR low 138 238 3t
3, 4 Address valid to WR low or RD low 120 4t

4 Data valid to WR transition 3 t

4 Data before WR 288 7t

4 Data hold after WR 13 t

–50 3t

CLCL

–130 ns

CLCL

–60 ns

CLCL

–150 ns

CLCL

–50 ns

CLCL

–70 ns

CLCL

–150 ns

CLCL

–165 ns

CLCL

+50 ns

CLCL

3 RD low to address float 0 0 ns
3, 4 RD or WR high to ALE high 23 103 t

5 High time

5 Low time

5 Rise time

5 Fall time

4

4

4

4

= 0°C to +70°C; VSS = 0V; Load Capacitance = 80pF)

amb

20 20 ns
20 20 ns

20 20 ns
20 20 ns

6 Serial port clock cycle time 0.75 12t

6 Output data setup to clock rising edge 492 10t

6 Output data hold after clock rising edge 8 2t

–40 t

CLCL

CLCL

–133 ns

CLCL

–117 ns

CLCL

+40 ns

CLCL

6 Input data hold after clock rising edge 0 0 ns

6 Clock rising edge to input data valid 492 10t

–133 ns

CLCL

= 100pF, load capacitance for all other outputs = 80pF.

= one oscillator clock period.

OSC

OSC
OSC

= 12MHz.
= 16MHz.

µs

1998 Aug 13

13

Philips Semiconductors Product specification

Single-chip 8-bit microcontroller

AC ELECTRICAL CHARACTERISTICS (Continued)

1, 2

80C552/83C552

24/30 MHz version

24MHz CLOCK 30MHz CLOCK VARIABLE CLOCK

SYMBOL FIGURE PARAMETER MIN MAX MIN MAX MIN MAX UNIT

1/t

CLCL

t

LHLL

t

AVLL

t

LLAX

t

LLIV

t

LLPL

t

PLPH

t

PLIV

t

PXIX

t

PXIZ

t

AVIV

t

PLAZ

Data Memory

t

RLRH

t

WLWH

t

RLDV

t

RHDX

t

RHDZ

t

LLDV

t

AVDV

t

LLWL

t

AVWL

t

QVWX

t

DW

t

WHQX

t

RLAZ

t

WHLH

External Clock

t

CHCX

t

CLCX

t

CLCH

t

CHCL

Serial Timing – Shift Register Mode3 (Test Conditions: T

t

XLXL

t

QVXH

t

XHQX

t

XHDX

t

XHDV

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN

3. These values are characterized but not 100% production tested.

4. t

= 1/f

CLCL

t

= 41.7ns at f

CLCL

2 Oscillator frequency 3.5 24 MHz
2 ALE pulse width 43 27 2t
2 Address valid to ALE low 17 8 t
2 Address hold after ALE low 17 8 t
2 ALE low to valid instruction in 102 68 4t
2 ALE low to PSEN low 17 8 t
2 PSEN pulse width 80 55 3t
2 PSEN low to valid instruction in 65 40 3t

–40 ns

CLCL

–25 ns

CLCL

–25 ns

CLCL

–65 ns

CLCL

–25 ns

CLCL

–45 ns

CLCL

–60 ns

CLCL

2 Input instruction hold after PSEN 0 0 0 ns
2 Input instruction float after PSEN 17 8 t
2 Address to valid instruction in 128 87 5t

–25 ns

CLCL

–80 ns

CLCL

2 PSEN low to address float 10 10 10 ns

3 RD pulse width 150 100 6t
4 WR pulse width 150 100 6t
3 RD low to valid data in 118 77 5t

–100 ns

CLCL

–100 ns

CLCL

–90 ns

CLCL

3 Data hold after RD 0 0 0 ns
3 Data float after RD 55 39 2t
3 ALE low to valid data in 183 117 8t

3 Address to valid data in 210 135 9t
3, 4 ALE low to RD or WR low 75 175 50 150 3t
3, 4 Address valid to WR low or RD low 92 58 4t

4 Data valid to WR transition 12 3 t

4 Data before WR 162 103 7t

4 Data hold after WR 17 8 t

–50 3t

CLCL

–75 ns

CLCL

–30 ns

CLCL

–130 ns

CLCL

–25 ns

CLCL

–28 ns

CLCL

–150 ns

CLCL

–165 ns

CLCL

+50 ns

CLCL

3 RD low to address float 0 0 0 ns
3, 4 RD or WR high to ALE high 17 67 8 58 t

5 High time

5 Low time

5 Rise time

5 Fall time

3

3

3

3

amb

17 15 17 ns
17 15 17 ns

5 3 20 ns
5 3 20 ns

= 0°C to +70°C; VSS = 0V; Load Capacitance = 80pF)
6 Serial port clock cycle time 0.5 0.4 12t
6 Output data setup to clock rising edge 283 200 10t
6 Output data hold after clock rising edge 23 6.6 2t

–25 t

CLCL

CLCL

–133 ns

CLCL

–60 ns

CLCL

+25 ns

CLCL

6 Input data hold after clock rising edge 0 0 0 ns
6 Clock rising edge to input data valid 283 200 10t

–133 ns

CLCL

= 100pF, load capacitance for all other outputs = 80pF.

= one oscillator clock period.

OSC

OSC

= 24MHz.

µs

1998 Aug 13

14

Philips Semiconductors Product specification

Single-chip 8-bit microcontroller

80C552/83C552

AC ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL PARAMETER INPUT OUTPUT

I2C Interface (Refer to Figure 9)

t

HD;STA

t

LOW

t

HIGH

t

RC

t

FC

t

SU;DAT1

t

SU;DAT2

t

SU;DAT3

t

HD;DAT

t

SU;STA

t

SU;STO

t

BUF

t

RD

t

FD

NOTES:

1. At 100 kbit/s. At other bit rates this value is inversely proportional to the bit-rate of 100 kbit/s.

2. Determined by the external bus-line capacitance and the external bus-line pull-resistor, this must be < 1µs.

3. Spikes on the SDA and SCL lines with a duration of less than 3 t
SCL = 400pF.

4. t

CLCL

1.2MHz) the SI01 interface meets the I

STAR T condition hold time ≥ 14 t
SCL low time ≥ 16 t
SCL high time ≥ 14 t

CLCL
CLCL
CLCL

SCL rise time ≤ 1µs –
SCL fall time ≤ 0.3µs < 0.3µs
Data set-up time ≥ 250ns > 20 t
SDA set-up time (before rep. STAR T cond.) ≥ 250ns > 1µs
SDA set-up time (before STOP cond.) ≥ 250ns > 8 t
Data hold time ≥ 0ns > 8 t
Repeated START set-up time ≥ 14 t
STOP condition set-up time ≥ 14 t
Bus free time ≥ 14 t

CLCL
CLCL
CLCL

SDA rise time ≤ 1µs –
SDA fall time ≤ 0.3µs < 0.3µs

will be filtered out. Maximum capacitance on bus-lines SDA and

CLCL

= 1/f

= one oscillator clock period at pin XTAL1. For 62ns, 42ns, 33.3ns < t

OSC

2

C-bus specification for bit-rates up to 100 kbit/s.

< 285ns (16MHz, 24MHz, 30MHz > f

CLCL

> 4.0µs
> 4.7µs
> 4.0µs

CLCL

CLCL

> 4.7µs
> 4.0µs
> 4.7µs

2

– t

CLCL

– t

2

1

1
1
1

3

FC

1
1
1

3

OSC

RD

>

1998 Aug 13

15

Philips Semiconductors Product specification

Single-chip 8-bit microcontroller

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The
first character is always ‘t’ (= time). The other
characters, depending on their positions,
indicate the name of a signal or the logical
status of that signal. The designations are:
A – Address
C – Clock
D – Input data
H – Logic level high
I – Instruction (program memory contents)
L – Logic level low, or ALE
P – PSEN

t

ALE

PSEN

PORT 0

LHLL

Q – Output data
R–RD
t – Time
V – Valid
W– WR
X – No longer a valid logic level
Z – Float
Examples: t

t

AVLL

t

t

LLAX

A0–A7 A0–A7

LLPL

t

LLIV

signal

signal

t

= Time for address valid to

AVLL

ALE low.

= Time for ALE low to

LLPL

PSEN

low.

t

PLPH

t

PLIV

t

t

PLAZ

t

PXIX

INSTR IN

PXIZ

80C552/83C552

ALE

PSEN

PORT 0

PORT 2

RD

PORT 2

t

AVLL

t

LLAX

A0–A7

FROM RI OR DPL

t

AVWL

t

AVIV

A8–A15 A8–A15

Figure 2. External Program Memory Read Cycle

t

WHLH

t

LLDV

t

LLWL

t

RLAZ

t

AVDV

P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH

t

RLDV

t

RLRH

t

RHDZ

t

RHDX

DATA IN A0–A7 FROM PCL INSTR IN

1998 Aug 13

Figure 3. External Data Memory Read Cycle

16

Philips Semiconductors Product specification

Single-chip 8-bit microcontroller

ALE

PSEN

t

LLWL

WR

t

LLAX

A0–A7

FROM RI OR DPL

t

AVWL

t

P2.0–P2.7 OR A8–A15 FROM DPH A8–A15 FROM PCH

PORT 0

PORT 2

t

AVLL

80C552/83C552

t

WHLH

t

WLWH

t

QVWX

t

DW

DATA OUT A0–A7 FROM PCL INSTR IN

WHQX

INSTRUCTION

ALE

CLOCK

OUTPUT DATA

WRITE TO SBUF

INPUT DATA

CLEAR RI

Figure 4. External Data Memory Write Cycle

0.8V

t

t

HIGH

V

IH1

V

IH1

0.8V

t

LOW

r

V

IH1

0.8V 0.8V

t

CLCL

t

f

V

IH1

Figure 5. External Clock Drive XTAL1

012345678

t

XLXL

t

t

QVXH

01234567

XHQX

t

XHDV

VALID VALID VALID VALID VALID VALID VALID VALID

t

XHDX

SET TI

SET RI

Figure 6. Shift Register Mode Timing

1998 Aug 13

17

Philips Semiconductors Product specification

Single-chip 8-bit microcontroller

VDD–0.5

0.45V

NOTE:
AC INPUTS DURING TESTING ARE DRIVEN AT V

0.45V FOR A LOGIC ‘0’. TIMING MEASUREMENTS ARE MADE AT V
LOGIC ‘1’ AND V

MAX FOR A LOGIC ‘0’.

IL

Figure 7. AC Testing Input/Output

START or repeated START condition

SDA

(INPUT/OUTPUT)

SCL

(INPUT/OUTPUT)

t

FDtRC

t

HD;STA

0.2V

0.2V

DD
DD

t

LOW

+0.9

–0.1

–0.5 FOR A LOGIC ‘1’ AND

DD

t

RD

t

HIGH

t

FC

t

MIN FOR A

IH

SU;DAT1

t

HD;DAT

80C552/83C552

V

+0.1V

V

LOAD

LOAD

V

–0.1V

LOAD

NOTE:
FOR TIMING PURPOSES, A PORT IS NO LONGER FLOATING WHEN A 100MV
CHANGE FROM LOAD VOLTAGE OCCURS, AND BEGINS TO FLOAT WHEN A
100mV CHANGE FROM THE LOADED V
20mA.

Figure 8. Float Waveform

repeated START condition

STOP condition

OH/VOL

t

t

SU;DAT2

TIMING

REFERENCE

POINTS

LEVEL OCCURS. IOH/IOL > +

SU;STA

t

BUF

t

SU;STO

0.7 V

CC

0.3 V

CC

t

SU;DAT3

START condition

0.7 V

CC

0.3 V

CC

–0.1V

V

OH

V

+0.1V

OL

Figure 9. Timing SIO1 (I2C) Interface

1998 Aug 13

18

Philips Semiconductors Product specification

Single-chip 8-bit microcontroller

50

40

30

, I

mA

I

DD

D

20

10

0

0

NOTE:
These values are valid only within the frequency specifications of the device under test.

f (MHz)

80C552/83C552

(1)

(2)

(3)

(4)

124168

(1) Maximum operating mode; V
(2) Maximum operating mode; V
(3) Maximum idle mode; V
(4) Maximum idle mode; V

DD
DD

= 6V
= 4V

DD
DD

= 6V
= 4V

Figure 10. 16MHz Version Supply Current (IDD) as a Function of Frequency at XTAL1 (f

60

50

40

I

, I

DD

NOTE:
These values are valid only within the frequency specifications of the device under test.

30

mA

D

20

10

0

0

f (MHz)

)

OSC

(1)

(2)

(3)
(4)

124168

20 24

(1) Maximum operating mode; V
(2) Maximum operating mode; V
(3) Maximum idle mode; V
(4) Maximum idle mode; V

DD
DD

DD
DD

= 5.5V
= 4.5V

= 5.5V
= 4.5V

1998 Aug 13

Figure 11. 24MHz Version Supply Current (IDD) as a Function of Frequency at XTAL1 (f

19

OSC

)

Philips Semiconductors Product specification

Single-chip 8-bit microcontroller

V

DD

P1.6
P1.7

V

DD

RST
STADC

(NC)

CLOCK SIGNAL

XTAL2
XTAL1

V

SS

Figure 12. IDD Test Condition, Active Mode

All other pins are disconnected

VDD–0.5

0.5V

0.7V

DD

0.2VDD–0.1

t

CHCL

t

CLCX

AV

V

AV

ref–

t

CLCL

DD

P0

EW

SS

EA

t

CHCX

t

CLCH

I

DD

V

DD

1

80C552/83C552

V

DD

CLOCK SIGNAL

V

DD

P1.6
P1.7

RST

STADC

(NC)

XTAL2
XTAL1

V

SS

Figure 13. IDD Test Condition, Idle Mode

All other pins are disconnected

V

DD

P1.6
P1.7
RST

STADC

(NC)

XTAL2
XTAL1

V

SS

V

DD

P0

EW

EA

AV

SS

AV

ref–

2

I

DD

V

DD

P0

EW

EA

AV

SS

AV

ref–

I

DD

V

V

DD

DD

V

DD

V

DD

Figure 14. Clock Signal Waveform for IDD Tests in Active

and Idle Modes t

CLCH

= t

CHCL

= 5ns

NOTES:

1. Active Mode:
a. The following pins must be forced to V

b. The following pins must be forced to V
c. Ports 1.6 and 1.7 should be connected to V

exceed the I

spec of these pins.

OL1

: EA, RST, Port 0, and EW.

DD

: STADC, AVss, and AV

SS

through resistors of sufficiently high value such that the sink current into these pins cannot

DD

ref–

.

d. The following pins must be disconnected: XTAL2 and all pins not specified above.

2. Idle Mode:
a. The following pins must be forced to V

b. The following pins must be forced to V
c. Ports 1.6 and 1.7 should be connected to V

exceed the I

spec of these pins. These pins must not have logic 0 written to them prior to this measurement.

OL1

: Port 0 and EW.

DD

: RST, STADC, AVss,, AV

SS

through resistors of sufficiently high value such that the sink current into these pins cannot

DD

, and EA.

ref–

d. The following pins must be disconnected: XTAL2 and all pins not specified above.

3. Power Down Mode:
a. The following pins must be forced to V

b. The following pins must be forced to V
c. Ports 1.6 and 1.7 should be connected to V

exceed the I

spec of these pins. These pins must not have logic 0 written to them prior to this measurement.

OL1

: Port 0 and EW.

DD

: RST, STADC, XTAL1, AVss,, AV

SS

through resistors of sufficiently high value such that the sink current into these pins cannot

DD

d. The following pins must be disconnected: XTAL2 and all pins not specified above.

Purchase of Philips I2C components conveys a license under the Philips’ I2C patent
to use the components in the I2C system provided the system conforms to the

2

I

C specifications defined by Philips. This specification can be ordered using the

code 9398 393 40011.

Figure 15. IDD Test Condition, Power Down Mode

All other pins are disconnected. V

, and EA.

ref–

= 2V to 5.5V

DD

3

1998 Aug 13

20

Philips Semiconductors Product specification

80C552/83C552Single-chip 8-bit microcontroller

PLCC68: plastic leaded chip carrier; 68 leads SOT188-2

1998 Aug 13

21

Philips Semiconductors Product specification

80C552/83C552Single-chip 8-bit microcontroller

QFP80: plastic quad flat package; 80 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT318-2

1998 Aug 13

22

Philips Semiconductors Product specification

80C552/83C552Single-chip 8-bit microcontroller

NOTES

1998 Aug 13

23

Philips Semiconductors Product specification

80C552/83C552Single-chip 8-bit microcontroller

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1998

All rights reserved. Printed in U.S.A.

Date of release: 08-98

Document order number: 9397 750 04289

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1998 Aug 13

24