Datasheet 80c451, 83c451, 87c451 DATASHEETS (Philips)

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Page 1

INTEGRATED CIRCUITS

80C451/83C451/87C451

80C51 8-bit microcontroller family

4K/128 OTP/ROM/ROMless, expanded I/O

Product specification Supersedes data of 1998 Jan 19 IC20 Data Handbook

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1998 May 01

Page 2

Philips Semiconductors Product specification

80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

DESCRIPTION

The Philips 8XC451 is an I/O expanded single-chip microcontroller fabricated with Philips high-density CMOS technology. Philips epitaxial substrate minimizes latch-up sensitivity.

The 8XC451 (includes the 80C451, 87C451 and 83C451) is a functional extension of the 87C51 microcontroller with three additional I/O ports and four I/O control lines for a total of 68 pins. Four control lines associated with port 6 facilitate high-speed asynchronous I/O functions.

The 8XC451 includes a 4k × 8 ROM (83C451) EPROM (87C451), a 128 × 8 RAM, 56 I/O, two 16-bit timer/counters, a five source, two priority level, nested interrupt structure, a serial I/O port for either a full duplex UART, I/O expansion, or multi-processor communications, and on-chip oscillator and clock circuits. The 80C451 ROMless version includes all of the 83C451 features except the on-board 4k × 8 ROM.

The 87C451 has 4k of EPROM on-chip as program memory and is otherwise identical to the 83C451.

The 8XC451 has two software selectable modes of reduced activity for further power reduction; idle mode and power-down mode. Idle mode freezes the CPU while allowing the RAM, timers, serial port, and interrupt system to continue functioning. Power-down mode freezes the oscillator, causing all other chip functions to be inoperative while maintaining the RAM contents.

FEA TURES

•80C51 based architecture

•Seven 8-bit I/O ports

•Port 6 features:

– Eight data pins – Four control pins – Direct MPU bus interface – Parallel printer interface

•On the microcontroller:

– 4k × 8 ROM (83C451)

4k × 8 EPROM (87C451)

ROMless version (80C451) – 128 × 8 RAM – Two 16-bit counter/timers – Two external interrupts

•External memory addressing capability

– 64k ROM and 64k RAM

•Low power consumption:

– Normal operation: less than 24mA at 5V , 12MHz – Idle mode – Power-down mode

80C451/83C451/87C451

PIN CONFIGURATION

9161

27 43

Pin Function

1EA

2 P2.0/A8 3 P2.1/A9 4 P2.2/A10 5 P2.3/A11 6 P2.4/A12 7 P2.5/A13 8 P2.6/A14

9 P2.7/A15 10 P0.7/AD7 11 P0.6/AD6 12 P0.5/AD5 13 P0.4/AD4 14 P0.3/AD3 15 P0.2/AD2 16 P0.1/AD1 17 P0.0/AD0 18 V

19 P4.7 20 P4.6 21 P4.5 22 P4.4 23 P4.3

Pin Function

LCC

24 P4.2 25 P4.1 26 P4.0 27 P1.0 28 P1.1 29 P1.2 30 P1.3 31 P1.4 32 P1.5 33 P1.6 34 P1.7 35 RST 36 P3.0/RxD 37 P3.1/TxD 38 P3.2/INT0 39 P3.3/INT1 40 P3.4/T0 41 P3.5/T1 42 P3.6/WR 43 P3.7/RD 44 P5.0 45 P5.1 46 P5.2

Pin Function

47 P5.3 48 P5.4 49 P5.5 50 P5.6 51 P5.7 52 XTAL2 53 XTAL1 54 V

55 ODS 56 IDS 57 BFLAG 58 AFLAG 59 P6.0 60 P6.1 61 P6.2 62 P6.3 63 P6.4 64 P6.5 65 P6.6 66 P6.7 67 PSEN 68 ALE/PROG

SU00084A

1998 May 01 853-0830 19327

Page 3

Philips Semiconductors Product specification

80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

BLOCK DIAGRAM

P0.0–P0.7

PORT 0

DRIVERS

RAM ADDR REGISTER

RAM

ACC

TMP2

PORT 0

LATCH

P2.0–P2.7

PORT 2

DRIVERS

PORT 2

LATCH

TMP1

P4.0–P4.7

PORT 4

DRIVERS

PORT 4

LATCH

80C451/83C451/87C451

P5.0–5.7

PORT 5

DRIVERS

PORT 5

LATCH

STACK

POINTER

4K x 8

ROM/EPROM

PROGRAM

ADDRESS

PSEN

ALE/PROG

EAV

RST

TIMING

AND

CONTROL

OSCILLATOR

XTAL1 XTAL2

INSTRUCTION

PORT 1

LATCH

PORT 1

DRIVERS

P1.0–P1.7

PSW

ALU

PORT 6

LATCH

PORT 6

DRIVERS

P6.0–P6.7

PCON SCON TMOD TCON

TH0 TL0 TH1

TL1

SBUF IE IP

INTERRUPT, SERIAL

PORT AND TIMER BLOCKS

PORT 6

CONTROL/STATUS

IDS ODS

AFLAG

BFLAG

PORT 3

LATCH

PORT 3

DRIVERS

P3.0–P3.7

BUFFER

INCRE-

MENTER

PROGRAM COUNTER

DPTR

SU00086

1998 May 01

Page 4

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

80C451/83C451/87C451

4K/128 OTP/ROM/ROMless, expanded I/O

ORDERING INFORMATION

ROMless ROM EPROM

TEMPERATURE RANGE °C

AND PACKAGE

SC80C451CCA68 SC83C451CCA68 SC87C451CCA68 OTP 0 to +70, Plastic Leaded Chip Carrier, 3.5 to 12 SOT188-3 SC80C451CGA68 SC83C451CGA68 SC87C451CGA68 OTP 0 to +70, Plastic Leaded Chip Carrier 3.5 to 16 SOT188-3

NOTE:

1. OTP = One Time Programmable

LOGIC SYMBOL

XTAL1

ADDRESS AND

DATA BUS

ADDRESS BUS

ALE/PROG

RxD

TxD INT0 INT1

T0 T1

SECONDARY FUNCTIONS

XTAL2

RST /V

PSEN

PORT 3

PORT 0

PORT 1PORT 2

FREQ

MHz

DRAWING

NUMBER

PORT 6 CONTROL

ODS

IDS BFLAG AFLAG

PORT 6

PORT 4

PORT 5

SU00085

1998 May 01

Page 5

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

80C451/83C451/87C451

4K/128 OTP/ROM/ROMless, expanded I/O

PIN DESCRIPTION

MNEMONIC

P0.0–0.7 17-10 I/O Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 is also the multiplexed data and low-order

P1.0–P1.7 27-34 I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 receives the low-order

P2.0–P2.7 2-9 I/O Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 emits the high-order address

P3.0–P3.7 36-43 I/O Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 can sink/source three LS

P4.0–P4.7 26-19 I/O Port 4: Port 4 is a 8-bit (LCC) bidirectional I/O port with internal pull-ups. Port 4 can sink/source three

P5.0–P5.7 44-51 I/O Port 5: Port 5 is a 8-bit (LCC) bidirectional I/O port with internal pull-ups. Port 5 can sink/source three

P6.0–P6.7 59-66 I/O Port 6: Port 6 is a specialized 8-bit bidirectional I/O port with internal pull-ups. This special port can

ODS 55 I ODS: Output data strobe IDS 56 I IDS: Input data strobe BFLAG 57 I/O BFLAG: Bidirectional I/O pin with internal pull-ups AFLAG 58 I/O AFLAG: Bidirectional I/O pin with internal pull-ups RST 35 I Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An

ALE/PROG 68 I/O Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during

PSEN 67 O Program Store Enable: The read strobe to external program memory. PSEN is activated twice each

EA/V

XTAL1 53 I Crystal 1: Input to the inverting oscillator amplifier that forms the oscillator. This input receives the

XTAL2 52 O Crystal 2: An output of the inverting amplifier that forms the oscillator. This pin should be floated when

PIN NO.

TYPE NAME AND FUNCTION

54 I Ground: 0V reference. 18 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation.

address bus during accesses to external memory. External pull-ups are required during program verification. Port 0 can sink/source eight LS TTL inputs.

address bytes during program memory verification. Port 1 can sink/source three LS TTL inputs, and drive CMOS inputs without external pull-ups.

bytes during access to external memory and receives the high-order address bits and control signals during program verification. Port 2 can sink/source three LS TTL inputs, and drive CMOS inputs without external pull-ups.

TTL inputs, and drive CMOS inputs without external pull-ups. Port 3 also serves the special functions

listed below: 36 I RxD (P3.0): Serial input port 37 O TxD (P3.1): Serial output port 38 I INT0 (P3.2): External interrupt 39 I INT1 (P3.3): External interrupt 40 I T0 (P3.4): Timer 0 external input 41 I T1 (P3.5): Timer 1 external input 42 O WR (P3.6): External data memory write strobe 43 O RD (P3.7): External data memory read strobe

LS TTL inputs and drive CMOS inputs without external pull-ups.

sink/source three LS TTL inputs and drive CMOS inputs without external pull-ups. Port 6 can be used in

a strobed or non-strobed mode of operation. Port 6 works in conjunction with four control pins that

serve the functions listed below:

internal pull-down resistor permits a power-on reset using only an external capacitor connected to VCC.

an access to external memory. ALE is activated at a constant rate of 1/6 the oscillator frequency except

during an external data memory access, at which time one ALE is skipped. ALE can sink/source three

LS TTL inputs and drive CMOS inputs without external pull-ups. This pin is also the program pulse

during EPROM programming.

machine cycle during fetches from external program memory. However, when executing out of external

program memory, two activations of PSEN

memory. PSEN

eight LS TTL inputs and drive CMOS inputs without an external pull-up. This pin should be tied low

during programming.

1 I Instruction Execution Control/Programming Supply Voltage: When EA is held high, the CPU

executes out of internal program memory, unless the program counter exceeds 0FFFH. When EA is

held low, the CPU executes out of external program memory. EA

pin also receives the 12.75V programming supply voltage (V

external oscillator when an external oscillator is used.

an external oscillator is used.

is not activated during fetches from internal program memory. PSEN can sink/source

are skipped during each access to external program

must never be allowed to float. This

) during EPROM programming.

1998 May 01

Page 6

Philips Semiconductors Product specification

80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

I/O Port Structure

The 8XC451 has a total of seven parallel I/O ports. The first four ports, P0 through P3, are identical in function to those present on the 80C51 family. The added ports 4 and 5 are identical in function to port 1; that is, they are standard quasi-bidirectional ports with no alternate functions and the standard output drive characteristics. Port 6 is a specialized 8-bit bidirectional I/O port with internal pullups.

Ports 4 and 5

Ports 4 and 5 are bidirectional I/O ports with internal pull-ups. Port 4 is an 8-bit port. Port 4 and port 5 pins with ones written to them, are pulled high by the internal pull-ups, and in that state can be used as inputs. Port 4 and 5 are addressed at the special function register addresses shown in Table 1.

Port 6

Port 6 is a special 8-bit bidirectional I/O port with internal pull-ups (see Figure 1). This special port can sink/source three LS TTL inputs and drive CMOS inputs without external pullups. The flexibility of this port facilitates high-speed parallel data communications. This port can be used as a standard I/O port, or in strobed modes of operation in conjunction with four special control lines: ODS AFLAG, and BFLAG. Port 6 operating modes are controlled by the port 6 control status register (CSR). Port 6 and the CSR are addressed at the special function register addresses shown in Table

1. The following four control pins are used in conjunction with port 6:

ODS

– Output data strobe (Active Low) for port 6. ODS can be programmed to control the port 6 output drivers and the output buffer full flag (OBF), or to clear only the OBF flag bit in the CSR (output-always mode). ODS the OBF flag can be programmed to be cleared on the negative or positive edge of ODS

IDS – Input data strobe (Active Low) for port 6. IDS is used to control the port 6 input latch and input buffer full flag (IBF) bit in the CSR. The input data latch can be programmed to be transparent when IDS latch only on the positive transition of IDS flag is set on the negative or positive transition of IDS

BFLAG – BFLAG is a bidirectional I/O pin which can be programmed to be an output, set high or low under program control, or to output the state of the input buffer full flag. BFLAG can also be programmed to input an enable signal for port 6. When BFLAG is used as an enable input, port 6 output drivers are in the high-impedance state, and the input latch does not respond to the IDS BFLAG is low. This feature facilitates the use of the SC8XC451 in bused multiprocessor systems.

AFLAG – AFLAG is a bidirectional I/O pin which can be programmed to be an output set high or low under program control, or to output the state of the output buffer full flag. AFLAG can also be programmed to be an input which selects whether the contents of the output buffer, or the contents of the port 6 control status register will output on port 6. This feature grants complete port 6 status to external devices.

Port 6 can be used in a number of different ways to facilitate data communication. It can be used as a processor bus interface, as a standard quasi-bidirectional I/O port, or as a parallel printer port (either polled or interrupt driven).

is low and latched on the positive transition of IDS, or to

strobe when BFLAG is high. Both features are enabled when

is active low for output driver control.

. Correspondingly , the IBF

, IDS,

80C451/83C451/87C451

Processor Bus Interface

Port 6 allows the use of an 8XC451 as an element on a microprocessor type bus. The host processor could be a general purpose MPU or the data bus of a microcontroller like the 8XC451 itself. Setting up the 8XC451 as a processor bus interface allows single or multiple microcontrollers to be used on a bus as flexible peripheral processing elements. Applications can include: keyboard scanners, serial I/O controllers, servo controllers, etc.

On reset, port 6 is programmed correctly (that is, Special Function registers CSR and P6) for use as a bus interface. This prevents the interface from disrupting data on the bus of a host processor during power-up.

Standard Quasi-bidirectional I/O Port

To use port 6 as a common I/O port, all of the control pins should be tied to ground. On hardware reset, bits 2-7 of the CSR are set to one. With the control pins grounded, the port’s operation and electrical characteristics will be identical to port 1 on the 80C51. No further software initialization is required.

Parallel Printer Port

The 8XC451 has the capacity to permit all of the intelligent features of a common printer to be handled by a single chip. The features of port 6 allow a parallel port to be designed with only line driving and receiving chips required as additional hardware. The onboard UART allows RS232 interfacing with only level shifting chips added. The 8-bit parallel ports 0 to 6 are ample to drive onboard control functions, even when ports are used for external memory access, interrupts, and other functions. The RAM addressing ability of ports 0 to 2 can be used to address up to 64k bytes of a hardware buffer/spooler.

In addition, either end of a parallel interface can be implemented using port 6, and the interfaces can be interrupt driven or polled in either case. For more detailed information on port 6 usage, refer to the application notes entitled “80C451 Operation of Port 6” and “256k Centronics Printer Buffer Using the SC87C451 Microcontroller.”

CONTROL STATUS REGISTER

The control status register (CSR) establishes the mode of operation for port 6 and indicates the current status of port 6 I/O registers. All control status register bits can be read and written by the CPU, except bits 0 and 1, which are read only. Reset writes ones to bits 2 through 7, and writes zeros to bits 0 and 1 (see Table 3).

CSR.0 Input Buffer Full Flag (IBF) (Read Only) – The IBF bit is set to a logic 1 when port 6 data is loaded into the input buffer under control of IDS IDS

, as determined by CSR.2 IBF is cleared when the CPU reads

the input buffer register. CSR.1 Output Buffer Full Flag (OBF) (Read Only) – The OBF flag

is set to a logic 1 when the CPU writes to the port 6 output data buffer . OBF is cleared by the positive or negative edge of ODS determined by CSR.3.

CSR.2 IDS Mode Select (IDSM) – When CSR.2 = 0, a low-to-high transition on the IDS loaded on the IDS transition on the IDS transparent when IDS

. This can occur on the negative or positive edge of

, as

pin sets the IBF flag. The Port 6 input buffer is

positive edge. When CSR.2 = 1, a high-to-low

pin sets the IBF flag. Port 6 input buffer is

is low, and latched when IDS is high.

1998 May 01

Page 7

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

80C451/83C451/87C451

4K/128 OTP/ROM/ROMless, expanded I/O

CSR.3 Output Buffer Full Flag Clear Mode (OBFC) – When CSR.3 = 1, the positive edge of the ODS When CSR.3 = 0, the negative edge of the ODS

input clears the OBF flag.

input clears the

OBF flag.

CSR.4, CSR.5 AFLAG Mode Select (MA0, MA1) – Bits 4 and 5 select the mode of operation for the

AFLAG pin as follows:

MA1 MA0 AFLAG Function 0 0 Logic 0 output

0 1 Logic 1 output 1 0 OBF flag output (CSR.1) 1 1 Select (SEL) input mode

The select (SEL) input mode is used to determine whether the port 6 data register or the control status register is output on port 6. When the select feature is enabled, the AFLAG input controls the source of port 6 output data. A logic 0 on AFLAG input selects the port 6 data register, and a logic 1 on AFLAG input selects the control status register.

Table 1. Special Function Register Addresses

NAME SYMBOL ADDRESS MSB LSB

Port 4 P4 C0 C7 C6 C5 C4 C3 C2 C1 C0 Port 5 P5 C8 CF CE CD CC CB CA C9 C8 Port 6 data P6 D8 DF DE DD DC DB DA D9 D8 Port 6 control status CSR E8 EF EE ED EC EB EA E9 E8

CSR.6, CSR.7 BFLAG Mode Select (MB0, MB1) – Bits 6 and 7 select the mode operation as follows:

MB1 MB0 BFLAG Function

0 0 Logic 0 output 0 1 Logic 1 output 1 0 IBF flag output (CSR.0) 1 1 Port enable (PE

In the port enable mode, IDS

)

and ODS inputs are disabled when BFLAG input is high. When the BFLAG input is low, the port is enabled for I/O.

SPECIAL FUNCTION REGISTER ADDRESSES

The SFRs are identical to those of the standard 80C51 with the exception of four registers that have been added to allow control of the three additional I/O ports P4, P5, and P6. The additional registers are P4, P5, P6, and CSR. Registers P4, P5, and P6 function as port latches for ports 4, 5, and 6, respectively. These registers operate identically to those for ports 0 through 3 of the 80C51.

AFLAG

MODE

(CSR.4/.5)

OUTPUT BUFFER FULL (CSR.1)

ODSBFLAGAFLAG

BFLAG/ODS

MODE

(CSR.6/.7)

INPUT BUFFER FULL (CSR.0)

CONTROL/STATUS

PORT 6

OUTPUT

DRIVERS

MUX

OUTPUT BUFFER

(P6 WRITE)

INTERNAL BUS

INPUT

BUFFER

(P6 READ)

Figure 1. Port 6 Block Diagram

IDS

MODE

EDGE/LEVEL

SELECT (CSR.2)

SU00087

1998 May 01

Page 8

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

80C451/83C451/87C451

4K/128 OTP/ROM/ROMless, expanded I/O

Table 2. 8XC451 Special Function Registers

SYMBOL DESCRIPTION

ACC* Accumulator E0H E7 E6 E5 E4 E3 E2 E1 E0 00H B* B register F0H F7 F6 F5 F4 F3 F2 F1 F0 00H

CSR*# Port 6 command/status E8H MB1 MB0 MA1 MA0 OBFC IDSM OBF IBF FCH DPTR Data pointer (2 bytes)

DPH Data pointer high 83H 00H DPL Data pointer low 82H 00H

IP* Interrupt priority B8H – – – PS PT1 PX1 PT0 PX0 xxx00000B

IE* Interrupt enable A8H EA – – ES ET1 EX1 ET0 EX0 0xx00000B P0* Port 0 80H 87 B6 85 84 83 82 81 80 FFH P1* Port 1 90H 97 96 95 94 93 92 91 90 FFH P2* Port 2 A0H A7 A6 A5 A4 A3 A2 A1 A0 FFH P3* Port 3 B0H B7 B6 B5 B4 B3 B2 B1 B0 FFH P4*# Port 4 C0H C7 C6 C5 C4 C3 C2 C1 C0 FFH P5*# Port 5 C8H CF CE CD CC CB CA C9 C8 FFH P6*# Port 6 D8H DF DE DD DC DB DA D9 D8 FFH

DIRECT

ADDRESS

BIT NAMES AND ADDRESSES MSB LSB

EF EE ED EC EB EA E9 E8

BF BE BD BC BB BA B9 B8

AF AE AD AC AB AA A9 A8

RESET VALUE

PCON Power control 87H SMOD – – – GF1 GF0 PD IDL 0xxx0000B

D7 D6 D5 D4 D3 D2 D1 D0 PSW* Program status word D0H CY AC F0 RS1 RS0 OV – P 00H SBUF Serial data buffer 99H xxxxxxxxB

9F 9E 9D 9C 9B 9A 99 98 SCON* Serial port control 98H SM0 SM1 SM2 REN TB8 RB8 TI RI 00H SP Stack pointer 81H 07H

8F 8E 8D 8C 8B 8A 89 88 TCON* Timer/counter control 88H TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 00H

TMOD T imer/counter mode 89H GA TE C/T M1 M0 GATE C/T M1 M0 00H TH0 Timer 0 high byte 8CH 00H TH1 Timer 1 high byte 8DH 00H TL0 Timer 0 low byte 8AH 00H TL1 Timer 1 low byte 8BH 00H

* SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs.

1998 May 01

Page 9

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

80C451/83C451/87C451

4K/128 OTP/ROM/ROMless, expanded I/O

Table 3. Control Status Register (CSR)

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MB1 MB0 MA1 MA0 OBFC IDSM OBF IBF

BFLAG Mode Select AFLAG Mode Select Output Buffer

0/0 = Logic 0 output* 0/1 = Logic 1 output* 1/0 = IBF output 1/1 = PE (0 = Select) (1 = Disable I/O)

NOTE:

* Output-always mode: MB1 = 0, MA1 = 1, and MA0 = 0. In this mode, port 6 is always enabled for output. ODS

input

ABSOLUTE MAXIMUM RATINGS

Operating temperature under bias Storage temperature range –65 to +150 °C Voltage on any other pin to V Power dissipation (based on package heat transfer limitations, not device power consumption) 1.5 W

NOTES:

1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied.

2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima.

3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V noted.

0/0 = Logic 0 output* 0/1 = Logic 1 output* 1/0 = OBF output 1/1 = SEL input (0 = Select) (1 = Control/status)

1, 2, 3

PARAMETER

Flag Clear

Mode

0 = Negative

edge of ODS

1 = Positive

edge o ODS

Input Data

Strobe Mode

0 = Positive edge of IDS

1 = Low level

of IDS

Output Buffer

Flag Full

0 = Output data buffer

empty

1 = Output

data buffer full

only clears the OBF flag.

RATING UNIT

0 to +70 °C

–0.5 to +6.5 V

Input Buffer

Flag Full

0 = Input data

buffer empty

1 = Input data

buffer full

unless otherwise

1998 May 01

Page 10

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

80C451/83C451/87C451

4K/128 OTP/ROM/ROMless, expanded I/O

DC ELECTRICAL CHARACTERISTICS

= 0°C to +70°C, VCC = 5V ±10%, VSS = 0V (87C451, 83C451, 80C451)

amb

SYMBOL PARAMETER CONDITIONS MIN TYPICAL

IL1

IH1

OL1

OH1

RST

NOTES:

1. Typical ratings are based on a limited number of samples taken from early manufacturing lots and are not guaranteed. The values listed are at room temperature, 5V .

2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the V to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V . In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input.

3. Capacitive loading on ports 0 and 2 may cause the V address bits are stabilizing.

4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN is approximately 2V .

5. I

CCMAX

where FREQ is the external oscillator frequency in MHz. I

6. See Figures 14 through 17 for ICC test conditions.

7. C

Input low voltage; except EA –0.5 0.2VCC–0.1 V Input low voltage to EA 0 0.2VCC–0.3 V Input high voltage; except XTAL1, RST 0.2VCC+0.9 VCC+0.5 V Input high voltage; XTAL1, RST 0.7V Output low voltage; ports 1, 2, 3, 4, 5, 6 IOL = 1.6mA Output low voltage; port 0, ALE, PSEN IOL = 3.2mA Output high voltage; ports 1, 2, 3, 4, 5, 6 IOH = –60µA, 2.4 V

Output high voltage (port 0 in external bus mode, ALE,

PSEN)

Logical 0 input current,; ports 1, 2, 3, 4, 5, 6 VIN = 0.45V –50 µA Logical 1-to-0 transition current; ports 1, 2, 3, 4, 5, 6 See note 4 –650 µA Input leakage current; port 0 VIN = VIL or V Power supply current: See note 6

Active mode @ 12MHz Idle mode @ 12MHz

Power down mode 3 50 µA Internal reset pull-down resistor 50 300 kΩ Pin capacitance

at other frequencies is given by: Active mode: I Idle mode: I

CCMAX

= 0.94 X FREQ + 13.71

CCMAX

= 0.14 X FREQ +2.31

applies to ports 1 through 6, AFLAG, BFLAG, XTAL1, XTAL2.

TEST LIMITS

2 2

IOH = –25µA 0.75V IOH = –10µA 0.9V

IOH = –800µA,

IOH = –300µA

= –80µA

2.4

0.75V

0.9V

11.5 25 mA

1.3 4 mA

s of ALE and ports 1 and 3. The noise is due

on ALE and PSEN to momentarily fall below the 0.9VCC specification when the

is given in mA. See Figure 13.

CCMAX

MAX UNIT

VCC+0.5 V

0.45 V

V V

V V V

+10 µA

10 pF

1998 May 01

Page 11

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

80C451/83C451/87C451

4K/128 OTP/ROM/ROMless, expanded I/O

AC ELECTRICAL CHARACTERISTICS

= 0°C to +70°C, VCC = 5V ±10%, VSS = 0V (87C451, 83C451, 80C451)

amb

SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT

1/t

CLCL

LHLL

AVLL

LLAX

LLIV

LLPL

PLPH

PLIV

PXIX

PXIZ

AVIV

PLAZ

Data Memory

RLRH

WLWH

RLDV

RHDX

RHDZ

LLDV

AVDV

LLWL

AVWL

QVWX

WHQX

RLAZ

WHLH

3, 4 RD pulse width 400 6t 3, 4 WR pulse width 400 6t 3, 4 RD low to valid data in 252 5t 3, 4 Data hold after RD 0 0 ns 3, 4 Data float after RD 97 2t 3, 4 ALE low to valid data in 517 8t 3, 4 Address to valid data in 585 9t 3, 4 ALE low to RD or WR low 200 300 3t 3, 4 Address valid to WR low or RD low 203 4t 3, 4 Data valid to WR transition 23 t 3, 4 Data hold after WR 33 t 3, 4 RD low to address float 0 0 ns 3, 4 RD or WR high to ALE high 43 123 t

Shift Register

XLXL

QVXH

XHQX

XHDX

XHDV

NOTES: SEE NEXT PAGE

Oscillator frequency: Speed Versions SC8XC451 C 3.5 12 MHz

SC8XC451 G 3.5 16 MHz 2 ALE pulse width 127 2t 2 Address valid to ALE low 28 t 2 Address hold after ALE low 48 t 2 ALE low to valid instruction in 234 4t 2 ALE low to PSEN low 43 t 2 PSEN pulse width 205 3t 2 PSEN low to valid instruction in 145 3t 2 Input instruction hold after PSEN 0 0 ns 2 Input instruction float after PSEN 59 t 2 Address to valid instruction in 312 5t 2 PSEN low to address float 10 10 ns

5 Serial port clock cycle time 1.0 12t 5 Output data setup to clock rising edge 700 10t 5 Output data hold after clock rising edge 50 2t 5 Input data hold after clock rising edge 0 0 ns 5 Clock rising edge to input data valid 700 10t

12MHz CLOCK VARIABLE CLOCK

–40 ns

CLCL

–55 ns

CLCL

–35 ns

CLCL

–100 ns

CLCL

–40 ns

CLCL

–45 ns

CLCL

–105 ns

CLCL

–25 ns

CLCL

–105 ns

CLCL

–100 ns

CLCL

–100 ns

CLCL

–165 ns

CLCL

–70 ns

CLCL

–150 ns

CLCL

–165 ns

CLCL

–50 3t

CLCL

–130 ns

CLCL

–60 ns

CLCL

–50 ns

CLCL

–40 t

CLCL

–133 ns

CLCL

–117 ns

CLCL

+50 ns

CLCL

+40 ns

CLCL

–133 ns

CLCL

µs

1998 May 01

Page 12

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

80C451/83C451/87C451

4K/128 OTP/ROM/ROMless, expanded I/O

AC ELECTRICAL CHARACTERISTICS1 (continued)

= 0°C to +70°C, VCC = 5V ±10%, VSS = 0V (87C451, 83C451, 80C451)

amb

SYMBOL FIGURE PARAMETER MIN MAX MIN MAX UNIT

Port 6 input (input rise and fall times = 5ns)

FLFH

ILIH

DVIH

IHDX

IVFV

Port 6 output

OLOH

FVDV

OLDV

OHDZ

OVFV

FLDV

OHFH

External Clock

CHCX

CLCX

CLCH

CHCL

NOTES:

1. Parameters are valid over operating temperature range unless otherwise specified.

2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.

8 PE width 270 3t 8 IDS width 270 3t 8 Data setup to IDS high or PE high 0 0 ns 8 Data hold after IDS high or PE high 30 30 ns 9 IDS to BFLAG (IBF) delay 130 130 ns

6 ODS width 270 3t 7 SEL to data out delay 85 85 ns 6 ODS to data out delay 80 80 ns 6 ODS to data float delay 35 35 ns 6 ODS to AFLAG (OBF) delay 100 100 ns 6 PE to data out delay 120 120 ns 7 ODS to AFLAG (SEL) delay 100 100 ns

10 High time 20 20 ns 10 Low time 20 20 ns 10 Rise time 20 20 ns 10 Fall time 20 20 ns

12MHz CLOCK VARIABLE CLOCK

+20 ns

CLCL

+20 ns

CLCL

+20 ns

CLCL

1998 May 01

Page 13

Philips Semiconductors Product specification

80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

EXPLANATION OF THE AC SYMBOLS

Each timing symbol has five characters. The first character is always ‘t’ (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A – Address C – Clock D – Input data H – Logic level high I – Instruction (program memory contents) L – Logic level low, or ALE

ALE

PSEN

PORT 0

LHLL

AVLL

LLPL

LLAX

A0–A7 A0–A7

LLIV

PLIV

PLPH

PLAZ

PXIX

INSTR IN

80C451/83C451/87C451

P – PSEN Q – Output data R–RD t – Time V – Valid W– WR X – No longer a valid logic level Z – Float Examples: t

PXIZ

signal

= Time for address valid to ALE low.

AVLL

= Time for ALE low to PSEN low.

LLPL

ALE

PSEN

PORT 0

PORT 2

AVLL

LLAX

A0–A7

FROM RI OR DPL

AVWL

AVIV

A0–A15 A8–A15

Figure 2. External Program Memory Read Cycle

WHLH

LLDV

LLWL

RLAZ

AVDV

P2.0–P2.7 OR A8–A15 FROM DPH A0–A15 FROM PCH

RLDV

RLRH

RHDZ

RHDX

DATA IN A0–A7 FROM PCL INSTR IN

SU00006

1998 May 01

SU00007

Figure 3. External Data Memory Read Cycle

Page 14

Philips Semiconductors Product specification

80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

ALE

PSEN

WLWH

DATA OUT A0–A7 FROM PCL INSTR IN

PORT 0

PORT 2

AVLL

LLAX

A0–A7

FROM RI OR DPL

AVWL

LLWL

QVWX

P2.0–P2.7 OR A8–A15 FROM DPH A0–A15 FROM PCH

WHLH

80C451/83C451/87C451

WHQX

INSTRUCTION

ALE

CLOCK

OUTPUT DATA

WRITE TO SBUF

INPUT DATA

CLEAR RI

SU00008

Figure 4. External Data Memory Write Cycle

012345678

XLXL

QVXH

XHDV

VALID VALID VALID VALID VALID VALID VALID VALID

XHQX

1230 4567

XHDX

SET TI

SET RI

SU00027

Figure 5. Shift Register Mode Timing

1998 May 01

Page 15

Philips Semiconductors Product specification

80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

OBF (AFLAG)

OVFV

(BFLAG)

OLOH

ODS

PORT 6

ODS

OLDV

FLDV

Figure 6. Port 6 Output

OHFH

80C451/83C451/87C451

OVFV

OHDZ

SU00088

SEL (AFLAG)

PORT 6

PE (BFLAG)

IDS

PORT 6

IBF (BFLAG)

FVDV

DATA DATACSR

Figure 7. Port 6 Select Mode

FLFH

ILIH

Figure 8. Port 6 Input

FVDV

DVIH

IHDZ

SU00089

SU00090

1998 May 01

IDS

IVFV

Figure 9. IBF Flag Output

IVFV

SU00091A

Page 16

Philips Semiconductors Product specification

80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

VCC–0.5

0.45V

VCC–0.5

0.45V

NOTE: AC inputs during testing are driven at VCC –0.5 for a logic ‘1’ and 0.45V for a logic ‘0’. Timing measurements are made at VIH min for a logic ‘1’ and VIL max for a logic ‘0’.

0.7V

0.2VCC–0.1

CHCL

CLCX

Figure 10. External Clock Drive

0.2V

+0.9

0.2V

–0.1

Figure 11. AC Testing Input/Output

CLCL

CHCX

CLCH

80C451/83C451/87C451

SU00009

SU00010

+0.1V

LOAD

NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded V

LOAD

–0.1V

TIMING

REFERENCE

POINTS

OH/VOL

–0.1V

+0.1V

level occurs. IOH/IOL ≥ ±20mA.

SU00011

Figure 12. Float Waveform

ICC mA

MAX ACTIVE MODE

TYP ACTIVE MODE

MAX IDLE MODE

TYP IDLE MODE

1998 May 01

4MHz 8MHz 12MHz 16MHz

FREQ AT XTAL1

VALID ONLY WITHIN FREQUENCY SPECIFICATIONS OF THE DEVICE UNDER TEST.

SU00092

Figure 13. ICC vs. FREQ

Page 17

Philips Semiconductors Product specification

80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

RST

(NC)

CLOCK SIGNAL

XTAL2

XTAL1

Figure 14. ICC Test Condition, Active Mode

All other pins are disconnected

Figure 16. Clock Signal Waveform for ICC Tests in Active and Idle Modes

IDS

ODS

VCC–0.5

0.45V

SU00093

0.2VCC–0.1

CHCL

0.7V

CLCH

= t

CLCX

CHCL

= 5ns

(NC)

CLOCK SIGNAL

Figure 15. ICC Test Condition, Idle Mode

CHCX

CLCH

CLCL

80C451/83C451/87C451

RST

XTAL2

XTAL1

IDS

ODS

All other pins are disconnected

SU00009

SU00094

IDS

ODS

P0 EA

SU00095

(NC)

RST

XTAL2

XTAL1

Figure 17. ICC Test Condition, Power Down Mode

All other pins are disconnected. V

= 2V to 5.5V

1998 May 01

Page 18

Philips Semiconductors Product specification

80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

EPROM CHARACTERISTICS

The 87C451 is programmed by using a modified Quick-Pulse Programming algorithm. It differs from older methods in the value used for V number of the ALE/PROG

The 87C451 contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an 87C451 manufactured by Philips Semiconductors.

Table 4 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the lock bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 18 and 19. Figure 20 shows the circuit configuration for normal program memory verification.

Quick-Pulse Programming

The setup for microcontroller quick-pulse programming is shown in Figure 18. Note that the 87C451 is running with a 4 to 6MHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers.

The address of the EPROM location to be programmed is applied to ports 1 and 2, as shown in Figure 18. The code byte to be programmed into that location is applied to port 0. RST, PSEN pins of ports 2 and 3 specified in Table 4 are held at the ‘Program Code Data’ levels indicated in Table 4. The ALE/PROG low 25 times as shown in Figure 19.

To program the encryption table, repeat the 25 pulse programming sequence for addresses 0 through 1FH, using the ‘Pgm Encryption Table’ levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data.

To program the lock bits, repeat the 25 pulse programming sequence using the ‘Pgm Lock Bit’ levels. After one lock bit is

(programming supply voltage) and in the width and

pulses.

is pulsed

and

80C451/83C451/87C451

programmed, further programming of the code memory and encryption table is disabled. However, the other lock bit can still be programmed.

Note that the EA maximum specified V glitch above that voltage can cause permanent damage to the device. The V and overshoot.

Program Verification

If lock bit 2 has not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory locations to be read is applied to ports 1 and 2 as shown in Figure 20. The other pins are held at the ‘Verify Code Data’ levels indicated in Table 4. The contents of the address location will be emitted on port 0. External pull-ups are required on port 0 for this operation.

If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out.

Reading the Signature Bytes

The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 need to be pulled to a logic low. The values are: (030H) = 15H indicates manufactured by Philips (031H) = 90H indicates 87C451

Program/Verify Algorithms

Any algorithm in agreement with the conditions listed in Table 4, and which satisfies the timing specifications, is suitable.

/VPP pin must not be allowed to go above the

level for any amount of time. Even a narrow

source should be well regulated and free of glitches

Table 4. EPROM Programming Modes

MODE RST PSEN ALE/PROG EA/V

Read signature 1 0 1 1 0 0 0 0 Program code data 1 0 0* V Verify code data 1 0 1 1 0 0 1 1 Pgm encryption table 1 0 0* V Pgm lock bit 1 1 0 0* V Pgm lock bit 2 1 0 0* V

NOTES:

1. ‘0’ = Valid low for that pin, ‘1’ = valid high for that pin.

2. VPP = 12.75V ±0.25V. = 5V ±10% during programming and verification.

3. V

* ALE/PROG

minimum of 10µs.

Trademark phrase of Intel Corporation.

receives 25 programming pulses while VPP is held at 12.75V . Each programming pulse is low for 100 µs (±10µs) and high for a

PP PP PP

P2.7 P2.6 P3.7 P3.6

1 0 1 1

1 0 1 0 1 1 1 1 1 1 0 0

1998 May 01

Page 19

Philips Semiconductors Product specification

80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

A0–A7

1 1 1

4–6MHz

RST P3.6

P3.7 XTAL2

XTAL1

87C451

Figure 18. Programming Configuration

ALE/PROG

PSEN

P2.7

P2.6

P2.0–P2.4

80C451/83C451/87C451

+5V

PGM DATA

+12.75V 25 100µs PULSES TO GROUND 0 1

A8–A12

SU00096

ALE/PROG:

1 0

4–6MHz

25 PULSES

1 0

100µs+1010µs MIN

SU00018

Figure 19. PROG Waveform

+5V

ALE/PROG

PSEN

P2.7

P2.6

P2.0–P2.4

PGM DATA

1 1 0 0 ENABLE

A8–A12

A0–A7

1 1 1

RST P3.6

P3.7 XTAL2

XTAL1

87C451

1998 May 01

Figure 20. Program Verification

SU00097

Page 20

Philips Semiconductors Product specification

80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS

= 21°C to +27°C, VCC = 5V±10%, VSS = 0V (See Figure 21)

amb

SYMBOL

1/t

CLCL

AVGL

GHAX

DVGL

GHDX

EHSH

SHGL

GHSL

GLGH

AVQV

ELQZ

EHQZ

GHGL

Programming supply voltage 12.5 13.0 V Programming supply current 50 mA Oscillator frequency 4 6 MHz Address setup to PROG low 48t Address hold after PROG 48t Data setup to PROG low 48t Data hold after PROG 48t P2.7 (ENABLE) high to V VPP setup to PROG low 10 µs VPP hold after PROG 10 µs PROG width 90 110 µs Address to data valid 48t ENABLE low to data valid 48t Data float after ENABLE 0 48t PROG high to PROG low 10 µs

PARAMETER MIN MAX UNIT

80C451/83C451/87C451

CLCL CLCL CLCL CLCL

48t

CLCL

CLCL CLCL CLCL

P1.0–P1.7 P2.0–P2.4

PORT 0

DVGL

ALE/PROG

EA/V

P2.7 ENABLE

AVGL

EHSH

GLGH

SHGL

NOTE:

FOR PROGRAMMING VERIFICATION SEE FIGURE 18. FOR VERIFICATION CONDITIONS SEE FIGURE 20.

PROGRAMMING* VERIFICATION*

ADDRESS ADDRESS

AVQV

DATA IN DATA OUT

GHDX

GHAX

GHGL

LOGIC 0

GHSL

LOGIC 1 LOGIC 1

ELQV

Figure 21. EPROM Programming and Verification

EHQZ

SU00020

1998 May 01

Page 21

Philips Semiconductors Product specification

80C51 8-bit microcontroller family

80C451/83C451/87C451

4K/128 OTP/ROM/ROMless, expanded I/O

PLCC68: plastic leaded chip carrier; 68 leads; pedestal SOT188-3

1998 May 01

Page 22

Philips Semiconductors Product specification

80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O

Data sheet status

Objective specification

Preliminary specification

Product specification

Product status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

[1]

80C451/83C451/87C451

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

 Copyright Philips Electronics North America Corporation 1998

Date of release: 05-98

Document order number: 9397 75003857

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1998 May 01