Datasheet 82C86H Datasheet (Intersil Corporation)

82C86H

March 1997

Features

• Full Eight Bit Bi-Directional Bus Interface

• Industry Standard 8286 Compatible Pinout

• High Drive Capability

- B Side I

- A Side I

• Three-State Outputs

• Propagation Delay . . . . . . . . . . . . . . . . . . . . . 35ns Max.

• Gated Inputs

- Reduce Operating Power

- Eliminate the Need for Pull-Up Resistors

• Single 5V Power Supply

• Low Power Operation . . . . . . . . . . . . . . . ICCSB = 10µA

• Operating Temperature Range

- C82C86H . . . . . . . . . . . . . . . . . . . . . . . . . 0

- I82C86H. . . . . . . . . . . . . . . . . . . . . . . . -40

- M82C86H. . . . . . . . . . . . . . . . . . . . . . -55

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA

OL

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12mA

OL

o

C to +70oC

o

C to +85oC

o

C to +125oC

CMOS Octal Bus Transceiver

Description

The Intersil 82C86H is a high performance CMOS Octal
Transceiver manufactured using a self-aligned silicon gate
CMOS process (Scaled SAJI IV). The 82C86H provides a full
eight-bit bi-directional bus interface in a 20 lead package. The
Transmit (T) control determines the data direction. The active
low output enable (
80C88 and other microprocessors. The 82C86H has gated
inputs, eliminating the need for pull-up/pull-down resistors and
reducing overall system operating power dissipation.

Ordering Information

PART NUMBER

CP82C86H-5 CP82C86H 20 Ld
IP82C86H-5 IP82C86H -40oC to +85oC E20.3
CS82C86H-5 CS82C86H 20 Ld
IS82C86H-5 IS82C86H -40oC to +85oC N20.35
CD82C86H-5 CD82C86H 20 Ld

ID82C86H-5 ID82C86H -40oC to +85oC F20.3
MD82C86H-5/B - -55oC to

5962­8757701RA

MR82C86H-5/B - 20 Pad

5962­87577012A

OE) permits simple interface to the 80C86,

PACK-

AGE TEMP. RANGE

0oC to +70oC E20.3

PDIP

0oC to +70oC N20.35

PLCC

0oC to +70oC F20.3

CERDIP

+125oC

- SMD # F20.3

-55oC to

CLCC

- SMD # J20.A

+125oC

PKG.

NO.5MHz 8MHz

F20.3

J20.A

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207

| Copyright © Intersil Corporation 1999

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File Number 2977.1

Pinouts

82C86H82C86H

82C86H (PDIP, CERDIP)

TOP VIEW

1

A

0

2

A

1

3

A

2

4

A

3

5

A

4

6

A

5

A

7

6

8

A

7

9

OE

10

GND

82C86H (PLCC, CLCC)

TOP VIEW

20

V

CC

B

19

0

18

B

1

17

B

2

16

B

3

15

B

4

14

B

5

13

B

6

12

B

7

T

11

4

A

3

A

5

4

6

A

5

A

7

6

A

8

7

A2A1A

9

OE

0

10 11 12 13

T

GND

CC

V

7B6

B

0

B

193 2 201

H = Logic One

18
17
16
15
14

L = Logic Zero

B

1

I = Input Mode

B

2

O = Output Mode
X = Don’t Care

B

3

Hi-Z = High Impedance

B

4

B

5

PIN DESCRIPTION

A

0-A7

B

0-B7

TRUTH TABLE

T

OE A B

X H Hi-Z Hi-Z
HL IO
LLOI

PIN NAMES

Local Bus Data I/O Pins
System Bus Data I/O Pins

T Transmit Control Input

OE Active Low Output Enable

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82C86H

82C86H

Functional Diagram

A0

B0

A1

A2

A3

A4

A5

A6

A7

OE

B1

B2

B3

B4

B5

B6

B7

T

Gated Inputs

During normal system operation of a latch, signals on the
bus at the device inputs will become high impedance or
make transitions unrelated to the operation of the latch.
These unrelated input transitions switch the input circuitry
and typically cause an increase in power dissipation in
CMOS devices by creating a low resistance path between
V

and GND when the signal is at or near the input switch-

CC

ing threshold. Additionally, if the driving signal becomes high
impedance (“float” condition), it could create an indetermi­nate logic state at the inputs and cause a disruption in
device operation.

The Intersil 82C8X series of bus drivers eliminates these
conditions by turning off data inputs when data is latched
(STB = logic zero for the 82C82/83H) and when the de vice is
disabled (
inputs disconnect the input circuitry from the V
ground power supply pins by turning off the upper P-channel
and lower N-channel (See Figures 1 and 2). No current flow
from V
logic states from floating inputs are not transmitted. The next
stage is held to a valid logic level internal to the device.

D.C. input voltage levels can also cause an increase in ICC if
these input levels approach the minimum V
V

IL

cuitry in its linear operating region (partially conducting
state). The 82C8X series gated inputs mean that this condi­tion will occur only during the time the device is in the trans­parent mode (STB = logic one). ICC remains below the
maximum ICC standby specification of 10µA during the time
inputs are disabled, thereby greatly reducing the average
power dissipation of the 82C8X series devices.

OE = logic one for the 82C86H/87H). These gated

and

CC

to GND occurs during input transitions and invalid

CC

or maximum

IH

conditions. This is due to the operation of the input cir-

Decoupling Capacitors

The transient current required to charge and discharge the
300pF load capacitance specified in the 82C86H/87H data
sheet is determined by:

ICLdv dt⁄()=

Assuming that all outputs change state at the same time and
that dv/dt is constant;

VCC 80%×()

------------------------------------ -

=

IC

L

tR tF⁄

where tR = 20ns, V

= 5.0V, CL = 300pF on each eight out-

CC

puts.

12–

I 80 300 10

480mA=

DATA IN

DATA IN

××()5.0V 0.8×()20 109–×()⁄×=

V

CC

P

STB

OE

FIGURE 2. 82C86H/87H GATED INPUTS

N

FIGURE 1. 82C82/83H

V

CC

P

N

V

CC

P

P

N

N

V

CC

P

P

N

N

This current spike may cause a large negative voltage spike
on V

which could cause improper operation of the device.

CC

To filter out this noise, it is recommended that a 0.1µF
ceramic disc capacitor be placed between V

CC

each device, with placement being as near to the device as
possible.

(EQ. 1)

(EQ. 2)

(EQ. 3)

INTERNAL
DAT A

INTERNAL
DAT A

and GND at

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82C86H82C86H

Absolute Maximum Ratings Thermal Information

Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V

Input, Output or I/O Voltage . . . . . . . . . . . .GND -0.5V to VCC+0.5V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

Operating Conditions

Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V

Operating Temperature Range

C82C86H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0oC to +70oC

I82C86H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC

M82C86H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

Thermal Resistance (Typical) θJA (oC/W) θJC (oC/W)

CERDIP Package . . . . . . . . . . . . . . . . 70 16

CLCC Package . . . . . . . . . . . . . . . . . . 80 20

PDIP Package. . . . . . . . . . . . . . . . . . . 75 N/A

PLCC Package . . . . . . . . . . . . . . . . . . 75 N/A

Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC

Maximum Junction Temperature Hermetic Package. . . . . . . +175oC

Maximum Junction Temperature Plastic Package. . . . . . . . . +150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC

(PLCC - Lead Tips Only)

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 Gates

DC Electrical Specifications V

SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS

V

V

V

OH

V

OL

I

IO Output Leakage Current -10.0 10.0 µA VO = GND or VCC, OE ≥ VCC -0.5V

ICCSB Standby Power Supply

ICCOP Operating Power Supply

NOTES:

1. VIH is measured by applying a pulse of magnitude = V
a valid logical “1” during valid input high time. Control pins (T, OE) are tested separately with all device data input pins at VCC -0.4

2. Typical ICCOP = 1mA/MHz of read/ cycle time. (Example: 1.0µs read/write cycle time = 1mA).

Logical One 2.0 - V C82C86H, I82C86H

IH

Input Voltage 2.2 V M82C86H (Note 1)

Logical Zero Input Voltage - 0.8 V

IL

Logical One Output Voltage

B Outputs 3.0 V IOH = -8mA
A Outputs 3.0 V IOH = -4mA
A or B Outputs VCC -0.4 V IOH = -100µA

Logical Zero Output Voltage

B Outputs 0.45 V IOL = 20mA
A Outputs 0.45 V IOL = 12mA

Input Leakage Current -10.0 10.0 µAVIN = GND or VCC DIP Pins 9, 11

I

Current

Current

= 5.0V ± 10%; TA = 0oC to +70oC (C82C86H);

CC

TA = -40oC to +85oC (I82C86H);
TA = -55oC to +125oC (M82C86H)

-10µAVIN = VCC or GND, VCC = 5.5V, Outputs Open

- 1 mA/MHz TA = +25oC, Typical (See Note 2)

to one data input at a time and checking the corresponding device output for

IH(MIN)

DIP Pins 1 - 8, 12 - 19

Capacitance T

SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS

CIN Input Capacitance

= +25oC

A

B Inputs 18 pF Freq = 1MHz, all measurements are
A Inputs 14 pF

referenced to device GND

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82C86H82C86H

AC Electrical Specifications V

= 5.0V ± 10%; TA = 0oC to +70oC (C82C86H);

CC

Freq = 1MHz TA = -40oC to +85oC (I82C86H);

TA = -55oC to +125oC (M82C86H)

NOTE 4

SYMBOL PARAMETER MIN

82C86H

MAX

82C86H-5

MAX

UNITS TEST CONDITIONS

(1) TIVOV Input to Output Delay Notes 1, 2

Inverting 5 30 35 ns

Non-Inverting 5 32 35 ns

(2) TEHTV Transmit/Receive Hold Time 5 - - ns Notes 1, 2

(3) TTVEL Transmit/Receive Setup Time 10 - - ns Notes 1, 2

(4) TEHOZ Output Disable Time 5 30 35 ns Notes 1, 2

(5) TELOV Output Enable Time 10 50 65 ns Notes 1, 2

(6) TR, TF Input Rise/Fall Times - 20 20 ns Notes 1, 2

(7) TEHEL Minimum Output Enable High Time Note 3

82C86H 30 - - ns

82C86H-5 35 - - ns

NOTES:

1. All AC parameters tested as per test circuits and definitions in timing wavef orms and test load circuits. Input rise and fall times are driven
at 1ns/V.

2. Input test signals must switch between VIL - 0.4V and VIH +0.4V.

3. A system limitation only when changing direction. Not a measured parameter.

4. 82C86H is available in commercial and industrial temperature ranges only. 82C86H-5 is available in commercial, industrial and military
temperature ranges.

Timing Waveform

TR, TF (6)

INPUTS

OE

OUTPUTS

T

2.0V

0.8V

(1)

TIVOV

(4)

TEHOZ

TEHEL (7)

VOH -0.1V
VOL +0.1V

TEHTV (2)

TELOV (5)

3.0V

0.45V

TTVEL (3)

NOTE: All timing measurements are made at 1.5V unless otherwise noted.

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Test Load Circuits

TIVOV LOAD CIRCUIT

A SIDE OUTPUTS

TELOV OUTPUT HIGH

ENABLE LOAD CIRCUIT

82C86H82C86H

TELOV OUTPUT LOW

ENABLE LOAD CIRCUIT

TEHOZ OUTPUT LOW/HIGH

DISABLE LOAD CIRCUIT

2.36V

160Ω

OUTPUT

100pF

(SEE NOTE)

TIVOV LOAD CIRCUIT

2.27V

91Ω

OUTPUT

300pF

(SEE NOTE)

TEST
POINT

TEST
POINT

OUTPUT

(SEE NOTE)

ENABLE LOAD CIRCUIT

OUTPUT

(SEE NOTE)

NOTE: Includes jig and stray capacitance.

1.5V

375Ω

TEST

100pF

POINT

B SIDE OUTPUTS

TELOV OUTPUT HIGH

1.5V

180Ω

TEST

300pF

POINT

1.5V

91Ω

OUTPUT

100pF

(SEE NOTE)

TEST
POINT

TELOV OUTPUT LOW

ENABLE LOAD CIRCUIT

1.5V

51Ω

OUTPUT

300pF

(SEE NOTE)

TEST
POINT

2.36V

160Ω

OUTPUT

50pF

(SEE NOTE)

TEST
POINT

TEHOZ OUTPUT LOW/HIGH

DISABLE LOAD CIRCUIT

2.27V

91Ω

OUTPUT

50pF

(SEE NOTE)

TEST
POINT

Burn-In Circuits

F2
F2
F2
F2
F2
F2
F2
F2

R1
R1
R1
R1
R1
R1
R1
R1
R1

MD82C86H CERDIP

V

CC

R1

C1

A
A
A
A
A
A
A
A
V

CC

V

CC

R2

A

R3

1
2
3
4
5
6
7
8

9

10

20
19
18
17
16
15
14
13
12

11

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82C86H82C86H

Burn-In Circuits

(Continued)

R5

F2

R5

F2

R5

F2

R5

F2

R5

F2

MR82C86H CLCC

V

CC

R5

F2

R5

F2

R5

R4R4 R5R5

F1F0 F3

F2

3212019

4

5

6

7

8

9101112

F3

13

F3

R5

C1

R5

18

R5

17

R5

16

R5

15

R5

14

F3

F3

F3

F3

F3

NOTES:

1. VCC = 5.5V ± 0.5V, GND = 0V

2. VIH = 4.5V ± 10%

3. VIL = -0.2V to 0.4V

4. R1 = 47kΩ± 5%

5. R2 = 2.4kΩ± 5%

6. R3 = 1.5kΩ± 5%

7. R4 = 1kΩ± 5%

8. R5 = 5kΩ± 5%

9. C1 = 0.01µF minimum

10. F0 = 100kHz ± 10%

11. F1 = F0/2, F2 = F1/2, F3 = F2/2

4-323

Die Characteristics

82C86H82C86H

DIE DIMENSIONS:

138.6 x 155.5 x 19 ± 1mils

METALLIZATION:

Type: Si - Al
Thickness: 11k

Å ± 1kÅ

Metallization Mask Layout

A2 A1 A0 V

GLASSIVATION:

Type: SiO

2

Thickness: 8kű 1kÅ

WORST CASE CURRENT DENSITY:

1.47 x 10

82C86H

CC

5

A/cm

2

B0 B1

B2

A3

A4

A5

A6

B3

B4

B5

B6B7TGNDOEA7

All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.

Intersil products are sold by description only. Intersil Corporation reser ves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.

For information regarding Intersil Corporation and its products, see web site http://www.intersil.com

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