Page 1
82C83H
March 1997
Features
• Full 8-Bit Parallel Latching Buffer
• Bipolar 8283 Compatible
• Three-State Inverting Outputs
• Propagation Delay . . . . . . . . . . . . . . . . . . . . . .25ns Max
• Gated Inputs
- Reduce Operating Power
- Eliminate the Need for Pull-Up Resistors
• Single 5V Power Supply
• Low Power Operation
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
• Operating Temperature Ranges
- C82C83H . . . . . . . . . . . . . . . . . . . . . . . . .0
- I82C83H. . . . . . . . . . . . . . . . . . . . . . . . -40
- M82C83H. . . . . . . . . . . . . . . . . . . . . . -55
o
C to +70oC
o
C to +85oC
o
C to +125oC
CMOS Octal Latching Inverting Bus Driver
Description
The Intersil 82C83H is a high performance CMOS Octal
Latching Buffer manufactured using a self-aligned silicon gate
CMOS process (Scaled SAJI IV). The 82C83H provides an 8bit parallel latch/buffer in a 20 lead pin package. The active
high strobe (STB) input allows transparent transfer of data
and latches data on the negative transition of this signal. The
active low output enable (OE) permits simple interface to
microprocessor systems. The 82C83H provides inverted data
at the outputs.
Ordering Information
PART NO. PACKAGE TEMP RANGE PKG. NO
CP82C83H 20 Ld PDIP 0
IP82C83H -40
CS82C83H 20 Ld PLCC 0
IS82C83H -40
CD82C83H 20 Ld CERDIP 0
ID82C83H -40
MD82C83H/B 0
8406702RA SMD# -55
MR82C83H/B 20 Pad CLCC -55
84067022A SMD# -55
o
C to +70oC E20.3
o
C to +85oC E20.3
o
C to +70oC N20.35
o
C to +85oC N20.35
o
C to +70oC F20.3
o
C to +85oC F20.3
o
C to +70oC F20.3
o
C to +125oC F20.3
o
C to +125oC J20.A
o
C to +125oC J20.A
Pinouts
82C83H (PDIP, CERDIP)
TOP VIEW
1
DI
0
DI
2
1
DI
3
2
DI
4
3
DI
5
4
DI
6
5
DI
7
6
8
DI
7
9
OE
GND
10
TRUTH TABLE
STB OE DI DO
X H X HI-Z
HLLH
HLHL
↓ LX†
H = Logic One
L = Logic Zero
X = Don‘t Care
HI-Z = High Impedance
↓ = Negative Transition
† = Latched to Value of Last
20
19
18
17
16
15
14
13
12
11
V
DO
DO
DO
DO
DO
DO
DO
DO
STB
Data
CC
0
1
2
3
4
5
6
7
82C83H (PLCC, CLCC)
TOP VIEW
DI2DI1DI0VCCDO
4
DI
3
DI
5
4
6
DI
5
DI
7
6
DI
8
7
9
10 11 12 13
OE
GND
STB
DO7DO
PIN NAMES
PIN DESCRIPTION
DI0 - DI
7
DO0 - DO
Data Input Pins
Data Output Pins
7
STB Active High Strobe
OE Active Low Output Enable
0
193 2 201
18
DO
1
17
DO
2
16
DO
3
15
DO
4
DO
14
5
6
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
4-281
File Number 2971.1
Page 2
82C83H
Functional Diagram
DI0
DI1
DI2
DI3
DI4
DI5
DI6
DI7
STB
DQ
CLK
Gated Inputs
During normal system operation of a latch, signals on the
bus at the device inputs will become high impedance or
make transitions unrelated to the operation of the latch.
These unrelated input transitions switch the input circuitry
and typically cause an increase in power dissipation in
CMOS devices by creating a low resistance path between
V
and GND when the signal is at or near the input switch-
CC
ing threshold. Additionally, if the driving signal becomes high
impedance (``float'' condition), it could create an indeterminate logic state at the inputs and cause a disruption in
device operation.
The Intersil 82C8X series of bus drivers eliminates these
conditions by turning off data inputs when data is latched
(STB = logic zero for the 82C82/83H) and when the de vice is
disabled (
OE = logic one for the 82C86H/87H). These gated
inputs disconnect the input circuitry from the V
ground power supply pins by turning off the upper P-channel
and lower N-channel (See Figures 1 and 2). No current flow
from V
to GND occurs during input transitions and invalid
CC
logic states from floating inputs are not transmitted. The next
stage is held to a valid logic level internal to the device.
STB
DATA IN
V
CC
P
N
FIGURE 1. 82C82/83H
V
P
P
N
N
D.C. input voltage le vels can also cause an increase in ICC if
these input levels approach the minimum V
V
conditions. This is due to the operation of the input cir-
IL
cuitry in its linear operating region (partially conducting
CC
DO0
DO1
DO2
DO3
DO4
DO5
DO6
DO7
OE
CC
INTERNAL
DAT A
or maximum
IH
and
state). The 82C8X series gated inputs mean that this condition will occur only during the time the device is in the transparent mode (STB = logic one). ICC remains below the
maximum ICC standby specification of 10µA during the time
inputs are disabled, thereby greatly reducing the average
power dissipation of the 82C8X series devices.
V
CC
P
OE
DATA IN
V
CC
P
N
P
N
N
INTERNAL
DAT A
FIGURE 2. 82C86H/87H GATED INPUTS
Decoupling Capacitors
The transient current required to charge and discharge the
300pF load capacitance specified in the 82C83H data sheet
is determined by
I = C
(dv/dt)
L
Assuming that all outputs change state at the same time and
that dv/dt is constant;
V
80 percent×()
CC
--------------------------------------------------------
IC
=
L
where t
R
⁄
t
RtF
= 20ns, VCC = 5.0V, CL = 300pF on each eight out-
puts.
I = (8 x 300 x 10
-12
) x (5.0V x 0.8)/(20 x 10-9) = 480mA
This current spike may cause a large negative voltage spike on
V
which could cause improper operation of the device. To fil-
CC
ter out this noise, it is recommended that a 0.1µF ceramic disc
capacitor be placed between V
and GND at each device,
CC
with placement being as near to the device as possible.
ALE
MULTI-
PLEXED
BUS
ICC
DATA IN
FIGURE 3. SYSTEM EFFECTS OF GATED INPUTS
ADDRESS ADDRESS
STB
V
CC
P
N
V
CC
P
P
N
N
INTERNAL
DAT A
(EQ. 1)
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Page 3
82C83H
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V
Input, Output or I/O Voltage . . . . . . . . . . . . GND 0.5V to VCC +0.5V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance (Typical) θ
CERDIP Package . . . . . . . . . . . . . . . . 70 16
CLCC Package . . . . . . . . . . . . . . . . . . 80 20
o
C/W θ
JA
PDIP Package. . . . . . . . . . . . . . . . . . . 75 N/A
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
C82C83H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to +70oC
I82C83H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to +85oC
PLCC Package . . . . . . . . . . . . . . . . . . 75 N/A
Storage Temperature Range. . . . . . . . . . . . . . . . . .-65oC to +150oC
Max Junction Temperature Ceramic Package . . . . . . . . . . . . . . +175oC
Max Junction Temperature Plastic Package. . . . . . . . . . . . . . . . +150oC
Lead Temperature (Soldering 10s) (PLCC - Lead Tips Only). . +300oC
M82C83H . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55oC to +125oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .265 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
JC
o
C/W
DC Electrical Specifications V
= 5.0V ± 10%; TA = 0oC to +70oC (C82C83H);
CC
TA = -40oC to +85oC (I82C83H);
TA = -55oC to +125oC (M82C83H)
SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS
V
IH
V
IL
V
OH
V
OL
I
I
Logical One Input Voltage 2.0
2.2
- V C82C83H, I82C83H,
M82C83H, (Note 1)
Logical Zero Input Voltage 0.8 V
Logical One Output Voltage 3.0
VCC -0.4V
-VI
OH
= -8mA,
IOH = -100mA, OE = GND
Logical Zero Output Voltage 0.45 V IOL = 20mA, OE = GND
Input Leakage Current -10 10 µAV
= GND or VCC,
IN
DIP Pins 1-9,11
I
O
Output Leakage Current -10 10 µAV
= GND or OE ≥ VCC -0.5V
O
DIP Pins 12-19
lCCSB Standby Power Supply Current - 10 µAV
= VCC or GND
IN
VCC = 5.5V Outputs Open
IC COP Operating Power Supply Current - 1 mA/
MHz
TA = +25oC, VCC = 5V, Typical
(See Note 2)
NOTES:
1. VIH is measured by applying a pulse of magnitude = V
to one data Input at a time and checking the corresponding device output for
lHMIN
a valid logical 1 - during valid input high time. Control pins (STB, CE) are tested separately with all device data input pins at VCC -0.4V.
2. Typical ICCOP = 1 mA/MHz of STB cycle time. (Example: 5MHz µP, ALE = 1.25MHz, ICCOP = 1.25mA).
Capacitance T
= +25oC
A
SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS
C
IN
Input Capacitance 13 pF FREQ = 1MHz, all measure-
ments are referenced to device
C
OUT
Output Capacitance 20 pF
GND
4-283
Page 4
82C83H
AC Electrical Specifications V
= 5.0V ±10%; CL= 300pF (Note 1), FREQ = 1MHz
CC
TA = 0oC to +70oC (C82C83H);
TA = -40oC to +85oC (l82C83H);
TA = -55oC to +125oC (M82C83H)
LIMITS
SYMBOL PARAMETER
UNITS TEST CONDITIONSMIN MAX
(1) TlVOV Propagation Delay Input to Output 5 25 ns See Notes 2, 3
(2) TSHOV Propagation Delay STB to Output 10 50 ns See Notes 2, 3
(3) TEHOZ Output Disable Time 5 22 ns See Notes 2, 3
(4) TELOV Output Enable Time 10 45 ns See Notes 2, 3
(5) TlVSL Input to STB Set Up Time 0 - ns See Notes 2, 3
(6) TSLIX Input to STB Hold Time 30 - ns See Notes 2, 3
(7) TSHSL STB High Time 15 - ns See Notes 2, 3
(8) TR, TF Input Rise/Fall Times - 20 ns See Notes 2, 3
NOTES:
1. Output load capacitance is rated 300pF for both ceramic and plastic packages.
2. All AC Parameters tested as per test load circuits. Input rise and tall times are driven at 1ns/V.
3. Input test signals must switch between VIL -0.4V and VlH +0.4V.
Timing Waveforms
TR, TF (8)
INPUTS
STB
OE
OUTPUTS
2.0V
0.8V
TIVSL (5)
TSHSL (7)
TIVOV
(1)
TSHOV (2)
TSLIX
(6)
TEHOZ (3)
All Timing measurements are made at 1.5V unless otherwise noted.
FIGURE 4. TIMING WAVEFORMS
Test Load Circuits
2.27V
91Ω
OUTPUT
TEST
POINT
300pF
(SEE NOTE)
VOH -0.1V
VOL +0.1V
OUTPUT
1.5V
TELOV (4)
3.0V
0.45V
180Ω
TEST
POINT
300pF
(SEE NOTE)
FIGURE 5. TIVOV, TSHOV FIGURE 6. TELOV OUTPUT HIGH ENABLE
4-284
Page 5
82C83H
Test Load Circuits
OUTPUT
(Continued)
1.5V
51Ω
300pF
(SEE NOTE)
NOTE: Includes jig and stray capacitance.
FIGURE 7. TELOV OUTPUT LOW ENABLE
Burn-In Circuits
R1
F2
F2
F2
F2
F2
F2
F2
F2
F0
R1
R1
R1
R1
R1
R1
R1
R1
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
2.27V
91Ω
TEST
POINT
OUTPUT
TEST
POINT
50pF
(SEE NOTE)
FIGURE 8. TEHOZ OUTPUT LOW/HIGH DISABLE
V
CC
C1
2
CC
V
F2
F2
F2
V
CC
R1
C1
A
A
A
A
A
A
A
A
F1
R4
F2
R4
V
CC
R2
A
R2
F2
F2
F2
F2
R4
R4
R4
R4
R4R4R4
3212019
4
5
6
7
8
9101112
18
17
16
15
14
13
R4
R4
R4
R4
R4
V
CC
2
FIGURE 9. MD82C83H CERDIP
NOTES:
1. V
= 5.5V ± 0.5V GND = 0V
CC
2. VIH = 4.5V ± 10%
3. VIL = -0.2 to 0.4V
4. R1 = 47kW ±5%
5. R2 = 2.0kW ±5%
6. R3 = 1.0kW ±5%
7. R4 = 5.0kW ±5%
8. C1 = 0.01µF Minimum
9. F0 = 100kHz ±10%
10. F1 = F0/2, F2 = F1/2, F3 = F2/2
4-285
R3
F0
R3R4R4
F1
CC
V
2
FIGURE 10. MR82C83H CLCC
Page 6
Die Characteristics
82C83H
DIE DIMENSIONS:
138.6 x 155.5 x 19 ± 1 mils
METALLIZATION:
Type: Silicon - Aluminum
Thickness: 11k
Å ± 2kÅ
Metallization Mask Layout
DI2 DI1 DI2 VCC DO0
GLASSIVATION:
Type: SiO
2
Thickness: 8kű 1kÅ
WORST CASE CURRENT DENSITY:
2.0 x 10
82C83H
5
A/cm
2
DO1
DO2
DI3
DI4
DI5
DI6
DO3
DO4
DO5
DO6DO7STBGNDOEDI7
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see web site http://www.intersil.com
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