Datasheet 82443BX Datasheet (Standard Microsystems Corporation)

Download

Page 1

Intel® 440BX AGPset: 82443BX Host Bridge/Controller

Datasheet

April 1998

Order Number: 290633-001

Page 2

Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, cop yright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. The 82443BX chipset may contain design defects or errors known as errata which may cause the product to deviate from published specifications.

Current characterized errata are available upon request.

C is a two-wire communications bus/protocol developed by Philips. SMBus is a subset of the I2C bus/protocol and was developed by Intel. Implementations of the I North American Philips Corporation.

Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by:

calling 1-800-548-4725 or

C bus/protocol or the SMBus bus/protocol may require licenses from various entities, including Philips Electronics N.V. and

82443BX Host Bridge

Datasheet

Page 3

Intel 82443BX Features

Processor/host bus support

•

— Optimized for Pentium

processor at 100 MHz system bus frequency; Support for 66 MHz

— Supports full symmetric

Multiprocessor (SMP) Protocol for up to two processors; I/O APIC related buffer management support (WSC# signal)

— In-order transaction and dynamic

deferred transaction support

— Desktop optimized GTL+ bus driv er

technology (gated GTL+ receivers for reduced power)

Integrated DRAM controller

•

— 8 to 512 Mbytes or 1G B (with

registered DIMMs)

— Supports up to 4 double-sided

DIMMs (8 rows memory)

— 64-bit data interface with ECC

support (SDRAM only)

— Unbuffered and Registered

SDRAM (Synchronous) DRAM Support (x-1-1-1 access @ 66 MHz, x-1-1-1 access @ 100 MHz)

— Enhanced SDRAM Open Page

Architecture Support for 16- and 64-Mbit DRAM devi ces with 2k, 4k and 8k page sizes

PCI bus interface

•

— PCI Rev. 2.1, 3.3V and 5V, 33MHz

interface compliant — PCI Parity Generation Support — Data streaming support from PCI to

DRAM — Delayed Transaction support for

PCI-DRAM Reads — Supports concurrent CPU, AGP and

PCI transactions to main memory

AGP interface

•

— Supports single AGP compliant

device (AGP-66/133 3.3V device)

— AGP Specification Rev 1.0

compliant

— AGP-data/transaction flow

optimized arbitration mechanism

— AGP side-band interface for ef fi cient

request pipelining without

interfering with the data streams — AGP-specific data buffering — Supports concurrent CPU, AGP and

PCI transactions to main memory — AGP high-priority transactions

(“expedite”) support

Power Management Functions

•

— Stop Clock Grant and Halt special

cycle translation (host to PCI Bus) — Mobile and “Deep Green” Desktop

support for system suspend/resume

(i.e., DRAM and power-on suspend) — Dynamic power do wn of idle DRAM

rows — SDRAM self-refresh power down

support in suspend mode — Independent, internal dynam ic cl ock

gating reduces average power

dissipation — Static STOP CLOCK support — Power-on Suspend mode — Suspend to DRAM — ACPI compliant power management

Packaging/Voltage

•

—492 Pin BGA — 3.3V core and mixed 3. 3V and GTL

I/O

Supporting I/O Bridge

•

— System Management Bus (SMB)

with support for DIMM Serial

Presence Detect (SPD) — PCI-ISA Bridge (PIIX4E) — Power Management Support — 3.3V core and mixed 5V, 3.3V I/O

and interface to the 2.5V CPU

signals via open-drain output buffers

82443BX Host Bridge

The Intel® 440BX AGPset is intended for the Pentium® II processor platform and emerging 3D graphics/multimedia applications. The 82443BX Host Bridge provides a Host-to-PCI bridge, optimized DRAM controller and data path, and an Accelerated Graphic Port (AGP) interface. AGP is a high performance, component level interconnect targeted at 3D graphics applications and is based on a set of performance enhancements to PCI.

The Intel 82443BX may contain design defects or errors known as errata which may cause the products to deviate from published specifications. Current characterized errata are available on request.

Datasheet

iii

Page 4

The I/O subsystem portion o f the Intel® 440BX AGPset platform is based on the 82371EB (PIIX4E), a highly integrated version of the Intel’s PCI-ISA bridge family. The Intel AGPset is ideal for the Mobile AGPset Pentium II processor platforms; providing full support for all system suspend modes and segmented power planes.

Intel 82443BX Simplified Block Diagram

440BX

A[31:3]#

ADS#

BPRI#

BNR#

CPURST#

DBSY#

DEFER#

HD[63:0]#

HIT#

HITM#

HLOCK#

HREQ[4:0]#

HTRDY#

DRDY#

RS[2:0]#

RASA[5:0]/CSA[5:0]# RASB[5:0]/CSB[5:0]#

CKE[3:2]/CSA[7:6]#

CKE[5:4]/CSB[7:6]# CASA[7:0]/DQMA[7:0] CASB[5,1]/DQMB[5,1]

GCKE/CKE1

SRAS[B,A]# CKE0/FENA SCAS[B,A]#

MAA[13:0]

MAB[13,12#,11#,10,9#:0#]

WEA# WEB#

MD[63:0]

MECC[7:0]

HCLKIN PCLKIN

GTLREF[B:A]

AGPREF VTT[B:A]

REF5V

PCIRST#

CRESET#

BREQ0#

TESTIN#

GCLKO

GCLKIN

DCLKO

DCLKWR

Host

Interface

DRAM

Interface

Clocks,

Reset,

Test,

and

Misc.

PCI Bus Interface (PCI #0)

AGP

Interface

Power

Mgnt

AD[31:0] C/BE[3:0]# FRAME# TRDY# IRDY# DEVSEL# PAR SERR# PLOCK# STOP#

PHOLD# PHLDA# WSC# PREQ0# PREQ[4:1]# PGNT0# PGNT[4:1]#

GAD[31:0] GC/BE[3:0]# GFRAME# GIRDY# GTRDY# GSTOP# GDEVSEL# GREQ# GGNT# GPAR

PIPE# SBA[7:0] RBF# STOP# ST[2:0] ADSTB_A ADSTB_B SBSTB

CLKRUN# SUSTAT# BXPWROK

BX_BLK.VSD

82443BX Host Bridge

Datasheet

Page 5

1 Architectural Overview...............................................................................................1-1

2 Signal Description......................................................................................................2-1

2.1 Host Interface Signals...................................................................................2-1

2.2 DRAM Interface ............................................................................................2-3

2.3 PCI Interface (Primary) .................................................................................2-5

2.4 Primary PCI Sideband Interface ...................................................................2-6

2.5 AGP Interface Signals...................................................................................2-7

2.6 Clocks, Reset, and Miscellaneous................................................................2-9

2.7 Power-Up/Reset Strap Options...................................................................2-10

3 Register Description...................................................................................................3-1

3.1 I/O Mapped Registers...................................................................................3-2

3.1.1 CONFADD—Configuration Address Registe r................... ...... .........3-2

3.1.2 CONFDATA—Configuration Data Register .....................................3-3

3.1.3 PM2_CTL—ACPI Power Control 2 Control Register.......................3-4

3.2 PCI Configuration Space Access..................................................................3-4

3.2.1 Configuration Space Mechanism Overview.....................................3-5

3.2.2 Routing the Configuration Accesses to PCI or AGP........................3-5

3.2.3 PCI Bus Configuration Mechanism Overview..................................3-6

3.2.3.1 Type 0 Access ....................................................................3-6

3.2.3.2 Type 1 Access ....................................................................3-6

3.2.4 AGP Bus Configuration Mechanism Overview ................................3-6

3.2.5 Mapping of Configuration Cycles on AGP .......................................3-7

3.3 Host-to-PCI Bridge Registers (Device 0) ......................................................3-8

3.3.1 VID—Vendor Identification Register (Device 0).............................3-10

3.3.2 DID—Device Identification Register (Device 0) .............................3-10

3.3.3 PCICMD—PCI Command Register (Device 0)..............................3-11

3.3.4 PCISTS—PCI Status Register (Device 0) .....................................3-12

3.3.5 RID—Revision Identification Register (Device 0) ..........................3-13

3.3.6 SUBC—Sub-Class Code Register (Device 0) ...............................3-13

3.3.7 BCC—Base Class Code Register (Device 0) ................................3-13

3.3.8 MLT—Master Latency Timer Register (Device 0)..........................3-14

3.3.9 HDR—Header Type Register (Device 0).......................................3-14

3.3.10 APBASE—Aperture Base Configuration Register (Device 0)........3-14

3.3.11 SVID—Subsystem Vendor Identification Register (Device 0)........3-15

3.3.12 SID—Subsystem Identification Register (Device 0).......................3-16

3.3.13 CAPPTR—Capabilities Pointer Register (Device 0)......................3-16

3.3.14 NBXCFG—NBX Configuration Register (Device 0).......................3-16

3.3.15 DRAMC—DRAM Control Register (Device 0) ...............................3-19

3.3.16 DRAMT—DRAM Timing Register (Device 0) ................................3-20

3.3.17 PAM[6:0]—Programmable Attribute Map Registers(Device 0)......3-20

3.3.18 DRB[0:7]—DRAM Row Boundary Registers (Device 0)................3-22

3.3.19 FDHC—Fixed DRAM Hole Control Register (Device 0) ................3-24

3.3.20 MBSC—Memory Buffer Strength Control Register (Device 0) ......3-25

3.3.21 SMRAM—System Management RAM Control Register

(Device 0)‘......................................................................................3-28

82443BX Host Bridge

Datasheet

Page 6

3.3.22 ESMRAMC—Extended System Management RAM Control

3.3.23 RPS—SDRAM Row Page Size Register (Device 0)......................3-30

3.3.24 SDRAMC—SDRAM Control Register (Device 0) ..........................3-30

3.3.25 PGPOL—Paging Policy Register (Device 0) .................................3-32

3.3.26 PMCR—Power Management Control Register (Device 0) ............3-33

3.3.27 SCRR—Suspend CBR Refresh Rate Register (Device 0) ............3-34

3.3.28 EAP—Error Address Pointer Register (Device 0)..........................3-35

3.3.29 ERRCMD—Error Command Register (Device 0)..........................3-36

3.3.30 ERRSTS—Error Status Register (Device 0)..................................3-37

3.3.31 ACAPID—AGP Capability Identifier Register (Device 0)...............3-38

3.3.32 AGPSTAT—AGP Status Register (Device 0)................................3-38

3.3.33 AGPCMD—AGP Command Register (Device 0)...........................3-39

3.3.34 AGPCTRL—AGP Control Register (Device 0) ..............................3-40

3.3.35 APSIZE—Aperture Size Register (Device 0).................................3-41

3.3.36 ATTBASE—Aperture Translation Table Base Register

(Device 0) ......................................................................................3-41

3.3.37 MBFS—Memory Buffer Frequency Select Register (Device 0).....3-42

3.3.38 BSPAD—BIOS Scratch Pad Register (Device 0) ..........................3-44

3.3.39 DWTC—DRAM Write Thermal Throttling Control Register

(Device 0) ......................................................................................3-45

3.3.40 DRTC—DRAM Read Thermal Throttling Control Register

(Device 0) ......................................................................................3-46

3.3.41 BUFFC—Buffer Control Register (Device 0) .................................3-47

3.4 PCI-to-PCI Bridge Registers (Device 1) .....................................................3-48

3.4.1 VID1—Vendor Identificatio n Registe r (Devi ce 1).......... ....... ...... ....3-49

3.4.2 DID1—Device Identification Register (Device 1) ...........................3-49

3.4.3 PCICMD1—PCI-to-PCI Command Register (Device 1) ................3-50

3.4.4 PCISTS1—PCI-to-PCI Status Register (Device 1)........................3-51

3.4.5 RID1—Revision Identification Register (Device 1) ........................3-51

3.4.6 SUBC1—Sub-Class Code Register (Device 1) .............................3-52

3.4.7 BCC1—Base Class Code Register (Device 1) ..............................3-52

3.4.8 MLT1—Master Latency Timer Register (Device 1)........................3-52

3.4.9 HDR1—Header Type Register (Device 1).....................................3-53

3.4.10 PBUSN—Primary Bus Number Register (Device 1)......................3-53

3.4.11 SBUSN—Secondary Bus Number Register (Device 1).................3-53

3.4.12 SUBUSN—Subordinate Bus Number Register (Device 1) ............3-54

3.4.13 SMLT—Secondary Master Latency Timer Register (Device 1).....3-54

3.4.14 IOBASE—I/O Base Address Register (Device 1)..........................3-54

3.4.15 IOLIMIT—I/O Limit Address Register (Device 1)...........................3-55

3.4.16 SSTS—Secondary PCI-to-PCI Status Register (Device 1) ...........3-56

3.4.17 MBASE—Memory Base Address Register (Device 1)...................3-57

3.4.18 MLIMIT—Memory Limit Address Register (Device 1)....................3-57

3.4.19 PMBASE—Prefetc hab le Mem ory Bas e Add re ss Regis te r

(Device 1) ......................................................................................3-58

3.4.20 PMLIMIT—Prefetchable Memory Limit Address Register

(Device 1) ......................................................................................3-58

3.4.21 BCTRL—PCI-to-PCI Bridge Control Register (Device 1) ..............3-59

82443BX Host Bridge

Datasheet

Page 7

4 Functional Description ...............................................................................................4-1

4.1 System Address Map....................................................................................4-1

4.1.1 Memory Address Ranges ................................................................4-2

4.1.1.1 Compatibility Area...............................................................4-3

4.1.1.2 Extended Memory Area ......................................................4-4

4.1.1.3 AGP Memory Address Range.............................................4-6

4.1.1.4 AGP DRAM Graphics Aperture...........................................4-6

4.1.1.5 System Management Mode (SMM) Memory Range...........4-6

4.1.2 Memory Shadowing .........................................................................4-8

4.1.3 I/O Address Space...........................................................................4-8

4.1.4 AGP I/O Address Mapping...............................................................4-8

4.1.5 Decode Rules and Cross-Bridge Address Mapping ........................4-9

4.1.5.1 PCI Interface Decode Rules ...............................................4-9

4.1.5.2 AGP Interface Decode Rules..............................................4-9

4.1.5.3 Legacy VGA Ranges ........................................................4-10

4.2 Host Interface..............................................................................................4-10

4.2.1 Host Bus Device Support...............................................................4-10

4.2.2 Symmetric Multiprocessor (SMP) Protocol Support.......................4-13

4.2.3 In-Order Queue Pipelining.............................................................4-13

4.2.4 Frame Buffer Memory Support (USWC)........................................4-13

4.3 DRAM Interface ..........................................................................................4-14

4.3.1 DRAM Organization and Configuration..........................................4-14

4.3.1.1 Configuration Mechanism For DIMMS..............................4-19

4.3.2 DRAM Address Translation and Decoding ....................................4-20

4.3.3 SDRAMC Register Programming ..................................................4-23

4.3.4 DRAMT Register Programming .....................................................4-23

4.3.5 SDRAM Paging Policy ...................................................................4-24

4.4 PCI Interface...............................................................................................4-24

4.5 AGP Interface .............................................................................................4-24

4.6 Data Integrity Support.................................................................................4-25

4.6.1 Data Integrity Mode Selection........................................................4-25

4.6.1.1 Non-ECC (Default Mode of Operation).............................4-25

4.6.1.2 EC Mode...........................................................................4-25

4.6.1.3 ECC Mode ........................................................................4-25

4.6.1.4 ECC Generation and Error Detection/Correction

and Reporting ...................................................................4-26

4.6.1.5 Optimum ECC Coverage ..................................................4-27

4.6.2 DRAM ECC Error Signaling Mechanism........................................4-27

4.6.3 CPU Bus Integrity ..........................................................................4-27

4.6.4 PCI Bus Integrity............................................................................4-27

4.7 System Clocking .........................................................................................4-28

4.8 Power Management....................................................................................4-28

4.8.1 Overview........................................................................................4-28

4.8.2 82443BX Reset..............................................................................4-32

4.8.2.1 CPU Reset........................................................................4-33

4.8.2.2 CPU Clock Ratio Straps....................................................4-33

4.8.2.3 82443BX Straps................................................................4-34

4.8.3 Suspend Resume ..........................................................................4-34

4.8.3.1 Suspend Resume protocols..............................................4-34

4.8.3.2 Suspend Refresh ..............................................................4-34

4.8.4 Clock Control Functions.................................................................4-35

4.8.5 SDRAM Power Down Mode...........................................................4-36

82443BX Host Bridge

Datasheet

vii

Page 8

4.8.6 SMRAM .........................................................................................4-36

5 Pinout and Package Information................................................................................5-1

5.1 82443BX Pinout............................................................................................5-1

5.2 Package Dimensions.................... ....... ...... ....... ...... ...... ....... .........................5-8

Figures

1-1 Intel® 440BX AGPset System Block Diagram .............................................1-2

3-1 82443BX PCI Bus Hierarchy ........................................................................3-5

3-2 SDRAM DIMMs and Corresponding DRB Registers..................................3-23

4-1 Memory System Address Space ..................................................................4-2

4-2 Four-DIMM Configuration with FET switches .............................................4-16

4-3 Three-DIMM SDRAM Configuration ...........................................................4-17

4-4 Three-SODIMMs EDO Configuration .........................................................4-18

4-5 Three-SODIMMs SDRAM Configuration ....................................................4-19

4-6 Typical Intel 4-7 Reset CPURST# in a Desktop or Mobile System When

PCIRST# Asserted .....................................................................................4-33

4-8 External Glue Logic Drives CPU Clock Ratio Straps..................................4-34

5-1 82443BX Pinout (Top View–left side)...........................................................5-2

5-2 82443BX Pinout (Top View–right side).........................................................5-3

5-3 82443BX BGA Package Dimensions—Top and Side Views ........................5-8

5-4 82443BX BGA Package Dimensions—Bottom Views..................................5-9

440BX AGPset System Clocking..........................................4-28

viii

82443BX Host Bridge

Datasheet

Page 9

Tables

2-1 Host Interface Signals...................................................................................2-1

2-2 Host Signals Not supported by the 82443BX................................................2-3

2-3 DRAM Interface Signals................................................................................2-3

2-4 Primary PCI Interface Signals.......................................................................2-5

2-5 Primary PCI Sideband Interface Signals.......................................................2-6

2-6 AGP Interface Signals...................................................................................2-7

2-7 Clocks, Reset, and Miscellaneous................................................................2-9

2-8 Power Management Interface.......................................................................2-9

2-9 Reference Pins ...........................................................................................2-10

2-10 Strapping Options .......................................................................................2-11

3-1 82443BX Register Map — Device 0.............................................................3-8

3-2 Attribute Bit Assignment..............................................................................3-21

3-3 PAM Registers and Associated Memory Segments...................................3-21

3-4 82443BX Configuration Space—Device 1..................................................3-48

4-1 Memory Segments and their Attributes.........................................................4-3

4-2 SMRAM Decoding ........................................................................................4-7

4-3 SMRAM Range Decode................................................................................4-7

4-4 SMRAM Decode Control...............................................................................4-7

4-5 Host Bus Transactions Supported By 82443BX .........................................4-11

4-6 Host Responses supported by the 82443BX..............................................4-12

4-7 Host Special Cycles with 82443BX.............................................................4-12

4-8 Sample Of Possible Mix And Match Options For 6 Row/3

DIMM Configurations ..................................................................................4-15

4-9 Data Bytes on DIMM Used for Programming DRAM Registers..................4-20

4-10 Supported Memory Configurations ................................................ ...... .......4-21

4-11 MA Muxing vs. DRAM Address Split...........................................................4-22

4-12 Programmable SDRAM Timing Parameters...............................................4-23

4-13 EDO DRAM Timing Parameters .................................................................4-23

4-14 Low Power Mode ........................................................................................4-31

4-15 AGPset Reset .............................................................................................4-32

4-16 Reset Signals..............................................................................................4-32

4-17 Suspend / Resume Events and Activities ...................................................4-34

4-18 SDRAM Suspend Refresh Configuration Modes........................................4-35

5-1 82443BX Alphabetical BGA Pin List.............................................................5-4

5-2 82443BX Package Dimensions (492 BGA) ..................................................5-9

82443BX Host Bridge

Datasheet

Page 10

Page 11

Architectural Overview

The Intel® 440BX AGPset includes the 82443BX Host Bridge and the 82371EB PIIX4E for the I/O subsystem. The 82443BX functions and capabilities include:

Support for single and dual Pentium II processor configurations

•

64-bit GTL+ based Host Bus Interface

•

32-bit Host address Support

•

64-bit Main Memory Interface with optimized support for SDRAM at 100 and 66/60 MHz

•

32-bit Primary PCI Bus Interface (PCI) with integrated PCI arbiter

•

AGP Interface (AGP) with 133 MHz data transfer capability configurable as a Secondary PCI

•

Bus Extensive Data Buffering between all interfaces for high thr oug hp ut and co ncur rent o peration s

•

Mobile and “Deep Green” Desktop power management support

•

Figure 1-1 shows a block diagram of a typical platform based on the Intel 82443BX host bus interface supports up to two Pentium II processors at the maximum bus frequency of 10 0 MHz. The ph ysical interface d esign is based on the GTL+ specifi cation optimized for the desktop. The 82443BX provides an optimized 64-bit DRAM interface. This interface is implemented as a 3.3V-only interface that supports only 3V DRAM technology. Two copies of the MA, and CS# signals drive a maximum of two DIMMs each; providing unbuffered high performance at 100 MHz. The 82443BX provides interface to PCI operating at 33 MHz. This interface implementation is compliant with PCI Rev 2.1 Specification. The 82443BX AGP interface implementation is based on Rev 1.0 of the AGP Specification. The AGP interface supports 133 MHz data transfer rates and can be used as a Secondary PCI interface operating at 66 MHz/3.3V supporting only a single PCI agent.

The 82443BX is designed to support the PIIX4E I/O bridge. PIIX4E is a highly integrated multifunctional component su pporting the following functions and capabiliti es:

PCI Rev 2.1 compliant PCI-ISA Bridge with support for both 3.3V and 5V 33 MHz PCI

•

operations Deep Green Desktop Power Management Support

•

Mobile Power Management Support

•

Enhanced DMA controller and Interrupt Controller and Timer functions

•

Integrated IDE controller with Ultra DMA/33 support

•

USB host interface with support for 2 USB ports

•

System Management Bus (SMB) with support for DIMM Serial PD

•

Support for an external I/O APIC component

•

440BX AGPset. The

82443BX Host Bridge Datasheet

1-1

Page 12

Architectural Overview

Figure 1-1. Intel

440BX AGPset System Block Diagram

Pentium®

Processor

Video

- DVD

- Camera

- VCR

Display

Video BIOS

- VMI

- Video Capture

Graphics

Encoder

2 IDE Ports

(Ultra DMA/33)

Device

2 USB

Ports

2X AGP Bus

Graphics

Local Memory

USB

Host Bus

82443BX

Host Bridge

82371EB

(PIIX4E)

(PCI-to-ISA

Bridge)

Pentium®

Processor

66/100

MHz

3.3V EDO &

SDRAM Support

Primary PCI Bus

(PCI Bus #0)

System MGMT (SM) Bus

Main

Memory

PCI Slots

APIC

ISA Slots

ISA Bus

System BIOS

sys_blk.vsd

Host Interface

The Pentium II processor supports a second level cache via a back-side bus (BSB) interface. All control for the L2 cache is handled by the processor. The 82443BX provides bus control signals and address paths for transfers between the processors front-side bus (host bus), PCI bus, AGP and main memory. The 82443BX supports a 4-deep in-order queue (i.e., supports pipelining of up to 4 outstanding transaction requests on the host bus). Due to the system concurrency requirements, along with support for pipelining of address requests from the host bus, the 82443BX supports request queuing for all three interfaces (Host, AGP and PCI).

Host-initiated I/O cycles are decoded to PCI, AGP or PCI configuration space. Host-initiated memory cycles are decoded to PCI, AGP (prefetchable or non-prefetchable memory space) or DRAM (including AGP aperture memory). For memory cycles (host, PCI or AGP initiated) that target the AGP aperture space in DRAM, the 82443BX translates the address using the AGP address translation table. Other host cycles forwarded to AGP are def ined by the A GP address map.

PCI and AGP initiated cycles that target the AGP graphics aperture are also translated using the AGP aperture translation table. AGP-initiated cycles that target the AGP graphics aperture mapped in main memory do not require a snoop cycle on the host bus, since the coherency of data for that particular memory range will be maintained by the software.

1-2

82443BX Host Bridge Datasheet

Page 13

Architectural Overview

DRAM Interface The 82443BX integrates a DRAM controller that supports a 64-bit main memory interface. The

DRAM controller supports the following features:

DRAM type: Extended Data Out (EDO) (mobile only) or Synchronous (SDRAM) DRAM

•

controller optim ized for dual/qua d-bank SDRAM organi zation on a row by row basis Memory Size: 8 MB to 512 MB (1GB with Registered DIMMs) with eight memory rows

•

Addressing Type: Symmetrical and Asymmetrical addressing

•

Memory Modules supported : Single and double density 3.3V DIMMs

•

DRAM device technology: 16 Mbit and 64 Mbit

•

DRAM Speeds: 60 ns for EDO and 100/66 MHz for synchronous memory (SDRAM).

•

The Intel (SPD) mechanism using the SMBus interface. The 82443BX provides optional data integrity features including ECC in the memory array. During reads from DRAM, the 82443BX provides error checking and correction of the data. The 82443BX supports multiple-bit error detection and single-bit error correction when ECC mode is enabled and single/multi-bit error detection when correction is disabled. During writes to the DRAM, the 82443BX generates ECC for the data on a QWord basis. Partial QWord writes require a read-modify-write cycle when ECC is enabled.

AGP Interfa ce

The 82443BX AGP implementation is compatible with the following:

•

The 82443BX supports only a synchronous AGP interface coupling to the 82443BX core frequency. The AGP interface can reach a theoretical ~500 MByte/sec transfer rate (i.e., using 133 MHz AGP compliant dev ic es).

PCI Interface

The 82443BX PCI interface is 3.3V (5V tolerant), 33 MHz Rev. 2.1 compliant and supports up to five extern al PCI bus masters in addition to the I/O bridge (PIIX4/PIIX4E). The PCI-to-DRAM interface can reach over 100 MByte/sec transfer rate for streaming reads and over 120 MBytes/sec for streaming writes.

System Clocking

440BX AGPset also pro vides DIMM plug-an d-pla y suppo rt via Serial Presence Detect

The Accelerated Graphics Port Specification, Rev 1.0 Accelerated Graphics Port Memory Performance Specification, Rev 1.0 (4/12/96)

The 82443BX operates the host interface at 66 or 100 MHz, the SDRAM/core at 66 or 100 MHz, PCI at 33 MHz and AGP at 66/133 MHz.

I/O APIC

I/O APIC is used to support dual processors as well as enhanced interrupt processing in the single processor environment. The 82443BX supports an external status output signal that can be used to control synchronization of interru pts in configurations that use PIIX4E with stand-al on e I/O APIC component.

82443BX Host Bridge Datasheet

1-3

Page 14

Page 15

Signal Description

This chapter provides a detailed description of 443BX signals. The signals are arranged in functional groups according to their associated interface.

The “#” symbol at the end of a signal name indicates that the active, or asserted state occurs when the signal is at a low voltage level. When “#” is not present after the signal name the signal is asserted when at the high voltage level.

The following notations are used to describe the signal type:

I Input pin O Output pin OD Open Drain Output pin. This pin requires a pullup to the VCC of the processor core I/OD Input / Open Drain Output pin. This pin requi res a pul lup t o the VCC o f the p rocesso r

core

I/O Bi-directional Input/Output pin

The signal description also includes the type of buffer used for the particular signal:

GTL+ Open Drain GTL+ interface signal. Refer to the GTL+ I/O Specification for complete

details

PCI PCI bus interface signals. These signals are compliant with the PCI 3.3V and 5.0V

Signaling Environment DC and AC Specifications

AGP AGP interface signals. These signals are compatible with AGP 3.3V Signaling

Environment DC and AC Specificati ons

CMOS The CMOS buffers are Low Voltage TTL compatible signals. These are 3.3V only.

2.1 Host Interface Signals

Table 2-1. Host Interface Signals (Sheet 1 of 2)

Name Type Description

CPURST#

A[31:3]#

HD[63:0]#

GTL+

I/O

GTL+

I/O

GTL+

CPU Reset.

generates this signal based on the PCIRST# input (from PIIX4E) and also the SUSTAT # pin in mobile mode. The CPURST# allows the CPUs to begin execution in a known state.

Address Bus:

A[31:3]# are inputs.

Host Data:

signals are inverted on the CPU bus.

The CPURST# pin is an output from the 82443BX. The 82443BX

A[31:3]# connect to the CPU address bus. During CPU cycles, the

These signals are connected to the CPU data bus. Note that the data

82443BX Host Bridge Datasheet

2-1

Page 16

Signal Description

Table 2-1. Host Interface Signals (Sheet 2 of 2)

Name Type Description

I/O

ADS#

BNR#

BPRI#

BREQ0#

DBSY#

DEFER#

DRDY#

HIT#

HITM#

HLOCK#

HREQ[4:0]#

HTRDY#

RS[2:0]#

GTL+

Address Strobe:

cycles of a request phase.

I/O

Block Next Request:

new request. This signal is used to dynamically control the CPU bus pipeline depth.

Priority Agent Bus Request:

bus. It asserts this signal to obtain the ownership of the address bus. This signal has priority over symmetric bus requests and will cause the current symmetric owner to stop issuing new transactions unless the HLOCK# signal was asserted.

Symmetric Agent Bus Request:

asserted to configure the symmetric bus agents. BREQ0# is negated 2 host clocks after CPURST# is negated.

I/O

Data Bus Busy:

requiring more than one cycle.

Defer:

I/O

The 82443BX generates a deferred response as defined by the rules of the 82443BX’s dynamic defer policy. The 82443BX also uses the DEFER# signal to indicate a CPU retry response.

Data Ready:

Hit:

Indicates that a caching agent holds an unmodified version of the requested line.

Also driven in conjunction with HITM# by the target to extend the snoop window.

Hit Modified:

requested line and that this agent assumes responsibility for providing the line. Also driven in conjunction with HIT# to ex tend the snoop window.

Host Lock:

until the negation of HLOCK# must be atomic, i.e. no PCI or AGP snoopable access to DRAM is allowed when HLOCK# is asserted by the CPU.

Request Command:

the signals define the transaction type to a level of detail that is sufficient to begin a snoop request. In the second clock, the signals carry additional information to define the complete transaction type. The transactions supported by the 82443BX Host Bridge are defined in the Host Interface section of this document.

Host Target Ready:

the data transfer phase.

Response Signals: RS[2:0] Response type

000 Idle state 001 Retry response 010 Deferred response 011 Reserved (not driven by 82443BX) 100 Hard F ailure (not driv en by 82443BX) 101 No data response 110 Implicit Writeback 111 Normal data response

The CPU bus owner asserts ADS# to indicate the first of two

Used to block the current request bus owner from issuing a

The 82443BX is the only Priority Agent on the CPU

Asserted by the 82443BX when CPURST# is

Used by the data bus owner to hold the data bus for transfers

Asserted for each cycle that data is transferred.

Indicates that a caching agent holds a modified version of the

All CPU bus cycles sampled with the assertion of HLOCK# and ADS#,

Asserted during both clocks of request phase. In the first clock,

Indicates that the target of the CPU transaction is able to enter

Indicates type of response according to the following the table:

2-2

NOTE:

1. All of the signals in the host interface are described in the CPU External Bus Specification. The preceding table highlights 82443BX specific uses of these signals.

82443BX Host Bridge Datasheet

Page 17

Table 2-2 lists the CPU bus interface signals which are NOT supported by the Intel® 440BX

AGPset.

Table 2-2. Host Signals Not supported by the 82443BX

Signal Function Not Supported By 82443BX

A[35:32]# Address Extended addressing (over 4 GB) AERR# Address Parity Error Parity protection on address bus AP[1:0]# Address Parity Parity protection on address bus BINIT# Bus Initialization Checking for bus protocol violation and protocol recovery mechanism DEP[7:0]# Data Bus ECC/Parity Enhanced data bus integrity IERR# Internal Error Direct internal error observation via IERR# pin INIT# Soft Reset Implemented by PIIX4E, BIST supported by external logic. BERR# Bus Error Unrecoverable error without a bus protocol violation RP# Request Parity Parity protection on ADS# and PREQ[4:0]#

RSP#

Response Parity Signal

Parity protection on RS[2:0]#

Signal Description

2.2 DRAM Interface

Table 2-3.

DRAM Interface

Name T

RASA[5:0]# /CSA[5:0]#

RASB[5:0]# /CSB[5:0]#

CKE[3:2] /CSA[7:6]#

CKE[5:4] /CSB[7:6]#

CASA[7:0]# /DQMA[7:0]

CASB[1,5]# /DQMB[1,5]

Signals (Sheet 1 of 2)

Row Address Strobe (EDO):

the MAxx lines into the DRAMs. Each signal is used to select one DRAM row. These signals drive the DRAM array directly without any external buffers.

Chip Select (SDRAM):

CMOS

perform the function of selecting the particular SDRAM components during the active state.

Note that there are 2 copies of RAS# per physical memory row to improve the loading.

Clock Enable:

refresh or power-down command to an SDRAM array when entering system suspend. CKE is also used to dynamically power down inactive SDRAM rows. This CKE function is not supported with Registered DIMMs.

Chip Select (SDRAM):

particular SDRAM components during the active state. Note that there are 2 copies of CS# per physical memory row to reduce the

Column Address Strobe A-side (EDO):

latch the column address on the MA[13:0] lines into the DRAMs of the A half of the memory array . These are activ e low signals that drive the DRAM array directly

without external buffering.

Input/Output Data Mask A-side (SDRAM):

memory array and act as synchronized output enables during read cycles and as a byte enables during write cycles.

Column Address Strobe B-side (EDO) / Input/Output Data Mask B-side

(SDRAM):

signals are used to reduce the loading in an ECC configuration

Descri

These signals are used to latch the row address on

For the memory row configured with SDRAM these pins

In mobile mode, SDRAM Clock Enable is used to signal a self-

These pins perform the function of selecting the

The same function as a corresponding signals for A side. These

tion

The CASA[7:0]# signals are used to

These pins control A half of the

82443BX Host Bridge Datasheet

2-3

Page 18

Signal Description

Table 2-3.

DRAM Interface

Name T

GCKE/CKE1

SRAS[B,A]#

CKE0/FENA

SCAS[B,A]#

MAA[13:0] MAB[12:11]# MAB[13,10]

MAB[9:0]#

WEA# WEB#

MD [63:0]

MECC[7:0]

Signals (Sheet 2 of 2)

Global CKE (SDRAM):

power down mode for the SDRAM. External logic must be used to implement this function.

SDRAM Clock Enable (CKE1):

signal a self-refresh or power-down command to an SDRAM array when entering

CMOS

I/O

CMOS

I/O

CMOS

system suspend. CKE is also used to dynamically power down inactive SDRAM rows. The combination of SDRAMPWR (SDRAM register) and MMCONFIG (DRAMC register) determine the functioning of the CKE signals. Refer to the DRAMC register (Section 3.3.15, “DRAMC—DRA M Control Register (Device 0)” on page 3-19) for more details.

SDRAM Row Address Strobe (SDRAM):

copies of the same logical SRASx signal (for loading purposes) used to generate SDRAM command encoded on SRASx/SCASx/WE signals.

SDRAM Clock Enable 0 (CKE0).

is used to signal a self-refresh or power-down command to an SDRAM array when entering system suspend. CKE is also used to dynamically power down

inactive SDRAM rows.

FET Enable (FENA):

proper MD path through the FET switches (refer to Section4.3, “DRAM Interface” on page 4-14 for more details).

SDRAM Column Address Strobe (SDRAM):

multiple copies of the same logical SCASx signal (for loading purposes) used to generate SDRAM command encoded on SRASx/SCASx/WE signals.

Memory Address(EDO/SDRAM):

provide the multiplexed row and column address to DRAM. There are two sets of

MA signals which drive a max. of 2 DIMMs each. MAA[12:11,9:0] are inverted copies of MAB[12:11,9:0]#. MAA[13,10] and MAB[13,10] are identical copies. Each MAA/MAB[13:0] line has a programmable buffer strength to optimize for different signal loading conditions.

Write Enable Signal (EDO/SDRAM):

The WE# lines have a programmable buffer strength to optimize for different signal loading conditions.

Memory Data (EDO/SDRAM):

data bus.

Memory ECC Data (EDO/SDRAM):

during access to DRAM.

Description

Global CKE is used in a 4 DIMM configuration requiring

In mobile mode, SDRAM Clock Enable is used to

The SRAS[B,A]# signals are multiple

In mobile mode, CKE0 SDRAM Clock Enable

In a 4 DIMM configuration. FENA is used to select the

The SCAS[B,A]# signals are

MAA[13:0] and MAB[13:0]# are used to

WE# is asserted during writes to DRAM.

These signals are used to interface to the DRAM

These signals carry Memory ECC data

2-4

82443BX Host Bridge Datasheet

Page 19

2.3 PCI Interface (Primary)

Table 2-4. Primary PCI Interface Signals (Sheet 1 of 2)

Name Type Description

AD[31:0]

DEVSEL#

FRAME#

IRDY#

C/BE[3:0]#

PAR

PLOCK#

TRDY#

PCI Address/Data:

Address is driven by the 82443BX with FRAME# assertion, data is driven or received

I/O

in the following clocks. When the 82443BX acts as a target on the PCI Bus, the

PCI

AD[31:0] signals are inputs and contain the address during the first clock of FRAME# assertion and input data (writes) or output data (reads) on subsequent clocks.

Device Select:

decoded its address as the target of the current access. The 82443BX asserts

I/O

DEVSEL# based on the DRAM address range or

PCI

by a PCI initiator. As an input it indicates whether any device on the bus has been selected.

Frame:

FRAME# is an output when the 82443BX acts as an initiator on the PCI Bus. FRAME# is asserted by the 82443BX to indicate the beginning and duration of an access. The 82443BX asserts FRAME# to indicate a bus transaction is beginning.

I/O

While FRAME# is asserted, data transfers continue. When FRAME# is negated, the

PCI

transaction is in the final data phase. FRAME# is an input when the 82443BX acts as a PCI target. As a PCI target, the 82443BX latches the C/BE[3:0]# and the AD[31:0] signals on the first clock edge on which it samples FRAME# active.

Initiator Ready:

I/O

input when the 82443BX acts as a PCI target. The assertion of IRDY# indicates the current PCI Bus initiator's ability to complete the current data phase of the

PCI

transaction.

Command/Byte Enable:

multiplexed on the same pins. During the address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase C/BE[3:0]# are used as byte enables. The byte enables determine which byte lanes carry meaningful data. PCI Bus command encoding and types are listed below.

C/BE[3:0]# Command Type

0000 Interrupt Acknowledge 0001 Special Cycle 0010 I/O Read 0011 I/O Write

I/O

0100 Reserved

PCI

0101 Reserved 0110 Memory Read 0111 Memory Write 1000 Reserved 1001 Reserved 1010 Configuration Read 1011 Configuration Write 1100 Memory Read Multiple 1101 Reserved (Dual Address Cycle) 1110 Memory Read Line 1111 Memory Write and Invalidate

Parity:

I/O

PCI

I/O

PCI

I/O

PCI

PAR is driven by the 82443BX when it acts as a PCI initiator during address and data phases for a write cycle, and during the address phase for a read cycle. PAR is driven by the 82443BX when it acts as a PCI target during each data phase of a PCI memory read cycle. Even parity is generated across AD[31:0] and C/BE[3:0]#.

Lock:

PLOCK# indicates an exclusive bus operation and may require multiple transactions to complete. When PLOCK# is asserted, non-exclusive transactions may proceed. The 82443BX supports lock for CPU initiated cycles only. PCI initiated locked cycles are not supported.

Target Ready:

output when the 82443BX acts as a PCI target. The assertion of TRDY# indicates the target agent's ability to complete the current data phase of the transaction.

These signals are connected to the PCI address/data bus.

Device select, when asserted, indicates that a PCI target device has

IRDY# is an output when 82443BX acts as a PCI initiator and an

TRDY# is an input when the 82443BX acts as a PCI initiator and an

Signal Description

AGP address range

PCI Bus Command and Byte Enable signals are

being accessed

82443BX Host Bridge Datasheet

2-5

Page 20

Signal Description

Table 2-4. Primary PCI Interface Signals (Sheet 2 of 2)

Name Type Description

System Error:

SERR# assertion by the 82443BX is enabled globally via SERRE bit of the PCICMD register. SERR# is asserted under the following conditions:

In an ECC configuration, the 82443BX asserts SERR#, for single bit (correctable) ECC errors or multiple bit (non-correctable) ECC errors if SERR# signaling is enabled via the ERRCMD control register. Any ECC errors received during initialization should be ignored.

• The 82443BX asserts SERR# for one clock when it detects a target abort during 82443BX initiated PCI cycle.

• The 82443BX can also assert SERR# when a PCI parity error occurs during the

SERR#

STOP#

NOTE:

1. All PCI interface signals conform to the PCI Rev 2.1 specification.

I/O

PCI

I/O

PCI

address or data phase.

• The 82443BX can assert SERR# when it detects a PCI address or data parity error on AGP.

• The 82443BX can assert SERR# upon detection of access to an invalid entry in the Graphics Aperture Translation Table.

• The 82443BX can assert SERR# upon detecting an invalid AGP master access outside of AGP aperture and outside of main DRAM range (i.e. in the 640k - 1M range or above TOM).

• The 82443BX can assert SERR# upon detecting an invalid AGP master access outside of AGP aperture.

• The 82443BX asserts SERR# for one clock when it detects a target abort during 82443BX initiated AGP cycle.

Stop:

STOP# is an input when the 82443BX acts as a PCI initiator and an output when the 82443BX acts as a PCI target. STOP# is used for disconnect, retry, and abort sequences on the PCI Bus.

The 82443BX asserts this signal to indicate an error condition. The

2.4 Primary PCI Sideband Interface

Table 2-5.

Primar

PHOLD#

PHLDA#

WSC#

PREQ[4:0]#

PGNT[4:0]#

PCI Sideband Interface

Name Type Description

PCI Hold:

ownership. The 82443BX will flush and disable the CPU-to-PCI write buffers before

granting the PIIX4E the PCI bus via PHLDA #. This prevents bus deadlock between

PCI

PCI and ISA.

PCI Hold Acknowledge:

ownership to the PIIX4E after CPU-PCI post buffers have been flushed and disabled.

PCI

Write Snoop Complete.

CMOS

snoop activity on the CPU bus on the behalf of the last PCI-DRAM write transaction is complete and that is safe to send the APIC interrupt message.

PCI Bus Request:

internal PCI arbiter.

PCI

PCI Grant: P

PCI arbiter.

PCI

Signals

This signal comes from the PIIX4E. It is the PIIX4E request for PCI bus

This signal is driven by the 82443BX to grant PCI bus

This signal is asserted active to indicate that all that the

PREQ[4:0]# are the PCI bus request signals used as inputs by the

GNT[4:0]# are the PCI bus grant output si gnals generated b y the internal

2-6

82443BX Host Bridge Datasheet

Page 21

2.5 AGP Interface Signals

]

y q

[

]

There are 17 new signals added to the normal PCI group of signals that together constitute the AGP interface. The sections below describe their operation and use, and are organized in five groups:

AGP Addressing Signals

•

AGP Flow Control Signals

•

AGP Status Signals

•

AGP Clocking Signals - Strobes

•

PCI Signals

•

Table 2-6. AGP Interface Signals (Sheet 1 of 2)

Name Type Description

AGP Sideband Addressing Signals

PIPE#

SBA[7:0]

RBF#

ST[2:0]

Pipelined Read:

address is to be

clock ed queued across the AD bus.

AGP

(graphics controller)

may not use PIPE#.

Sideband Address:

command to the 82443BX from the AGP master. Note that, when sideband addressing is disabled, these signals are isolated (no external/internal pull-ups are

AGP

required).

Read Buffer Full.

AGP

uested low priority read data. When RBF# to return low priority read data to the AGP master on the first block. RBF# is only sampled at the beginning of a cycle.

If the AGP master is always ready to accept return read data then it is not required to implement this signal.

Status

Bus:

it ma

do. ST[2:0

When G

GNT#

000 Indicates that previously requested low priority read data is being returned to

the master.

001 Indicates that previously requested high priority read data is being returned to

the master.

010 Indicates that the master is to provide low priority write data for a previously

queued write command.

011 Indicates that the master is to provide high priority write data for a previously

queued write command. 100 Reserved 101 Reserved 110 Reserved 111 Indicates that the master has been

The master ma

transaction by asserting

82443BX and an input to the master.

This signal is asserted by the current master to indicate a full width

ueued by the target. The master queues one request each rising

e while PIPE#

AGP Flow Control Signals

This bus provides information from the arbiter to a AGP Master on what

only have meaning to the master when its G

is deasserted these signals have no meaning and must be ignored.

Signal Description

is asserted. When

and is an input to the 82443BX. Note that initial AGP designs

This bus

This signal indicates if the master is ready to accept previously

AGP Status Signals

ueue AGP requests by asserting PIPE#

is a sustained tri-state signal from

PIPE#

provides an additional bus to pass address and

FRAME#. ST

is deasserted no new requests are

PIPE#

is asserted the 82443BX is not allowed

iven permission to start a bus transaction.

are always an output from the

2:0

masters

is asserted.

GNT#

or start a PCI

82443BX Host Bridge Datasheet

2-7

Page 22

Signal Description

[

]

(

Table 2-6. AGP Interface Signals (Sheet 2 of 2)

Name Type Description

AD Bus Strobe A:

ADSTB_A

ADSTB_B

SBSTB

GFRAME#

GIRDY#

GTRDY#

GSTOP#

GDEVSEL#

GREQ#

GGNT#

GAD[31:0]

GC/BE[3:0]#

GPAR

I/O

The agent that is providing data drives this signal. This signal requires an 8.2K ohm

AGP

external pull-up resistor.

I/O

AD Bus Strobe B:

signal requires an 8.2K ohm external pull-up resistor.

AGP

Sideband Strobe:

requires an 8.2K ohm external pull-up resistor.

AGP

AGP FRAME# Protocol SIgnals (similar to PCI)

I/O

Graphics Frame:

by its own pull up resistor.

AGP

Graphics Initiator Ready:

master is ready to provide asserted for a write operation, the master is not allowed to insert wait states. The assertion of IRDY# for reads indicates that the master is ready to transfer to a

I/O

subsequent block (32 bytes) of read data. The master is

AGP

states during the initial data transfer (32 bytes) of a read transaction. However, it may insert wait states after each 32 byte block is transferred.

(There is no GFRAME#

Graphics Target Ready:

target is ready to provide read data for the entire transaction (when the tr ansfer siz e is

I/O

less than or equal to 32 bytes) or is ready to transfer the initial or subsequent block (32 bytes) of data when the transfer size is greater than 32 bytes. The target is

AGP

allowed to insert wait states after each block (32 bytes) is transferred on both read and write transactions.

I/O

Graphics Stop:

AGP

I/O

Graphics Device Select:

AGP

Graphics Request:

PCI or AGP request.)

AGP

Graphics Grant:

. The additional information indicates that the selected master is the recipient

AGP

I/O

AGP

I/O

AGP

I/O

AGP

2:0 of previously requested read data (high or normal priority), it is to provide write data (high or normal priority), for a previously queued write command or has been given permission to start a bus transaction (AGP or PCI).

Graphics Address/Data:

Graphics Command/Byte Enables:

information usin

PIPE#

not used during the return of read data.

Graphics Parity:

transactions as defined by the PCI specification.

AGP Clocking Signals - Strobes

This si

nal provides timing for double clocked data on the AD

This signal is an additional copy of the AD_STBA signal. This

THis signal provides timing for a side-band bus. This signal

Same as PCI. Not used b

New meanin

all

write data for the current transaction. Once IRDY# is

GIRDY#

New meanin

Same as PCI. Not used by AGP.

Same as PCI. (Used to request access to the bus to initiate a

Same meanin

Same as PCI.

different commands than PCI) when requests are being queued when . Provide valid byte information during AGP write transactions and are

Same as PCI. Not used on AGP transactions, but used during PCI

relationship for AGP transactions.)

as PCI but additional information is provided on

AGP. GFRAME#

. GIRDY#

. GTRDY#

Sli

htly different meaning. Provides command

indicates the AGP compliant

remains deasserted

never

allowed to insert wait

bus.

NOTE:

AGP Sideband Addressing Signals.

the AGP master. Note that the master can only use one mechanism. When PIPE# is used to queue addresses the master is not allowed to queue addresses using the SBA bus. For ex ample, during configuration time, if the master indicates that it can use either mechanism, the configuration software will indicate which mechanism the master will use. Once this choice has been made, the master will continue to use the mechanism selected until the master is reset (and reprogrammed) to use the other mode. This change of modes is not a dynamic mechanism but rather a static decision when the device is first being configured after reset.

2-8

The above table contains two mechanisms to queue requests by

82443BX Host Bridge Datasheet

Page 23

2. PCI signals are redefined when used in AGP transactions carried using AG P protocol extension. For transactions on the AGP interface carried using PCI protocol these signals completely preserve PCI semantics. The exact role of all PCI signals during AGP transactions is in Table 2-6.

3. The LOCK# signal is not supported on the AGP interface (even for PCI operations).

4. PCI signals described in Table 2-4 behave according to PCI 2.1 specifications when used to perform PCI transactions on the AGP Interface.

2.6 Clocks, Reset, and Miscellaneous

Table 2-7. Clocks, Reset, and Miscellaneous

Name Type Description

HCLKIN

PCLKIN

DCLKO

DCLKWR

PCIRST#

GCLKIN

GCLKO

CRESET#

TESTIN#

CMOS

Host Clock In:

82443BX logic that is in the Host clock domain. When SUSTAT# is active, there is an internal 100K ohm pull down on this signal.

PCI Clock In:

an external clock synthesizer component from the host clock. This clock is used by all of the 82443BX logic that is in the PCI clock domain.

When SUSTAT# is active, there is an internal 100K ohm pull down on this signal.

SDRAM Clock Out:

buffer clock device that produces multiple copies for the DIMMs.

SDRAM Write Clock:

This clock is used by the 82443BX when writing data to the SDRAM array. Note: See the Design Guide for routing constraints.

PCI Reset:

and bi-directional signals will also tri-state compliant to PCI Rev 2.0 and 2.1 specifications.

When SUSTAT# is active, there is an internal 100K ohm pull down on this signal.

AGP Clock In:

AGP Clock Out:

both the reference input pin on the 82443BX and the AGP compliant device.

Delayed CPU Reset:

to control the multiplexer for the CPU strap signals. CRESET# is delayed from CPURST# by two host clocks.

Note:

This pin requires an external pull-up resistor. If not used, no pull up is required.

Test Input:

Note: This pin has an internal 50K ohm pull-up.

This pin receives a buffered host clock. This clock is used by all of the

This is a buffered PCI clock reference that is synchronously derived by

66 or 100 MHz SDRAM clock reference. It feeds an external

Feedback reference from the external SDRAM clock buffer.

When asserted, this signal will reset the 82443BX logic. All PCI output

The GCLKIN input is a feedback reference from the GCLKOUT signal.

The frequency is 66 MHz. The GCLKOUT output is used to feed

CRESET# is a delayed copy of CPURST#. This signal is used

This pin is used for manufa cturing, and board level test purposes.

Signal Description

Table 2-8. Power Management Interface

Name Type Description

Primary PCI Clock Run:

or maintain the PCI clock by the assertion of CLKRUN#. The 82443BX tristates

I/OD

CLKRUN#

SUSTAT#

BXPWROK

CMOS

82443BX Host Bridge Datasheet

CLKRUN# upon deassertion of PCIRST# (since CLK is running upon deassertion of reset). If connected to PIIX4E an external 2.7K Ohm pull-up is required for Desktop, Mobile requires (8.2k–10K) pull-up. Otherwise, a 100 Ohm pull down is required.

Suspend Status (from PIIX):

from the PIIX4E. It is used to isolate the suspend voltage well and enter/exit DRAM self-refresh mode. During POS/STR SUSTAT# is active.

BX Power OK:

indicates valid power is applied to the 82443BX.

The 82443BX requests the central resource (PIIX4E) to start

SUSTAT# signals the system suspend state transition

BXPWROK input must be connected to the PWROK signal that

2-9

Page 24

Signal Description

Table 2-9. Reference Pins

Name Description

GTLREF[B:A] GTL Buffer voltage reference input VTT[B:A] GTL Threshold voltage for early clamps VCC Power pin @ 3.3V VSS Ground REF5V PCI 5V reference voltage (for 5V tolerant buffers) AGPREF Ex ternal Input Reference

2.7 Power-Up/Reset Strap Options

Ta ble 2-10 is the list of all power-up options that are loaded into the 82443BX during cold reset. The 82443BX is required to float all the signals connected to straps during cold reset and keep them floated for a minimum of 4 host clocks after the end of cold reset sequence. Cold reset sequence is performed when the 82443BX power is applied.

Note: All signals used to select power-up strap options are connected to either internal pull-down or pull-

up resistors of minimum 50K ohm s (max im um i s 150 K). That sel ect s a def ault mode on the signal during reset. To enable different mod es, e xternal pul l ups or pul l do wns (the op posite of the i nternal resistor) of approximately 10K ohm can be connected to particular signals. These pull up or pull down resistors should be connected to the 3.3V power supply.

During normal operation of the 82443BX, including while it is in suspend mode, the paths from GND or Vcc to internal strapping resistors are disabled to effectively disable the resistors. In these cases, the MAB# lines are driven by the 82443BX to a valid voltage levels.

Note: Note that when resuming from suspend, even while PCIRST# is active, the MAB# lines remain

driven by the 82443BX and the strapping latches maintain the value stored during the cold reset. This first column in Table 2-10 lists the sign al that is sampled to obtain the strapping option. The

second column shows which register the strapping option is loaded into. The third column is a description of what functionality the strapping selects.

The GTL+ signals are connected to the VTT through the normal pull-ups. CPU bus straps controlled by the 82443BX (e.g. A7# and A15#), are driven active at least six clocks prior to the active-to-inactive edge of CPURST# and driven inactive four clocks after the active-to-inactive edge of the CPURST#.

2-10

82443BX Host Bridge Datasheet

Page 25

Table 2-10. Strapping Options

Signal Description

Signal

MAB13#

MAB12# NBXCFG[13]

MAB11# NBXCFG[2]

MAB10 PMCR[3]

MAB9# PMCR [1]

MAB8#

MAB7# DRAMC[5]

MAB6# none

A[15]# none

A7# none

Name[bit]

Description

Reserved. Host Frequency Select:

66 MHz. If MAB#12 is strapped to 1, the host bus frequency is 100 MHz. An internal pull-down is used to provide the default setting of 66 MHz.

In-Order Queue Depth Enable.

of PCIRST#, then the 82442BX will drive A7# low during the CPURST# deassertion. This forces the CPU bus to be configured for non-pipelined operation.

If MAB11 is strapped to 1 (default), then the 82443BX does not drive the A7# low during reset, and A7# is sampled in default non-driven state (i.e. pulled-up as far as GTL+ termination is concerned) then the maximum allowable queue depth by the CPU bus protocol is selected (i.e., 8).

Note that internal pull-up is used to provide pipelined bus mode as a default.

Quick Start Select.

mode is used. MAB10 = 0 (default) for normal stop clock mode. If MAB10 = 1 during the rising

edge of PCIRST#, then the 82443BX will drive A15# low during CPURST# deassertion. This will configure the CPU for Quick Start mode of operation.

Note that internal pull-down is used to provide normal stop clock mode as a default.

AGP Disable:

are tri-stated and isolated. When strapped to a 0 (default), the AGP interface is enabled.

When MMCONFIG is strapped active, we require that AGP_DISABLE is also strapped active. When MMCONFIG is strapped inactive, AGP_DISABLE can be strapped active or inactive but IDSEL_REDIRECT (bit 16 in NBXCFG register) must never be activated.

This signal has an internal pull-down resistor.

Reserved. Memory Module Configuration, MMCONFIG:

82443BX configures its DRAM interface in a 430-TX compatible manner. These unused inputs are isolated while unused outputs are tri-stated: RASB[5:0]#/ CSB[5:0]#, CKE[3:2]/CSA[7:6]#, CKE[5:4]/CSB[7:6]#, CASB[5,1]#/DQMB[5,1], GCKE/CKE1, MAA[13:0], DCLKO.

When strapped to a 0 (default), the 82443BX DRAM signal are used normally. IDSEL_REDIRECT (bit 16 in NBXCFG register) is programmed by BIOS, before it begins with device enumeration process. The combination of SDRAMPWR (SDRAMC register) and MMCONFIG (DRAMC register) determine the functioning of the CKE signals. Refer to the DRAMC register for more details.

Note that internal pull-down is used to set the DRAM interface to a nor mal configuration, as a default.

Host Bus Buffer Mode Select:

100 MHz host bus buffers are used (default). When strapped ‘1’, the mobile Low Power GTL+ 66 MHz host bus buffers are

selected. Note that internal pull-down is used to set the host bus buffers to a desktop

configuration as a default. External pull-up therefore is needed f or mobile systems, only.

Quick Start Select.

will reflect if the quick start/stop clock mode is enabled in the processors.

In-order Queue Depth Status.

CPURST# reflects if the IOQD is set to 1 or maximum allowab le by the CPU bus.

When strapped to a 1, the AGP interface is disabled, all A GP signals

If MAB#12 is strapped to 0, the host bus frequency is 60/

If MAB11# is strapped to 0 during the rising edge

The value on this pin at reset determines which stop clock

When strapped to a 1, the

When strapped 0, the desktop GTL+ 66 MHz or

The value on A15# sampled at the rising edge of CPURST#

The value on A[7]# sampled at the rising edge of

NOTE:

1. Proper strapping must be used to define logical values for these signals. Default value “0”, or “1” provided by the internal pull-up or pull-down resistor can be overridden by the external pull-up, or pull-down resistor

82443BX Host Bridge Datasheet

2-11

Page 26

Page 27

Register Description

The 82443BX contains two sets of software accessible registers, accessed via the Host CPU I/O address space:

1. Control re gisters that are I/O mapped into the CPU I/O space. These re gisters co ntrol access to PCI and AGP configuration space.

2. Internal configuration registers residing within the 82443BX, partitione d into two logical device register sets (“logical” since they reside within a single physical device). The first register set is dedicated to Host-to-PCI Bridge functionality. This set (device 0) controls PCI interface operations, DRAM configuration, and other chip-set operating parameters and optional features. The second register set (dev ice 1) is dedicated to Host-to-AGP Bridge functions (controls AGP interface configurations and operating parameters).

The following nomenclature is used for register access attributes.

RO Read Only. If a register is read only, writes to this register have no effect. R/W Read/Write. A register with this attribute can be read and written R/WC Read/Write Clear. A register bit with this attribute can be read and written.

However, a write of a 1 clears (sets to 0) the corresponding bit and a write of a 0 has no effect.

R/WO Read/Write Once. A register bit with this attribute can be written to only once after

power up. After the first write, the bit becomes read only.

R/WL Read/Write/Lock. This register includes a lock bit. Once the lock bit has been set to

1, the register becomes read only.

The 82443BX supports PCI configuration space access using the mechanism denoted as Configuration Mechanism #1 in the PCI specification.

The 82443BX internal registers (both I/O Mapped and Configuration registers) are accessible by the Host CPU. The registers can be accessed as Byte, Word (16-bit), or DWord (32-bit) quantities, with the exception of CONFADD which can on ly be accessed as a Dword. All multi-byte numeric fields use "little-endian" ordering (i.e., lower addresses contain the least significant parts of the field).

Some of the 82443BX registers described in this section contain reserved bits. These bits are labeled "Reserved”. Software must deal correctly with fields that are reserved. On reads, software must use appropriate masks to extract the defined bits and not rely on reserved bits being any particular value. On writes, software must ensure that the values of reserved bit positions are preserved. That is, the values of reserved bit positions must first be read, merged with the new values for other bit positions and then written back.

Note: Software does not need to perform read, merge, write operation for the configuration address

configuration space of the Host-to-PCI Bridge entity that are marked either "Reserved" or “Intel Reserved”. The 82443BX responds to accesses to “Reserved” address locations by completing the host cycle. When a “Reserved” register location is read, a zero value is returned. (“Reserved” registers can be 8-, 16-, or 32-bit in size). Writes to “Reserved” registers have no effect on the

82443BX Host Bridge Datasheet

3-1

Page 28

82443BX. Registers that are marked as “I ntel R eserv ed ” mu st not be modified b y system softw are. Writes to “Intel Reserved” registers may cause system failure. Reads to “Intel Reserved” registers may return a non-zero value. Software should not write to reserved configuration locations in the device-specific region (above address offset 3Fh)

Upon reset, the 82443BX sets its internal configuration registers to predetermined default states. However, there are a few exceptions to this rule.

1. When a reset occurs during the POS/STR state, several configuration bits are not reset to their default state. These bits are noted in the following register description.

2. Some register values at reset are determined by external strapping options.

The default state represents the minimum functionalit y feature set requir ed to successfully bri ng up the system. Hence, it does not represent the optimal system configuration. It is the responsibility of the system initialization software (usually BIOS) to properly determine the DRAM configurations, operating parameters and optional system features that are applicable, and to program the 82443BX registers accordingly.

3.1 I/O Mapped Registers

The 82443BX contains three registers that reside in the CPU I/O address space − the Confi

uration Address (CONFADD) Register, the Configuration Data (CONFDATA)

ister, and the Power Management Control Register. The Configuration Address

ister enables/disables the configuration space and determines what portion of

confi

uration space is visible through the Configuration Data window.

3.1.1 CONFADD—Configuration Address Register

I/O Address: 0CF8h Accessed as a Dword Default Value: 00000000h Access: Read/Write Size: 32 bits

CONFADD is a 32 bit register accessed only when referenced as a Dword. A Byte or Word reference will "pass through" the Configuration Add ress Re g ister onto the PCI bus as an I/O cycle. The CONFADD register contains the Bus Number, Device Number, Function Number, and Register Number for which a subsequent configuration access is intended.

3-2

82443BX Host Bridge Datasheet

Page 29

Bit Descriptions

Configuration Enable (CFGE).

enabled. If this bit is reset to 0 accesses to PCI configuration space are disabled.

30:24

23:16

15:11

10:8

7:2

1:0 Reserved.

Reserved. Bus Number.

is either the 82443BX or the PCI Bus that is directly connected to the 82443BX, depending on the Device Number field. A type 0 Configuration Cycle is generated on PCI if the Bus Number is programmed to 00h and the 82443BX is not the target. If the Bus Number is non-zero a type 1 configuration cycle is generated on PCI or AGP with the Bus Number mapped to AD[23:16] during the address phase.

Device Number.

a Type 1 Configuration cycle this field is mapped to AD[15:11]. During a Type 0 Configuration Cycle this field is decoded and one bit among AD[31:11] is driven to a 1. The 82443BX is always Device Number 0 for the Host-to-PCI bridge entity and Device Number 1 for the Host- AGP entity. Therefore, the 82443BX internally references the AD11 and AD12 pins as corresponding IDSELs for the respective devices dur ing PCI configuration cycles. NOTE: The AD11 and AD12 must not be connected to any other PCI bus device as IDSEL signals.

Function Number.

the configuration registers of a particular function in a multi-function device to be accessed. The 82443BX only responds to configuration cycles with a function number of 000b; all other function number values attempting access to the 82443BX (Device Number = 0 and 1, Bus Number = 0) will generate a master abort.

specified by the other fields in the Configuration Address Register. This field is mapped to AD[7:2] during PCI configuration cycles.

When the Bus Number is programmed to 00h the target of the Configuration Cycle

This field selects one agent on the PCI bus selected by the Bus Number. During

This field is mapped to AD[10:8] during PCIx configuration cycles. This allows

This field selects one register within a particular Bus, Device, and Function as

When this bit is set to 1 accesses to PCI configuration space are

3.1.2 CONFDATA—Configuration Data Register

I/O Address: 0CFCh Default Value: 00000000h Access: Read/Write Size: 32 bits

CONFDATA is a 32 bit read/write window into configuration space. The portion of configuration space that is referenced by CONFDATA is determined by the contents of CONFADD.

Bit Descriptions

31:0

Configuration Data Windo w ( CDW).

CONFDATA I/O space will be mapped to configuration space using the contents of CONFADD.

If bit 31 of CONFADD is 1 any I/O reference that f alls i n the

82443BX Host Bridge Datasheet

3-3

Page 30

3.1.3 PM2_CTL—ACPI Power Control 2 Control Register

I/O Address: 0022h Default Value: 00h Access: Read/Write Size: 8 bits

This register is used to disable both the PCI and AGP arbiters in the 82443BX to prevent any external bus masters from acquiring the PCI or AGP bus. Any currently running PCI cycles will terminate properly.

Accesses to this register are controlled by the Power Management Control Register (Offset 7Ah). When bit 6 of the PMCR is set to ‘1 ’, the ACPI Register at I/O location 002 2h is enable d. When bi t 6 is set to ‘0’, I/O accesses to location 0022h are forwarded to PCI or AGP (if within programmable IO range).

Bit Description

7:1 Reserved

Primary PCI and AGP Arbiter Request Disable (ARB_DIS).

82443BX will not respond to any PCI REQ# signals, AGP requests, or PHOLD# from PIIX4E going active until this bit is set back to 0. Only External AGP and PCI requests are masked from the

arbiters. If the PIIX is in passiv e release mode, masking will not occur until an activ e release i s seen via PHLDA# assertion. This prevents possible deadlock.

ARB_DIS has no effect on AGP side band signals or AGP data transfer requests.

When this bit is set to 1, the

3.2 PCI Configuration Space Access

The 82443BX implementation manifests two PCI devices within a single physical component body:

Device 0 = Host-to-PCI Bridge = PCI bus #0 interface, Main Memory Controller, Graphics

•

Aperture controller, 82443BX specific AGP control registers. Device 1 = Host-to-AGP interface = “Virtual” PCI-to-PCI Bridge, including AGP address

•

space mapping, normal PCI interface, and associated AGP sideband signal control.

Corresponding conf igu ration registers for both devices are mapped as de vices residi ng on PC I (b us

0). Configuration register layout and functionality for the Device #0 should be inspected carefully, as new features added to the 82443BX initiated a reasonable level of change relative to other proliferation’s of the Pentium registers of the 82443BX Device # 1 are based on the normal conf igu ration space template of a PCIto-PCI Bridge as described in the PCI to PCI Bridge Architecture Specification.

Figure 3-1shows the PCI bus hierarchy for the 82443BX). In the PCI bus hierarchy, the primary PCI bus is th e hi gh est level bus in the hiera rchy and is PCI b us #0 . Th e P CI- to -P CI bri d ge function provides access to the AGP/PCI bus 0. This bus is below the primary bus in the PCI bus hierarchy and is represented as PCI Bus #1.

Pro processor AGPsets (i.e. 440FX, 440LX). Configuration

3-4

82443BX Host Bridge Datasheet

Page 31

Figure 3-1. 82443BX PCI Bus Hierarchy

Host Bridge

CPU

82443BX

Host-to-PCI Bridge

PCI Bus #0

Virtual Host-to-PCI Bridge

AGP Device

PCI Bus #1 – AGP

3.2.1 Configuration Space Mechanism Overview

The 82443BX supports two bus interfaces: PCI (referenced as Primary PCI) and AGP (referenced as AGP). The AGP interface is treated as a second PCI bus from the configuration point of view. The following sections describe the configuration space mapping mechanism associated with both buses.

Note: The configuration space for device #1 is controlled by the AGP_DIS bit in the PMCR register.

When the AGP_DIS bit (PMCR[1]) is set to 0, the conf iguration space fo r de vice #1 is enabled, and the registers for device #1 are accessible through the configuration mechanism defined below. When the AGP_DIS bit (PMCR[1]) is set to 1, the configuration space for device #1 is disabled. All configuration cycles (reads and writes) to device #1 of bus 0 will cause the master abort status bit for device #0/ bus 0 to be set. Configuration read cycles will return data of all 1’s. Conf iguration write cycles will have no effect on the registers.

3.2.2 Routing the Configuration Accesses to PCI or AGP

Routing of configuration accesses to AGP is controlled via PCI-to-PCI bridge normal mechanism using information contained within the PRIMARY BUS NUMBER, the SECONDARY BUS NUMBER, and the SUBORDINATE BUS NUMBER registers of the Host-to-AGP internal “virtual” PCI-to-PCI brid ge device. Detailed description of the mechanism for translati ng CPU I/O bus cycles to configuration cycles on one of the two buses is described below.

To distinguish between PCI configuration cycles targeting the two logical device register sets supported in the 82443BX, this document refers to the Host-to- PCI bridge PCI interface as PCI an d the Host- AGP PCI interface as AGP.

82443BX Host Bridge Datasheet

3-5

Page 32

3.2.3 PCI Bus Configuration Mechanism Overview

The PCI Bus defines a slot based "configuration space" that allows each device to contain up to 8 functions with each function containing up to 256 8-bit configuration registers. The PCI specification defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the CPU. Configuration space is supported by a mapping mechanism implemented within the chip-set. The PCI specification defines two mechanisms to access configuration space, Mechanism #1 and Mechanism #2. The 82443BX supports only Mechanism #1.

The configuration access mechanism makes use of the CONFADD Register and CONFDATA Register. To reference a configuration register a Dwor d I/O wr ite c ycle is u sed to p lace a value into CONFADD that specifies the PCI bus, the device on that bus, the function within the device, and a specific configuration register of the device function being accessed. CONFADD[31] must be 1 to enable a configuration cycle. CONFDATA then becomes a window into the four bytes of configuration space specif ied by the contents of CONFADD. Any read or write to CONFD ATA will result in the Host Bridge translating CONFADD into a PCI configuration cycle.

3.2.3.1 Type 0 Access

If the Bus Number field of CONFADD is 0, a Type 0 Configuration cycle is performed on PCI (i.e. bus #0). CONFADD[10:2] is mapped directly to AD[10:2]. The Device Number fi eld of CONFADD is decoded onto AD[31:11]. The Host-to-PCI Bridge entity within the 82443BX is accessed as Device #0 on the PCI bus segment. The Host- /A GP Bridge entity within the 82443BX is accessed as Device #1 on the PCI bus segment. To access Device #2, the 82443BX will assert AD13, for Device #3 will assert AD14, and so forth up to Device #20 for which will assert AD31. Only one AD line is asserted at a time. All device numbers higher than 20 cause a type 0 configuration access with no IDSEL asserted, which will result in a Master Abort.

3.2.3.2 Type 1 Access

If the Bus Number field of CONFADD is non-zero, then a Type 1 Configuration cycle is performed on PCI bus (i.e. bus #0). CONFADD[23:2] is mapped directly to AD[23:2]. AD[1:0] are driven to 01 to indicate a Type 1 Configuration cycle. All other lines are driven to 0.

3.2.4 AGP Bus Configuration Mechanism Overview

This mechanism is compatible with PCI mechanism #1 supported for the PCI bus as defined abo ve . The configuration mechanism is the same for both accessing AGP or PCI-only devices attached to the AGP interface.

3-6

82443BX Host Bridge Datasheet

Page 33

3.2.5 Mapping of Configuration Cycles on AGP

From the AGPset conf iguration perspecti v e, AGP is seen as another PCI bus interface residing on a Secondary Bus side of the “virtual” PCI-to-PCI bridge referred to as the 82443BX Host- AGP bridge. On the Primary bus side, the “virtual” PCI-to-PCI bridge is attached to the B US #0 referred to in this document as the PCI interface. The “virtual” PCI-to-PCI bridge entity is used to map T y pe #1 PCI Bu s Conf i gurati on cy cles on P CI onto Type #0 or Type #1 configuration cycles on the AGP interface.

Type 1 configuration cycles on PCI that have a BUS-NUMBER that matches the SECONDARYBUS-NUMBER of the “virtual” PCI to PCI bridge will be translated into Type 0 configuration cycles on the AGP interf ace. Type 1 configuration cycles on PCI that hav e a BUS-NUMBER that is behind the “virtual” P2P bridge will be translated into Type 1 configuration cycles on the AGP interface.

Note: The PCI bus supports a total of 21 devices by mapping bits 15:11 of the CONFADD to the IDSEL

lines on AD[31:11]. For secondary PCI busses (including the AGP bu s), only 16 devices are supported by mapping bits 15:11 of the CONFADD to the IDSEL lines (AD[31:16]).

To prepare for mapp ing of the configuration cycles on AGP the initialization software will go through the following sequence:

1. Scan all devices residing on the PCI bus (i.e., Bus #0) using Type 0 configuration accesses.

2. For every device residing at bus #0 which implements PCI-to-PCI bridge functionality, it will configure the secondary bus of the bridge with the appropriate number and scan further down the hierarchy. This process will include the configuration of the “virtual” PCI-to-PCI Bridge within the 82443BX used to map the AGP address space in a software specific manner.

82443BX Host Bridge Datasheet

3-7

Page 34

3.3 Host-to-PCI Bridge Registers (Device 0)

Table 3-1 shows the 82443BX configuration space for device #0.

Table 3-1. 82443BX Register Map — Device 0 (Sheet 1 of 2)

Address

Offset

00–01h VID Vendor Identification 8086h RO 02–03h DID Device Identification 7190h/7192h RO 04–05h PCICMD PCI Command Register 0006h R/W 06–07h PCISTS PCI Status Register 0210h/0200h RO, R/WC 08 RID Revision Identification 00/01h/02h RO 09 — Reserved 00h — 0Ah SU BC Sub-Class Code 00h RO 0Bh BCC Base Class Code 06h RO 0Ch — Reserved 00h — 0Dh MLT Master Latency Timer 00h R/W 0Eh HDR Header Type 00h RO 10–13h APBASE Aperture Base Address 00000008h R/W,RO 14–2Bh — Reserved 00h — 2C–2Dh SVID Subsystem Vendor Identification 00h R/WO 2E–2Fh SID Subsystem Identification 00h R/WO 30–33h — Reserved 00h — 34h CAPPTR Capabilities Pointer A0h/00h RO 35–4Fh — Reserved 00h —

50–53h NBXCFG 440BX Configuration 54–56h — Reserved 00h —

57h DRAMC DRAM Control 00S0_0000b R/W 58h DRAMT DRAM Timing 03h R/W 59–5Fh PAM[6:0] Programmable Attribute Map (7 registers) 00h R/W 60–67h DRB[7:0] DRAM Row Boundary (8 registers) 01h R/W 68h FDHC Fixed DRAM Hole Control 00h R/W 69–6Eh MBSC Memory Buffer Strength Control 0000-0000-0000h R/W 6F–70h — Reserved 00h — 71h — Intel Reserved 1Fh — 72h SMRAM System Management RAM Control 02h R/W 73h ESMRAMC Extended System Management RAM Control. 38h R/W 74–75h RPS SDRAM Row Page Size 0000h R/W 76–77h SDRAMC SDRAM Control Register 0000h R/W 78–79h PGPOL Paging Policy Register 00h R/W 7Ah PMCR Power Management Control Register 0000_S0S0b R/W 7B–7Ch SCRR Suspend CBR Refresh Rate Register 0038h R/W 7D–7Fh — Res erved 00h —

Symbol

[0000h]:[00S0_00 00_000S_0S00b]

R/W

3-8

82443BX Host Bridge Datasheet

Page 35

Table 3-1. 82443BX Register Map — Device 0 (Sheet 2 of 2)

Address

Offset

80–83h EAP Error Address Pointer Register 00000000h RO, R/WC 84–8Fh — Reserved 00h — 90h ERRCMD Error Command Register 80h R/W 91–92h ERRSTS Error Status Register 0000h R/WC, RO 93h — Reserved 00h R/W 94–97h — Intel Reserved 00006104h — 98–99h — Intel Reserved 0500h — 9Ah — Intel Reserved 00h — 9B–9Fh — Reserved — —

A0–A3h ACAPID AGP Capability Identifier A4–A7h AGPSTAT AGP Status Register 1F000203h RO

A8–ABh AGPCMD AGP Command Register 00000000h RW AC–AFh — Reserved 00h — B0–B3h AGPCTRL AGP Control Register) 00000000h R/W B4h APSIZE Aperture Size Control Register 00h R/W B5–B7h — Reserved 00h — B8–BBh ATTBASE Aperture Translation Table 00000000h R/W BCh — Reserved — — BDh — Reserved — — BE–BFh — Reser ved 00h — C0–C3h — Intel Reserved 00000000h — C4–C7h — Intel Reserved 00000000h — C8h — Intel Reserved 18h — C9h — Intel Reserved 0Ch — CA–CCh MBFS Memory Buffer Frequency Select 000000h R/W CD–CFh — Reserved 00h — D0–D7h BSPAD BIOS Scratch Pad 00...00h R/W

D8–DFh Intel Reserved 000....000h —

E0–E7h D WT C DRAM Write Thermal Throttling Control 000....000h R/W/L

E8–EFh DRTC DRAM Read Thermal Throttling Control 000....000h R/W/L

F0–F1h BUFFC Buffer Control Register 0000h R/W/L F2–F7h — Intel Reserved 0000F800h — F8–FBh — Intel Reserved 00000F20h — FC–FFh — Intel Reserved 00000000h —

Symbol

00100002h 00000000h

NOTES:

1. The ‘S’ symbol represents the strapping option.

2. Write operations must not be attempted to the Intel Reserved re

82443BX Host Bridge Datasheet

isters.

3-9

Page 36

3.3.1 VID—Vendor Identification Register (Device 0)

Address Offset: 00–01h Default Value: 8086h Attribute: Read Only Size: 16 bits

The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Reg ister uniquely identify an y PCI device. Writes to this register have no effect.

Bit Description

15:0

Vendor Identification Number.

This is a 16-bit value assigned to Intel. Intel VID = 8086h.

3.3.2 DID—Device Identification Register (Device 0)

Address Offset: 02–03h Default Value: 7190h/7192h Attribute: Read Only Size: 16 bits

This 16-bit register combined with the Vendor Identification register uniquely identifies any PCI device. Writes to this register have no effect.

Bit Description

This is a 16 bit value assigned to the 82443BX Host-to-PCI

15:0

Device Identification Number.

Bridge Function #0. 7190h = When the AGP_DIS bit (PMCR[1]) is set to 0, the DID =7190h. 7192h = When the AGP_DIS bit is set to 1, the DID = 7192h.

3-10

82443BX Host Bridge Datasheet

Page 37

3.3.3 PCICMD—PCI Command Register (Device 0)

Address Offset: 04–05h Default: 0006h Access: Read/Write Size 16 bits

This 16-bit register provides basic control over the 82443BX PCI interface ability to respond to PCI cycles. The PCICMD Register enables and disables the SERR# signal, 82443BX response to PCI special cycles, and enables and disables PCI bus master accesses to main memory.

Bit Descriptions

15:10 Reserved.

Fast Back-to-Back.

5 Reserved.

82443BX. 0 = Hardwired to 0.

SERR# Enable (SERRE).

its own SERRE bit to control error reporting for the bus conditions occurred on the A GP b us. Two control bits are used in a logical OR manner to control SERR# pin driver.

1 = If this bit is set to a 1, the 82443BX’s SERR# signal driver is enabled and SERR# is asserted

when an error condition occurs, and the corresponding bit is enabled in the ERRCMD register. The error status is reported in the ERRSTS and PCISTS registers. Also, if this bit is set and the 82443BX’s PCI parity error reporting is enabled by the PERRE bit located in this register, then the 82443BX will report address and data parity errors (when it is potential target).

0 = SERR# is never driven by the 82443BX.

Address/Data Stepping. Parity Error Enable (PERRE).

1 = Enable. Address and data parity errors are reported via SERR# mechanism (if enabled via

SERRE bit).

0 = Disable. Address and data parity errors are not reported via the 82443BX SERR# signal.

(NOTE: Other types of error conditions can be still signaled via SERR# mechanism.)

NOTE: The 82443BX PCI bus interface is still required to generate parity even if parity error reporting is disabled via this bit.

Memory Write and Invalidate Enable.

0 = Hardwired to 0.

Special Cycle Enable.

0 = Hardwired to 0.

Bus Master Enable (BME).

on the PCI Bus. 1 = Hardwired to 1, permitting the 82443BX to function as a PCI Bus master.

Memory Access Enable (MAE).

(DRAM). The 82443BX always allows PCI master access to main memory. 1 = Hardwired to 1.

I/O Access Enable (IOAE).

0 = Hardwired to 0.

Fast bac k-to-back cycles to diff erent PCI targets are not implemented by t he

Note that this bit only controls SERR# for the PCI bus. Device #1 has

Not implemented (hardwired to 0).

Note that the PERR# signal is not implemented by the 82443BX.

The 82443BX never uses this command.

The 82443BX ignores all special cycles generated on the PCI.

The 82443BX does not support disabling of its bus master capability

This bit enables/disables PCI master access to main memory

The 82443BX does not respond to PCI bus I/O cycles.

82443BX Host Bridge Datasheet

3-11

Page 38

3.3.4 PCISTS—PCI Status Register (Device 0)

Address Offset: 06–07h Default Value: 0210h/0200h Access: Read Only, Read/Write Clear Size: 16 bits

PCISTS is a 16-bit status register that reports the occurrence of a PCI master abort and PCI target abort on the PCI bus. PCISTS also indicates the DEVSEL# timing that has been set by the 82443BX hardware for target responses on the PCI bus. Bits [15:12] and bit 8 are read/write clear and bits [10:9] are read only.

Bit Descriptions

Detected Parity Error (DPE).

PERR# is not implemented in the 82443BX.

10:9

6:5 Reserved.

3:0 Reserved.

1 = Indicates 82443BX’s detection of a parity error in the address or data phase of PCI bus

transactions.

0 = Software sets DPE to 0 by writing a 1 to this bit.

Signaled System Error (SSE).

1 = This bit is set to 1 when the 82443BX asserts SERR# for any enabled error condition under

device 0.

0 = Software sets SSE to 0 by writing a 1 to this bit.

Received Master Abort Status (RMAS).

termination of PCI special cycles. 1 = When the 82443BX terminates a PCI bus transaction (82443BX is a PCI master) with an

unexpected master abort, this bit is set to 1.

0 = Software resets this bit to 0 by writing a 1 to it.

Received Target Abort Status (RTAS).

1 = When a 82443BX-initiated PCI transaction is terminated with a target abort, RTAS is set to 1.

The 82443BX also asserts SERR# if enabled in the ERRCMD register.

0 = Software resets RTAS to 0 by writing a 1 to it.

Signaled Target Abort Status (STAS).

0 = Hardwired to a 0

DEVSEL# Timing (DEVT).

82443BX responds as a target on PCI, and indicates the time when a valid DEVSEL# can be sampled by the initiator of the PCI cycle.

01 = Medium (hardwired to 01)

Data Parity Detected (DPD).

errors are still detected and reported on SERR# (if enabled by SERRE and PERRE). 0 = Hardwired to 0

Fast Back-to-Back (FB2B).

transactions on the PCI bus. 0 = Hardwired to 0

Capability List (CLIST).

1 = When the AGP DIS bit (PMCR[1]) is set to 0, this bit is set to 1. 0 = When the AGP DIS bit (PMCR[1]) is set to 1, this bit is set 0.

Note that the function of this bit is not affected by the PERRE bit.

Note that Master abort is the normal and expected

The 82443BX does not generate target abort.

This 2-bit field indicates the timing of the DEVSEL# signal when the

82443BX does not implement the PERR# pin. Howev er, data parity

The 82443BX as a target does not support fast back-to-back

3-12

82443BX Host Bridge Datasheet

Page 39

3.3.5 RID—Revision Identification Register (Device 0)

Address Offset: 08h Default Value: 02h Access: Read Only Size: 8 bits

This register contains the revision number of the 82443BX Function #0. These bits are read only and writes to this register have no effect.

Bit Description

This is an 8-bit value that indicates the revision identification

7:0

Revision Identification Number.

number for the 82443BX Function #0. B-1 = 02h

3.3.6 SUBC—Sub-Class Code Register (Device 0)

Address Offset: 0Ah Default Value: 00h Access: Read Only Size: 8 bits

This register contains the Sub-Class Code for the 82443BX Function #0. This code is 00h indicating a Host Bridge device. The register is read only.

Bit Description

7:0

Sub-Class Code (SUBC).

the 82443BX falls. The code is 00h indicating a Host Bridge.

This is an 8-bit value that indicates the category of Bridge into which

3.3.7 BCC—Base Class Code Register (Device 0)

Address Offset: 0Bh Default Value: 06h Access: Read Only Size: 8 bits

This register contains the Base Class Code of the 82443BX Function #0. This code is 06h indicating a Bridge device. This register is read only.

Bit Description

7:0

Base Class Code (BASEC).

82443BX. This code has the value 06h, indicating a Bridge device.

This is an 8-bit value that indicates the Base Class Code for the

82443BX Host Bridge Datasheet

3-13

Page 40

3.3.8 MLT—Master Latency Timer Register (Device 0)

Address Offset: 0Dh Default Value: 00h Access: Read/Write Size: 8 bits

This register controls the amount of time that 82443BX can burst data on the PCI Bus as a PCI master. The MLT[2:0] bits are reserved and assumed to be 0 when determining the Count Value.

Bit Description

Master Latency Timer Count Value for PCI Bus Access.

7:3

2:0 Reserved.

the amount of time the 82443BX, as a PCI bus master, can burst data on the PCI Bus. The default value of MLT is 00h and disables this function. For example, if the MLT is programmed to 18h, then the value is 24 PCI clocks.

MLT is an 8-bit register that controls

3.3.9 HDR—Header Type Register (Device 0)

Offset: 0Eh Default: 00h Access: Read Only Size: 8 bits

This register identifies the header layout of the configuration space.

Bit Descriptions

7:0

Header Type (HEADT).

on this field.

This read only field always returns 0 when read. Writes have no affect

3.3.10 APBASE—Aperture Base Configuration Register (Device 0)

Offset: 10–13h Default: 00000008h Access: Read/Write, Read Only Size: 32 bits

The APBASE is a normal PCI Base Address register that is used to request the base of the Graphics Aperture. The normal PCI Configuration mechanism defines the base address configuration register such that only a fixed amount of space can be requested (dependent on which bits are hardwired to “0” or behave as hardwired to “0”). To allow for flexibility (of the aperture) an additional register called APSIZE is used as a “back-end” register to control which bits of the APBASE will behave as hardwired to “0”. This register will be programmed by the 82443BX specific BIOS code that will run before any of the generic configuration software is run.

Note: Bit 9 of the NBXCFG register is used to prevent accesses to the aperture range before this register

is initialized by the configuration software and appropriate translation table structure has been established in the main memory.

3-14

82443BX Host Bridge Datasheet

Page 41

Bit Description

Upper Programmable Base Address bits (R/W).

31:28

27:22

21:4

2:1

selected via lower bits 27:4. Default = 0000b

Lower “Hardwired”/Pr ogrammable Base Address bits.

as a programmable depending on the contents of the APSIZE register as defined below:

27 26 25 24 23 22 Aperture Siz e

r/w r/w r/w r/w r/w r/w 4 MB r/w r/w r/w r/w r/w 0 8 MB r/w r/w r/w r/w 0 0 16 MB r/w r/w r/w 0 0 0 32 MB r/w r/w 0 0 0 0 64 MB r/w 0 0 0 0 0 128 MB 0 0 0 0 0 0 256 MB Bits 27:22 are controlled by the bits 5:0 of the APSIZE register in the following manner: If bit APSIZE[5]=0 then APBASE[27]=0 and if APSIZE[5]=1 then APBASE[27]=r/w (read/write).

The same applies correspondingly to other bits. Default for APSIZE[5:0]=000000b forces default APBASE[27:22] =000000b (i.e., all bits respond

as “hardwired” to 0). This provides a default to the maximum aperture size of 256 MB. The 82443BX specific BIOS is responsible for selecting smaller size (if required) before PCI configuration software runs and establishes the system address map.

Hardwired to “0”. Prefetchable (RO).

prefetchable ( i.e., the device returns all bytes on reads regardless of the byte enables), and the 82443BX may merge processor writes into this range without causing errors.

Type (RO).

address range defined by the upper bits of this register can be located anywhere in the 32-bit address space.

Memory Space Indicator (RO).

This forces minimum aperture size selected by this register to be 4MB.

This bit is hardwired to “1” to identify the Graphics Aperture range as a

These bits determine addressing type and they are hardwired to “00” to indicate that

Hardwired to “0” to identify aperture range as a memory range.

These bits are used to locate the range size

These bits behave as a “hardwired” or

3.3.11 SVID—Subsystem Vendor Identification Register (Device 0)

Offset: 2C–2Dh Default: 0000h Access: Read/Write Once Size: 16 bits

Bit Description

Subsystem Vendor ID (R/WO).

15:0

default value is 00h. This field should be programmed during boot-up. After this field is written once, it becomes read only.

82443BX Host Bridge Datasheet

This value is used to identify the vendor of the subsystem. The

3-15

Page 42

3.3.12 SID—Subsystem Identification Register (Device 0)

Offset: 2E–2Fh Default: 0000h Access: Read/Write Once Size: 16 bits

Bit Description

15:0

Subsystem ID (R/WO).

00h. This field should be programmed during boot-up. After this field is written once, it becomes read only.

This value is used to identify a particular subsystem. The default value is

3.3.13 CAPPTR—Capabilities Pointer Register (Device 0)

Offset: 34h Default: A0h/00h Access: Read Only Size: 8 bits

The CAPPTR provides the of f set that is the po inter to the location where the AG P normal registers are located.

Bit Description

Pointer to the start of AGP normal register block.

7:0

A0h = When the AGP_DIS bit (PMCR[1]) is set to 0, the value in this field is A0h. 00h = When the AGP_DIS bit (PMCR[1]) is set to 1, this field is set to 00h.

3.3.14 NBXCFG—NB X Configuration Register (Device 0)

Offset: 50–53h Default: bits 31–16: 0000h

bits 15–0: 00S0-0000-000S-0S00b Access: Read/Write, Read Onl Size: 32 bits

for strapping options

3-16

Bit Description

SDRAM Row Without ECC.

When reading a SDRAM row (DIMM) which is none-ECC, the 82 443BX drives the ECC data lines

31:24

23:19 Reserved.

during the first data transfer in a burst read. 0 = ECC components are populated in this row. The 82443BX will not drive the ECC signals. 1 = ECC components are not populated in this row. The 82443BX will drive the ECC lines in the

first read data transferred when this row is addressed.

Host Bus Fast Data Ready Enable (HBFDRE).

0 = Assertion of DRAM data on host bus occurs one clock after sampling snoop results. (default)

1 = Assertion of DRAM data on host bus occurs on the same clock the snoop result is being

sampled. This mode is faster by one clock cycle.

Bit[n] of this 8 bit array corresponds to row[n] of the SDRAM array.

82443BX Host Bridge Datasheet

Page 43

Bit Description

ECC - EDO static Drive mode.

0 = Normal mode of operation (default).

1 = ECC signals are always driven. This mode is used in a mobile system. EDO components are

used, but ECC components are not populated in any of the DRAM rows.

IDSEL_REDIRECT.

base design. For CPU initiated configuration cycles to PCI, Device 1 which are targeted to the 82443BX’s host to AGP bridge:

0 = When set to ‘0’ (default), IDSEL1 (or AD12) is allocated to this bridge. The external AD12 is

never activated. CPU initiated configuration cycles to BUS0, DEVICE7 are targeted a PCI bus

14 Intel Reserved.

13:12

8:7

device that its IDSEL input is connected to IDSEL7 (AD18).

1 = When set to ‘1’, IDSEL7 (or AD18) is allocated to this bridge. Since it is internal in the

82443BX, the external AD18 is never activated. CPU initiated configuration cycles to BUS0, DEVICE7 are targeted a PCI bus device that its IDSEL input is connected to IDSEL1 (AD12). In some 430TX based systems, this is connected to PIIX4E.

Note that CPU initiated configuration cycles to other PCI buses or other devices are normally mapped and are not affected.

WSC# Handshake Disable.

Processor mode where external IOAPIC is used, this bit should be set to ‘0’ (default). Setting this bit to ‘0’, enables the WSC# handshake mechanism.

Host/DRAM Frequency.

is set by an external strapping option at reset. These bits are also used to select the required refresh rate. These bits apply to both SDRAM and EDO, with t he e x ception that the sett ing ‘00’ for 100 MHz is illegal for an EDO system.

00 = 100 MHz 01 = Reserved 1 0 = 66 MHz 11 = Reserved

AGP to PCI Access Enable.

transaction pending: 1) this bit is set to 1 and the 82443BX allows AGP to PCI traffic, or 2) this bit is set to 0 (default) and the 82443BX blocks AGP to PCI traffic. The AGP to PCI traffic must not target the ISA bus.

1 = Enable 0 =Disable

PCI Agent to Aperture Access Disable.

the PCI side. 1 = Disable 0 = Enable (default). If this bit is “0” (default) and bit 9 = 1, accesses to the aperture are enabled

for the PCI side.

Note: This bit is don’t care if bit 9 of this register = 0.

Aperture Access Global Enable.

(CPU, PCI or AGP) before aperture range is established by the configuration software and appropriate translation table in the main DRAM has been initialized. Default is “0”. It must be set after system is fully configured for aperture accesses.

1 = Enable. Note that this bit globally controls accesses to the aperture. Once enabled, bit 10

provides the next level of control for accesses originated from the PCI side.

0 = Disable

DRAM Data Integrity Mode (DDIM) (R/W).

modes. 00 = Non-ECC (Byte-Wise Writes supported) (Default) 01 = EC-only - Error Checking with No correction 10 = ECC Mode (Error Checking/Correction) 11 = ECC Mode with hardware scrubbing enabled

This is a programmable option to make the 82443BX compatible with 430TX

In the Uni-Processor mode, this bit should be set to ‘1’. In the Dual-

These bits are used to determine the host and DRAM frequency. Bit 13

When PHLDA# is active or there is an outstanding passive release

This bit is used to prevent access to the aperture from

This bit is used to prevent access to the aperture from any port

These bits select one of 4 DRAM data integrity

82443BX Host Bridge Datasheet

3-17

Page 44

Bit Description

1:0 Reserved.

ECC Diagnostic Mode Enable (EDME) (R/W).

1 = Enable. When this bit is set to 1, the 82443BX will enter ECC Diagnostic test mode and the

4 Reserved.

82443BX forces the MECC[7:0] lines to 00h for all writes to memor y. During reads, the read MECC[7:0] lines are compared against internally generated ECC. Recognized errors are indicated via the ERRSTS register as in normal ECC operation.

0 = Normal operation mode (default).

MDA Present (MDAP).

This bit is used to indicate the presence of a secondary monochrome adapter on the PCI bus, while the primary graphics controller is on the AGP bus. This bit works in conjunction with the VGA_EN bit (Register 3E, bit 3 of device 1) as follows:

VGA_EN MDAP Description

0 X

The MDA ranges are a subset of the VGA ranges as follows: Memory: 0B0000h–0B7FFFh I/O: 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh

USWC Write Post During I/O Bridge Access Enable (UWPIO) (R/W).

1 = Enable. Host USWC writes to PCI memory are posted. 0 = Disable. P osting of USWC is not allowed.

In-Order Queue Depth (IOQD) (RO).

deassertion of the CPURST#. It indicates the depth of the Pentium queue (i.e., level of Pentium Pro processor bus pipelining).

1 = In-order queue = maximum. If A7# is sampled “1” (i.e,. undriven on the Pe ntium Pro

processor bus), the depth of the Pentium Pro processor bus in-order queue is configured to the maximum allowed by the Pentium Pro processor protocol (i.e., 8). However, the actual maximum supported by the 82443BX is 4, and it is controlled by the 82443BX’s Pentium Pro processor interface logic using the BNR# signaling mechanism.

0 = A7# is sampled asserted (i.e., “0”). The depth of the Pentium Pro processor bus in-order

queue is set to 1 (i.e., no pipelining support on the Pentium Pro processor bus).

NOTE: During reset, A7# can be driven either by the 82443BX or by an e xternal source as defined by the strapping option on the MAB11# pin.

All VGA cycles are sent to PCI.

are not claimed by the 82443BX.

All VGA cycles are sent to AGP.

claimed by the 82443BX and forwarded to the AGP bus.

All VGA cycles are sent to AGP, except

(or the aliased ranges defined below). PCI master writes in the VGA range (outside of the MDA range) are claimed by the 82443BX and forwarded to AGP. PCI and AGP master read/writes to the MDA range are ignored by the 82443BX.

This bit reflects the value sampled on A7# on the

PCI master cycles to the VGA range

PCI master writes to VGA range are

for cycles in the MDA range

Pro processor bus in-order

3-18

82443BX Host Bridge Datasheet

Page 45

3.3.15 DRA MC— DRAM Control Register (Device 0)

Address Offset: 57h Default Value: 00S0_0000b Access: Read/Write Size: 8 bits

Bit Description

7:6 Reserved.

This bit is set by an external strapping option. The

4:3

2:0

Module Mode Configuration (M MCONFIG).

combination of this bit and the SDRAMPWR bit (SDRAMC register) determine the functioning of the CKE signals as defined as follows:

SDRAMPWR MMC ONFIG CKE Operation

0 0 3 DIMM, CKE[5:0] driven, self-refresh entry staggered.

X 1 3 DIMM, CKE0 only, self-refresh entry not staggered. SDRAM

1 0 4 DIMM, GCKE only, self-refresh entry staggered. SDRAM

Under MMCONFIG mode, the AGP must be disabled.

NOTE: DRAM Type (DT).

set to 00, EDO timings are used for all cycles to main memory. When set to 01, SDRAM timings are used for all cycles to memory. When set to 10, timings for memory cycles accommodate Registered SDRAMs. For registered SDRAM timings, all address and control lines to the SDRAMs are assumed to be registered, while memory data and ECC bits are not registered. EDO, SDRAM and Registered SDRAM cannot be mixed within a system.

00 = EDO 01 = SDRAM 10 = Registered SDRAM 11 = Reserved

When PCIRST# assertion occurs during POS/STR, this bit is not reset to ‘0’.

NOTE: DRAM Refresh Rate (DRR).

selected by this field. Disabling the refresh cycle (000) results in the eventual loss of DRAM data. Changing DRR value will reset the refresh request timer. This field is used in conjunction with the SDRAM frequency bits in the NBXCFG register to determine the correct load value for the refresh timer.

000 = Refresh Disabled 001 = 15.6 us 010 = 31.2 us 011 = 62.4 us 100 = 124.8 us 101 = 249.6 us 110 = Reserved 111 = Reserved NOTE: When PCIRST# assertion occurs during POS/STR, this bit is not reset to ‘0’.

This field indicates the DRAM type used to populate the entire array. When

SDRAM dynamic power down available.

dynamic power down unavailable.

The DRAM refresh rate is adjusted according to the frequency

82443BX Host Bridge Datasheet

3-19

Page 46

3.3.16 D RAMT— DRAM Timing Register (Device 0)

Address Offset: 58h Default Value: 03h Access: Read/Write Size: 8 bits

This 8-bit register controls main memory DRAM timings. Refer to the DRAM section for details regarding the DRAM timings programmed in this register.

Bit Description

7:2 Reserved.

EDO RASx# Wait State (RWS).

is asserted for row misses. This provides one clock of additional MAX[13:0] setup time to RASx# assertion. This bit does not affect page misses since the MAX[13:0] lines are setup several cloc ks

in advance of RAS# assertion for page misses. 0 = 1 tASR 1 = 2 tASR

EDO CASx# Wait State (CWS).

assertion of the first CASx# for page hit cycles. This allows one additional clock of MA setup time to the CASx# for the leadoff page hit cycle. Page miss and row miss timings are not affected by

this bit. 0 = 1 Tasc 1 = 2 Tasc

When RWS = 1, one additional wait state is inserted before RAS#

When CWS = 1, one additional wait state is inserted before the

3.3.17 PAM[6:0]—Programmable Attribute Map Registers (Device 0)

Address Offset: 59h (PAM0) – 5Fh (P AM6) Default Value: 00h Attribute: Read/Write

The 82443BX allows programmab le memory attr ib ut es on 13 Legacy memory segments of va rious sizes in the 640 KB to 1 MB address range. Seven Programmable Attribute Map (PAM) Registers are used to support these features. Cacheability of these areas is controlled via the MTRR registers in the Pentium Pro processor. Two bits are used to specify memory attributes for each memory segment. These bits apply to bo th h ost accesses and PCI initiator accesses to th e PAM areas. These attributes are:

RE Read Enable. When RE = 1, the host read accesses to the corresponding memory segment

are claimed by the 82443BX and directed to main memory. Conversely, when RE = 0, the host read accesses are directed to PCI.

WE Write Enable. When WE = 1, the host write accesses to the corresponding memory

segment are claimed by the 824 43BX and directed to main memo ry. Conversely, when WE = 0, the host write accesses are directed to PCI.

The RE and WE attributes permit a memory segment to be Read Only, Write Only, Read/Write, or disabled. For example, if a memory segment has RE = 1 and WE = 0, the segment is Read Only.

Each PAM Register controls two regions, typically 16 KB in size. Each of these reg ions has a 4- bit field. The four bits that control each region have the same encoding and are defined in Table 3-2.

3-20

82443BX Host Bridge Datasheet

Page 47

Table 3-2. Attribute Bit Assignment

Bits [7, 3] Reserved

xx00

xx01

xx10

xx11

Bits [6, 2] Reserved

Bits [5, 1]WEBits [4, 0]

Description

Disabled.

directed to PCI. The 82443BX does not respond as a PCI target for any read or write access to this area.

Read Only.

are forwarded to PCI for termination. This write protects the corresponding memory segment. The 82443BX will respond as a PCI target for read accesses but not for any write accesses.

Write Only.

are forwarded to the PCI for termination. The 82443BX will respond as a PCI target for write accesses but not for any read accesses.

Read/Write.

memory. Both read and write cycles from the host are claimed by the 82443BX and forwarded to DRAM. The 82443BX will respond as a PCI target for both read and write accesses.

DRAM is disabled and all accesses are

Reads are forwarded to DRAM and writes

Writes are forwarded to DRAM and reads

This is the normal operating mode of main

As an example, consider a BIOS that is implemented on the expansion bus. During the initialization process, the BIOS can be shadowed in main memory to increase the system performance. When BIOS is shadowed in main memory, it should be copied to the same address location. To shadow the BIOS, the attributes for that address range should be set to write only. The BIOS is shadowed by f irst doing a read o f that address. This read is forwar ded to the expan sion bus. The host then does a write of the same address, which is directed to main memory. After the BIOS is shadowed, the attrib utes for that mem ory area are set to read only so that all writes are forw arded to the expansion bus. Table 3-3 shows the PAM registers and the associated attribute bits:

Table 3-3. PAM Registers and Associated Memory Segments

PAM Reg Attribute Bits Memory Segment Comments Offset

PAM0[3:0] Reserved 59h PAM0[7:4] R R WE RE 0F0000h – 0FFFFFh BIOS Area 59h PAM1[3:0] R R WE RE 0C0000h – 0C3FFFh I SA Add-on BIOS¹ 5Ah PAM1[7:4] R R WE RE 0C4000h – 0C7FFFh I SA Add-on BIOS¹ 5Ah PAM2[3:0] R R WE RE 0C8000h – 0CBFFFh ISA Add-on BIOS¹ 5Bh PAM2[7:4] R R WE RE 0CC000h – 0CFFFFh ISA Add-on BIOS¹ 5Bh PAM3[3:0] R R WE RE 0D0000h – 0D3FFFh I SA Add-on BIOS 5Ch PAM3[7:4] R R WE RE 0D4000h – 0D7FFFh I SA Add-on BIOS 5Ch PAM4[3:0] R R WE RE 0D8000h – 0DBFFFh ISA Add-on BIOS 5Dh PAM4[7:4] R R WE RE 0DC000h – 0DFFFFh ISA Add-on BIOS 5Dh PAM5[3:0] R R WE RE 0E0000h – 0E3FFFh BIOS Extension 5Eh PAM5[7:4] R R WE RE 0E4000h – 0E7FFFh BIOS Extension 5Eh PAM6[3:0] R R WE RE 0E8000h – 0EBFFFh BIOS Extension 5Fh PAM6[7:4] R R WE RE 0EC000h – 0EFFFFh BIOS Extension 5Fh

NOTE:

1. The C0000h to CFFFFh segment can be used for SMM space if enabled by the SMRAM register

82443BX Host Bridge Datasheet

3-21

Page 48

DOS Application Area (00000h–9FFFh)

The DOS area is 640 KB and i t is fur ther di vid ed in to tw o p arts. Th e 512 KB area at 0 to 7 FFFFh i s always mapped to the main memory controlled by the 82443BX, while the 128 KB address range from 080000 to 09FFFFh can be mapped to PCI or to main DRAM. By default this range is mapped to main memory and can be declared as a main memory hole (accesses forwarded to PCI) via 82443BX’s FDHC configuration register.

Video Buffer Area (A0000h–BFFFFh)

This 128 KB area is not controlled by attribute bits. The host-initiated cycles in this region are always forwarded to either PCI or AGP unless this range is accessed in SMM mode. Rout i n g of

accesses is controlled by the Legacy VGA control mechanism of the “virtual” PCI-to-PCI bridge device embedded within the 82443BX.

This area can be programmed as SMM area via the SMRAM register. When used as a SMM space this range can not be accessed from PCI or AGP.

Expansion Area (C0000h–DFFFFh)

This 128 KB area is divided into eight 16 KB segments which can be assigned with different attributes via PAM control register as defined by Table 3-3.

Extended System BIOS Area (E0000h–EFFFFh)

This 64 KB area is divided into four 16 KB segments which can be assigned with different attributes via PAM control register as defined by the Table 3-3.

System BIOS Area (F0000h–FFFFFh)

This area is a single 64 KB segment which can be assigned with different attributes via PAM control register as defined by the Table 3-3.

3.3.18 DRB[0:7]—DRAM Row Boundary Registers (Device 0)

Address Offset: 60h (DRB0) – 67h (DRB7) Default Value: 01h Access: Read/Write Size: 8 bits/register

The 82443BX supports 8 physical rows of DRAM. The width of a row is 64 bits. The DRAM Row Boundary Registers define up per and lower addresses for each DR AM row. Contents of these 8-bit registers represent the boundary addresses in 8 MB granularity. For example, a value of 01h indicates 8 MB.

60h DRB0 = Total memory in row0 (in 8 MB) 61h DRB1 = Total memory in row0 + row1 (in 8 MB) 62h DRB2 = Total memory in row0 + row1 + row2 (in 8 MB) 63h DRB3 = Total memory in row0 + row1 + row2 + row3 (in 8 MB) 64h DRB4 = Total memory in row0 + row1 + row2 + row3 + row4 (in 8 MB) 65h DRB5 = Total memory in row0 + row1 + row2 + row3 + row4 + row5 (in 8 MB) 66h DRB6 = Total memory in row0 + row1 + row2 + row3 + row4 + row5 + row6 (in 8 MB) 67h DRB7 = Total memory in row0 + row1 + row2 + row3 + row4 + row5 + row6 + row7

(in 8 MB)

3-22

82443BX Host Bridge Datasheet

Page 49

The DRAM array can be configured with single or double-sided DIMMs using 2MX8, 4Mx16, or 8Mx8 parts. The array also supports x4 width DRAM components on registered DIMMs. Each register defines an address range that will cause a particular CS# line (or RAS# in the EDO case) to be asserted (e.g., if the first DRAM row is minus 8 MB, then accesses within the 0 to 8 MByte range will cause CSx0#/RASx0# to be asserted). The DRAM Row Boundary (DRB) Registers are programmed with an 8-bit upper address limit value. This upper address limit is compared to bits [30:23] of the requested address, for each row, to determine if DRAM is being targeted.

Note: DRAM is selected only if address[31:30] are zero.

Bit Description

7:0

Row Boundary Address.

determine the upper address limit of a particular row (i.e., DRB minus previous DRB = row size). NOTE: When PCIRST# assertion occurs during POS/STR, these bits are not reset to ‘01h’.

This 8-bit value is compared against address lines A[30:23] to

Row Boundary Address

These 8 bit values represent the upper address limits of the eight rows (i.e., this row minus previous row = row size). Unpopulated rows have a value equal to the previous row (row size = 0). DRB7 reflects the maximum amount of DRAM in the system. The top of memory is determined by the value written into DRB7.

Note: The 82443BX supports a maximum of 1 GB of DRAM using registered SDRAM DIMMs. (an

example of this configuration is 4 double-sided registered DIMMs using 16Mx4 parts). As an example of a general purpose configuration where eight physical rows are configured for

either single-sided or double-sided DIMMs, the memory array would be configured like the one shown in Figure 3-2. In this configuration, the 82443BX drives eight CS# signals directly to the DIMM rows. If single-sided DIMMs are populated, the even CS# signals are used and the odd CS#s are not connected. If double-sided DIMMs are used, all four CS# signals are used per DIMM.

Figure 3-2. SDRAM DIMMs and Corresponding DRB Registers

CSA7#/CSB7# DIMM3 – Back CSA6#/CSB6#

CSA5#/CSB5# CSA4#/CSB4#

DIMM3 – Front

DIMM2 – Back DIMM2 – Front

DRB7 DRB6

DRB5 DRB4

CSA3#/CSB3# CSA2#/CSB2#

CSA1#/CSB1# CSA0#/CSB0#

82443BX Host Bridge Datasheet

DIMM1 – Back DIMM1 – Front

DIMM0 – Back DIMM0 – Front

DRB3 DRB2

DRB1 DRB0

3-23

Page 50

The following 2 examples describe how the DRB Registers are programmed for cases of singlesided and double-sided DIMMs on a motherboard.

Example #1 Single-sided DIMMs

Assume a total of 16 MB of DRAM are required using single-sided 1MB x 64 DIMMs. In this configuration, two DIMMs are required.

DRB0 = 01h populated (1 DIMM, 8 Mbyte this row) DRB1 = 01h empty row DRB2 = 02h populated (1 DIMM, 8 Mbyte this row) DRB3 = 02h empty row DRB4 = 02h empty row DRB5 = 02h empty row DRB6 = 02h empty row DRB7 = 02h empty row

Example #2 Mixed Single-/Do uble-sided DIMMs

As another example, consider a system that is initially shipped with 8 MB of memory using a 1M x 64 DIMM and that rest of the memory array should be upgradable up to a maximum supported memory of 200 MB. This can be handled b y furt her popu latin g the array wi th one 16M x 64 si nglesided DIMM (one row) and one 8M x 64 double-sided DIMM (two rows), yielding a total of 200 MB of DRAM. The DRB Registers are programmed as follows:

DRB0 = 01h populated with 8 MB, 1MB x 64 single-sided DIMM DRB1 = 01h empty row DRB2 = 05h populated with 32 MB, 1/2 of 8M x 64 DIMM DRB3 = 09h populated with 32 MB, the other 1/2 of 8M x 64 DIMM DRB4 = 19h populated with 128 MB, 16M x 64 single-sided DIMM DRB5 = 19h empty row DRB6 = 19h empty row DRB7 = 19h empty row

3.3.19 F DHC—Fixed DRAM Hole Control Register (Device 0)

Address Offset: 68h Default Value: 00h Access: Read/Write Size: 8 bits

This 8-bit register controls 2 fixed DRAM holes: 512 KB – 640 KB and 15 MB –16 MB.

Bit Description

Hole Enable (HEN).

enabled hole are passed on to PCI. PCI cycles matching an enabled hole will be ignored by the 82443BX (no DEVSEL#). NOTE: A selected hole is not remapped.

7:6

5:0 Reserved.

00 = None 01 = 512 KB–640 KB (128 KB bytes) 10 = 15 MB – 16 MB (1 MB byte) 11 = Reserved

This field enables a memory hole in DRAM space. Host cycles matching an

3-24

82443BX Host Bridge Datasheet

Page 51

3.3.20 MBSC—Memor y Buffer Strength Control Register (Device 0)

Address Offset: 69–6Eh Default Value: 000000000000h Access: Read/Write Size: 48 bits

This register programs the various DRAM interface signal buffer strengths, based on non-mixed memory configurations of DRAM type (EDO or SDRAM), DRAM density (x8, x16, or x32), DRAM technology (16MB or 64 MB), and rows populated. Note that x4 DRAM may only be supported when used on registered DIMMs.

Note: The choice of 100 MHz or 66 MHz buffer is independent of b us fr equency. It is possible to select a

100 MHz memory buffer even though the bus frequency is 66 MHz (and vice versa).

Bit Description

47:40 Reserved

This field sets the buffer strength f or

39:38

37:36

35:34

33:32

MAA[13:0], WEA#, SRASA#, SCASA# Buffer Strengths.

the MAA[13:0], WEA#, SRASA#, SCASA# pins. 00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (66 MHz & 100 MHz)

MAB[12:11, 9:0]# & MAB[13,10], WEB#, SRASB#, SCASB# Buffer Strengths.

the buffer strength for MAB[12:11, 9:0]# & MAB[13,10], WEB#, SRASB#, SCASB# pins. Note that the address’s MAB# are inverted copies of MAA, with the exception of MAB[13,10].

00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (66 MHz & 100 MHz)

MD [63:0] Buffer Strength Control 2. 4 DIMM FET Configuration:

connected to DIMM2 and DIMM3. The buffer strength is programmable based on the SDRAM load in detected in 82443BX.

3 DIMM & 4 DIMM non-FET Configuration:

value as MD[63:0] Buffer Strength Control 1. This buff er strength is programmable based upon the SDRAM load detected in all DIMM connectors.

00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (100 MHz only)

MD [63:0] Buffer Strength Control 1. 4 DIMM FET Configuration:

connected to DIMM0 and DIMM1. The buffer strength is programmable based upon the SDRAM load in detected in (Low) by the 82443BX.

3 DIMM & 4 DIMM non-FET Configurations:

the SDRAM load detected in all DIMM connectors. 00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (100 MHz only)

DIMM slots 2&3

This field sets the buffer strength for the MD[63:0] path that is

. This path is enabled when FENA is asserted (High) by the

This field should be programmed to the same

This field sets the buffer strength for the MD[63:0] path that is

DIMM slots 0&1.

This path is enabled when FENA is asserted

The buffer strength is programmable based upon

This field sets

82443BX Host Bridge Datasheet

3-25

Page 52

31:30

29:28

27:26

25:24

23:22

21:20

Bit Description

MECC [7:0] Buffer Strength Control 2. 4 DIMM FET Configuration:

connected to DIMM2 and DIMM3 The buffer strength is programmab le based upon t he SDRAM ECC load detected in by the 82443BX.

3 DIMM & 4 DIMM non-FET Configurations:

value as MECC[7:0] Buffer Strength Control 1. This buffer strength is programmable based upon the SDRAM load detected in all DIMM connectors.

00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (100 MHz only)

MECC [7:0] Buffer Strength Control 1. 4 DIMM FET Configuration:

connected to DIMM0 and DIMM1. The buffer strength is programmable based upon the SDRAM ECC load detected in (High) by the 82443BX.

3 DIMM & 4 DIMM non-FET Configuration:

the SDRAM ECC load detected in all DIMM slots. 00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (100 MHz only)

CSB7#/CKE5 Buffer Strength.

00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (66 MHz & 100 MHz)

CSA7#/CKE3 Buffer Strength.

00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (66 MHz & 100 MHz)

CSB6#/CKE4 Buffer Strength.

00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (66 MHz & 100 MHz)

CSA6#/CKE2 Buffer Strength.

00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (66 MHz & 100 MHz)

CSA5#/RASA5#, CSB5#/RASB5# Buffer Strength.

CSA5#/RASA5#, CSB5#/RASB5# pins. 0 = 1x (66 MHz & 100 MHz) 1 = 2x (66 MHz & 100 MHz)

CSA4#/RASA4#, CSB4#/RASB4# Buffer Strength.

CSA4#/RASA4#, CSB4#/RASB4# pins. 0 = 1x (66 MHz & 100 MHz) 1 = 2x (66 MHz & 100 MHz)

CSA3#/RASA3#, CSB3#/RASB3# Buffer Strength.

CSA3#/RASA3#, CSB3#/RASB3# pins. 0 = 1x (66 MHz & 100 MHz) 1 = 2x (66 MHz & 100 MHz)

This field sets the buffer strength for the MECC[7:0] path that is

DIMM slots 2&3

This field sets the buffer strength for the MECC[7:0] path that is

DIMM slots 0&1.

. This path is enabled when FENA is deasserted (High)

This field should be programmed to the same

This path is enabled when FENA is deasserted

The buffer strength is programmable based upon

This field sets the buffer strength for CSB7#/CKE5 pins.

This field sets the buffer strength for CSA7#/CKE3 pins.

This field sets the buffer strength for CSB6#/CKE4 pins.

This field sets the buffer strength for CSA6#/CKE2pins.

This field sets the buffer strength for the

3-26

82443BX Host Bridge Datasheet

Page 53

Bit Description

CSA2#/RASA2#, CSB2#/RASB2# Buffer Strength.

13:12

11:10

9:8

7:6

5:4

3:2

1:0

CSA2#/RASA2#, CSB2#/RASB2# pins. 0 = 1x (66 MHz & 100 MHz) 1 = 2x (66 MHz & 100 MHz)

CSA1#/RASA1#, CSB1#/RASB1# Buffer Strength.

CSA1#/RASA1#, CSB1#/RASB1# pins. 0 = 1x (66 MHz & 100 MHz) 1 = 2x (66 MHz & 100 MHz)

CSA0#/RASA0#, CSB0#/RASB0# Buffer Strength.

CSA0#/RASA0#, CSB0#/RASB0# pins. 0 = 1x (66 MHz & 100 MHz) 1 = 2x (66 MHz & 100 MHz)

DQMA5/CASA5# Buffer Strength.

pins. 00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (66 MHz only)

DQMA1/CASA1# Buffer Strength.

pin. 00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (66 MHz & 100 MHz)

DQMB5/CASB5# Buffer Strength.

pin. 00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (66 MHz only)

DQMB1/CASB1# Buffer Strength.

pin. 00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (66 MHz only)

DQMA[7:6,4:2,0]/CASA[7:6,4:2,0]# Buffer Strength.

DQMA[7:6]/CASA[7:6]#, DQMA[4:2]/CASA[4:2]#, and the DQMA[0]/CASA[0]# pins. 00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (66 MHz & 100 MHz)

CKE1/GCKE Buffer Strength.

00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (66 MHz & 100 MHz)

CKE0/FENA Buffer Strength.

00 = 1x (66 MHz & 100 MHz) 01 = Reserved (Invalid setting) 10 = 2x (66 MHz & 100 MHz) 11 = 3x (66 MHz & 100 MHz)

This field sets the buffer strength for the DQMA5/CASA5#

This field sets the buffer strength for the DQMA1/CASA1#

This field sets the buffer strength for the DQMB5/CASB5#

This field sets the buffer strength for the DQMB1/CASB1#

This field sets the buffer strength for the CKE1 pin.

This field sets the buffer strength for the CKE0/FENA pin.

This field sets the buffer strength for the

82443BX Host Bridge Datasheet

3-27

Page 54

3.3.21 SMRAM—System Management RAM Control Register (Device 0)

Address Offset: 72h Default Value: 02h Access: Read/Write Size: 8 bits

The SMRAMC register controls how accesses to Compatible and Extended SMRAM spaces are treated. The Open, Close, and Lock bits function only when G_SMRAME bit is set to a 1. Also, the OPEN bit must be reset before the LOCK bit is set.

Bit Description

7 Reserved

When D_OPEN=1 and D_LCK=0, the SMM space DRAM is made

When D_CLS = 1 SMM space DRAM is not accessible to data

When D_LCK is set to 1 then D_OPEN is reset to 0 and D_LCK,

If G_SMRAME is set to a 1 and H_SMRAM_EN is set to

This field programs the location

2:0

SMM Space Open (D_OPEN).

visible even when SMM decode is not active. This is intended to help BIOS initialize SMM space.

Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time. When D_LCK is set to a 1, D_OPEN is reset to 0 and becomes read only.

SMM Space Closed (D_CLS).

references, even if SMM decode is active. Code references may still access SMM space DRAM. This will allow SMM software to reference "through" SMM space to update the display even when

SMM is mapped over the VGA range. Software should ensure that D_OPEN=1 and D_CLS=1 are not set at the same time.

SMM Space Locked (D_LCK).

D_OPEN, H_SMRAM_EN, TSEG_SZ, TSEG_EN and DRB7 become read only. D_LCK can be set to 1 via a normal configuration space write but can only be cleared by a power-on reset. The combination of D_LCK and D_OPEN provide convenience with security . The BIOS can use the

D_OPEN function to initialize SMM space and then use D_LCK to "lock down" SMM space in the future so that no application software (or BIOS i tself) can violate the integrity of SMM space, even if the program has knowledge of the D_OPEN function.

Global SMRAM Enable (G_SMRAME).

0, then Compatible SMRAM functions are enabled, providing 128 KB of DRAM accessible at the A0000h address while in SMM (ADS# with SMM decode). To enable Extended SMRAM function

this bit has be set to 1. Refer to the section on SMM for more details. Once D_LCK is set, this bit becomes read only.

Compatible SMM Space Base Segment (C_BASE_SEG) (RO).

of SMM space. "SMM DRAM" is not remapped. It is simply "made visible" if the conditions are right to access SMM space, otherwise the access is forwarded to PCI.

010 = Hardwired to 010 to indicate that the 82443BX supports the SMM space at

A0000h–BFFFFh.

3-28

82443BX Host Bridge Datasheet

Page 55

3.3.22 ESMRAMC—Extended System Management RAM Control Register (Device 0)

Address Offset: 73h Default Value: 38h Access: Read/Write Size: 8 bits

The Extended SMRAM register controls the configuration of Extended SMRAM space. The Extended SMRAM (E_SMRAM) memory provides a write-back cacheable SMRAM memory space that is above 1 Mbyte.

Bit Descri

Controls the SMM memory space location (i.e above 1 Mbyte or

This bit is forced to ‘1’ by 82443BX. This bit is forced to ‘1’ by 82443BX. This bit is forced to ‘1’ by 82443BX.

Selects the size of the TSEG memory block, if enabled. This memory is

2:1

H_SMRAM_EN (H_SMRAME).

below 1 Mbyte). 1 = When G_SMRAME is 1 and H SMRAME is set to 1, the High SMRAM memory space is

enabled, the Compatible SMRAM memory is disabled, and accesses in the 0A0000h to

5 4 3

0FFFFFh range are forwarded to PCI, while SMRAM accesses from 100A0000h to 100FFFFFh are remapped to DRAM address A0000h to FFFFFh

0 = When G SMRAME is set to a 1 and H SMRAM EN is set to 0, then the Compatible SMRAM

space is enabled.

Once D_LCK is set, this bit becomes read only.

E_SMRAM_ERR (E_SMERR).

1 = This bit is set when CPU accesses the defined memory ranges in Extended SMRAM (High

Memory and T-segment) while not in SMM space and with the D-OPEN bit = 0.

0 = It is software’s responsibility to clear this bit. The software must write a 1 to this bit to clear it.

SMRAM_Cache (SM_CACHE). SMRAM_L1_EN (SM_L1). SMRAM_L2_EN (SM_L2). TSEG_SZ[1:0] (T_SZ).

taken from the top of DRAM space (i.e., TOM - TSEG_SZ), which is no longer claimed by the memory controller (all accesses to this space are sent to the PCI bus if TSEG_EN is set). The physical address for the extended SMRAM memory appears is from (256M + TOM - TSEG_SZ) to (256M + TOM). This address is remapped to DRAM address (TOM - TSEG_SZ) to TOM. This field decodes as follows:

00 = (TOM–128KB) to TOM 01 = (TOM–256KB) to TOM 10 = (TOM–512KB) to TOM 11 = (TOM–1MB) to TOM Once D_LCK is set, this bit becomes read only.

TSEG_EN (T_EN).

additional SMRAM memory) for Extended SMRAM space only. When G_SMRAME =1 and TSEG_EN = 1, the TSEG is enabled to appear in the appropriate physical address space. Once D_LCK is set, this bit becomes read only.

Enabling of SMRAM memory (TSEG, 128 KB, 256 KB, 512 KB or 1 MB of

tion

82443BX Host Bridge Datasheet

3-29

Page 56

3.3.23 RPS—SDRAM Row Page Size Register (Device 0)

Address Offset: 74h–75h Default Value: 0000h Access: Read/Write Size: 16 bits

This register sets the row page size for SDRAM only. For EDO memory, the page size is fixed at 2 KB.

Bit Description

Each pair of bits in this register indicate the page size used for one row of DRAM.

15:0

Page Size (PS).

The encoding of the two bit fields.

Bits[1:0] Page Size

00 2 KB 01 4 KB 10 8 KB 11 Reserved

RPS bits Corresponding DRB register

1:0 DRB[0], row 0 3:2 DRB[1], row 1 5:4 DRB[2], row 2 7:6 DRB[3], row 3 9:8 DRB[4], row 4 11:10 DRB[5], row 5 13:12 DRB[6], row 6 15:14 DRB[7], row 7

3.3.24 SDRAMC—SDRAM Control Register (Device 0)

Address Offset: 76h–77h Default Value: 00h Access: Read/Write Size: 16 bits

Bit Description

15:10 Reserved

9:8

Idle/Pipeline DRAM Leadoff Timing (IPDLT).

when bits 9:8 are set to 01. All other settings are illegal.

Adds a clock delay to the lead-off clock count

3-30

82443BX Host Bridge Datasheet

Page 57

Bit Description

7:5

SDRAM Mode Select (SMS).

SDRAMs. These special modes are intended for initialization at power up.

SMS Mode

000 001

010

011

100

101 110 111 Note: BIOS must take into consideration MAB inversion when programming for 3 and 4 DIMM.

SDRAMPWR.

configurations. For a 3 DIMM configuration, SDRAMPWR should be set to ‘0’. For a 4 DIMM configuration, SDRAMPWR should be set to ‘1’. In this case the 82443BX drives a single CKE signal (GCKE). The combination of SDRAMPWR and MMCONFIG (DRAMC register) determine

the functioning of the CKE signals. Refer to the DRAMC register (Section 3.3.15, “DRAMC— DRAM Control Register (Device 0)” on page 3-19) for more details.

Note: When PCIRST# assertion occurs during POS/STR, these bits are not reset to 0.

Leadoff Command Timing (LCT).

(SRASx#, SCASx# and WEx#) and CSx# are considered valid on leadoffs for CPU cycles. 0 = 4 CS# Clock 1 = 3 CS# Clock The LCT Bit should be initialized by BIOS as recommended below:

CAS# Latency (CL).

sampled by the SDRAMs and when the 82443BX samples read data from the SDRAMs. If a given row is populated with a registered SDRAM DIMM, an extra clock is inserted between the read command the when the 82443BX samples read data. For a registered DIMM with CL=2,

this bit should be set to 1. 0 = 3 DCLK CAS# latency. 1 = 2 DCLK CAS# latency.

SDRAM RAS# to CAS# Delay (SRCD).

Activate command to a read or write command. 0 = 3 clocks will be inserted between a row activate command and either a read or write

1 = 2 clocks will be inserted between a row activate and either a read or write command.

SDRAM RAS# Precharge (SRP).

0 = 3 clocks of RAS# precharge. 1 = 2 clocks of RAS# precharge.

Normal SDRAM Operation. NOP Command Enable

Command on the SDRAM interface.

All Banks Precharge Enable

Banks Precharge Command on the SDRAM interface.

Mode Register Set Enable

register set command on the SDRAM interface. The Command is driven on the MAx[13:0] lines. MAx[2:0] must always be driven to 010 for burst of 4 mode. MA3 must be driven to 1 for interleave wrap type. MAx4 needs to be driven to the value programmed in the CAS# Latency bit. MAx[6:5] should always be driven to 01. MAx[12:7] must be driven to 000000. BIOS must calculate and drive the correct host address for each row of memory such that the correct command is driven on the MAx[12:0] lines.

CBR Enable

SDRAM interface.

Reserved. Reserved. Reserved.

The SDRAMPWR bit controls how the CKE signals are driven for different DRAM

• Desktop platforms running at 100 MHz should leave the LCT bit set to its default value of 0.

• Desktop platforms running at 66 MHz should leave the LCT bit set to its default value of 0, if load on either MAA or MAB signals is > 9. Otherwise, set the LCT bit to 1, if load on both MAA and MAB is ≤ 9.

• Mobile platforms will be run at 66MHz and should set the LCT bit to 1.

This bit controls the number of CLKs between when a read command is

command.

These bits allow the 82443BX to drive various commands to the

(default)

. In this mode all CPU cycles to SDRAM result in NOP

. In this mode all CPU cycles to SDRAM result in an All

. In this mode all CPU cycles to SDRAM result in a mode

. In this mode all CPU cycles to SDRAM result in a CBR cycle on the

These bits control when the SDRAM command pins

This bit controls the number of DCLKs from a Row

This bit controls the number of DCLKs for RAS# precharge.

82443BX Host Bridge Datasheet

3-31

Page 58

3.3.25 PGPOL—Paging Policy Register (Device 0)

Address Offset: 78–79h Default Value: 0000h Access: Read/Write Size: 16 bits

Bit Description

Banks per Row (BPR).

corresponds to row 7 while bit 8 corresponds to row 0. These bits are defined only for SDRAM systems and define whether the corresponding row has a two bank implementation or a four

15:8

7:5 Reserved.

4 Intel Reserved.

3:0

bank implementation. Those with two banks (bit=0) can hav e up to two pages open at an y gi v en time. Those with four banks (bit=1) can have up to four pages open at any time. Note that the bits referencing empty rows are ‘don’t care’.

0 = 2 banks 1 = 4 banks

DRAM Idle Timer (DIT).

will remain in the idle state before prechar ging all pages. This field is used for both EDO and SDRAM memory systems.

0000 = 0 clocks 0001 = 2 clocks 0010 = 4 clocks 0011 = 8 clocks 0100 = 10 clocks 0101 = 12 clocks 0110 = 16 clocks 0111 = 32 clocks 1XXX = Infinite (pages are not closed for idle condition).

Each bit in this field corresponds to one row of the memory array. Bit 15

This field determines the number of clocks that the DRAM controller

3-32

82443BX Host Bridge Datasheet

Page 59

3.3.26 PMCR—Power Management Control Register (Device 0)

Address Offset: 7Ah Default Value: 0000_S0S0b Access Read/Write Size 8 Bits

Bit Description

Power Do wn SDRAM Enable (PDSE).

1 = Enable. When PDSE=1, an SDRAM row in idle state will be issued a power down

command. The SDRAM row will exit power down mode only when there is a request to access this particular row.

0 = Disable

ACPI Control Register Enable (SCRE).

1 = Enable. The ACPI control register in the 82443BX is enabled, and all CPU cycles to IO

address 0022h are handled by the 82443BX and are not forwarded to PCI.

0 = Disable (default). All CPU cycles to IO address 0022h are passed on to the PCI bus.

Suspend Refresh Type (SRT).

during Power On Suspend (POS/STR) or Suspend to RAM modes. SRT has no effect on SDRAM refresh.

1 = Self refresh mode 0 = CBR fresh mode NOTE: When PCIRST# assertion occurs during POS/STR, this bit is not reset to ‘0’.

Normal Refresh Enable (NREF_EN).

following a POS/STR state. After coming out of reset the software must set this bit before doing an access to memory.

1 = Enable 0 = Disable

Quick Start Mode (QSTART) (RO).

1 = Quick start mode of operation is enabled for the processor. This mode is entered using a

strapping option that is sampled by the 82443BX and the CPU during reset. This register bit is Read Only and a configuration write to it is ignored.

Gated Clock Enable (GCLKEN).

82443BX when a AGPset “IDLE” state occurs. This happens when the 82443BX detects an idle state on all its buses.

1 = Enable 0 = Disable

AGP Disable (AGP_DIS).

ignored. 1 = Disable. The AGP interface and the clocks of AGP associated logic are permanently

disabled. This mode is entered using a strapping option that is sampled by the 82443BX during reset.

0 = Enable

CPU reset without PCIRST enable (CRst_En).

reset without an incoming PCIRST#. This option allows the reset of the processor when the system is coming out of POS state. Defaults to ‘0’ upon PCIRST# assertion.

1 = Enable 0 = Disable NOTE: When PCIRST# assertion occurs during POS/STR, this bit is not reset to ‘0’.

This register bit is Read Only and a configuration write to it is

This bit determines what type of EDO DRAM refresh is used

This bit is used to enable normal refresh operation

GCLKEN enables internal dynamic clock gating in the

This bit enables the 82443BX to assert CPU

82443BX Host Bridge Datasheet

3-33

Page 60

3.3.27 SCRR—Suspen d CBR Refresh Rate Register (Device 0)

Address Offset: 7Bh–7Ch Default Value: 0038h Access Read/Write Size 16 Bits

Bit Description

15:13 Reserved.

SRRAEN bit is cleared to its default

11:0

Suspend CBR refresh Rate Auto Adjust Enable (SRRAEN).

during cold reset only. It is not affected by PCIRST# during resume from suspend. 0 = Disable (default). Indicates that the suspend CBR refresh rate is not updated by the 82443BX

hardware to track the system operating conditions. In this case, it is expected that BIOS will set the SRR to reflect the worst case operating conditions so that minimum refresh rate will be provided.

1 = Enable. Indicates that the 82443BX hardware adjusts the suspend refresh rate according to

system operating conditions by comparing the number of OSCCLKs in a given time. This mode allows the system to dynamically adjust the refresh rate and thus minimize suspend power consumption while guaranteeing required refresh rate.

Suspend CBR Refresh Rate (SRR).

OSCCLK rising edges. When it expires, a suspend CBR refresh request is triggered. This bit field may be loaded by BIOS to reflect the desirable refresh rate. In addition, the 82443BX will update it automatically, when the above SRRAEN = 1. In either case, the register is accessible for read and write operation at all times.

• This 12-bit field provides a dynamic range greater than the maximum CBR refresh rate that is supported of 249.6uSEC.

• SRR bit field is cleared to its default during cold reset only. It is not affected by PCIRST# during resume from suspend.

• The default value of this register is 038h, or 56 decimal. It represents a 15.5uS time between refreshes with the slowest corner OSCCLK cycle time of 270nS.

The rate is loaded into the counter which counts down on

3-34

82443BX Host Bridge Datasheet

Page 61

3.3.28 EAP—Error Address Pointer Register (Device 0)

Address Offset: 80–83h Default Value: 00000000h Access Read Only, Read/Write-Clear Size 32 Bits

Bit Description

Error Address Pointer (EAP) (RO).

of which an error (single bit or multi-bit error) has occurred. Note that this field represents the

31:12

11:2 Reserved.

address of the first error occurrence after bits 1:0 ha v e been cleared b y soft ware . Once bits 1:0 are set to a value different than 00b, as a result of an error, this bit field is locked and doesn't change as a result of a new error.

Multiple Bit Error (MBE) (R/WC).

and the address has been logged in bits 31:12. The EAP register is locked until the CPU clears this bit by writing a 1. Software uses bits 1:0 to detect whether the logged error address is for Single or Multi bit error, since both Single and Multiple Error bits of the Error Status register can be set. Once software completes the error processing, a value of ‘1’ is written to this bit field to clear the value (back to 0) and unlock the error logging mechanism.

Note: Any ECC errors received during initialization should be ignored.

Single Bit Error (SBE) (R/WC).

1 = Indicates that a single bit ECC error has occurred, and the address has been logged in bits

31:12. The EAP register is locked until the CPU clears this bit by writing a 1.

Note: Any ECC errors received during initialization should be ignored.

This field is used to store the 4 KB block of main memory

This bit indicates that a multi-bit ECC error has occurred,

82443BX Host Bridge Datasheet

3-35

Page 62

3.3.29 ERRCMD—Error Command Register (Device 0)

Address Offset: 90h Default Value: 80h Access: Read/Write Size: 8 bits

This 8-bit register controls the 82443BX responses to v arious system errors. The actual assertion of SERR# is enabled via the PCI Command register.

Bit Description

SERR# on AGP Non-Snoopable Access Outside of Graphics Aperture.

bit 10 of ERRSTS registers transitions from 0 to 1 (during an AGP access to the address outside

of the graphics aperture) then an SERR# assertion event will be generated. 1 = Enable (default). 0 = Disable.

SERR# on Invalid AGP DRAM Access.

outside the graphics aperture and outside the main DRAM range (i.e., in 640 KB – 1 MB range or above top of memory) are invalid. When this bit is set, bit 9 of the ERRSTS will be set and SERR# will be asserted, read accesses are not directed to main memory or the aperture range.

1 = Enable. 0 = Disable reporting of this condition via SERR#.

SERR# on Access to Invalid Graphics Aperture Translation Tabl e Entry.

82443BX sets bit 8 of the ERRSTS and asserts SERR# following a read or write access to an invalid entry in the Graphics Aperture Translation Table residing in main memory.

1 = Enable. 0 = Disable reporting of this condition via SERR#.

SERR# on Receiving Target Abort.

1 = Enable. The 82443BX asserts SERR# on receiving a target abort on either the PCI or AGP. 0 = Disable. The 82443BX does not assert SERR# on receipt of a target abort.

SERR# on Detected Thermal Throttling Condition.

1 = Enable. The 82443BX asserts SERR# when thermal throttling condition is detected for either

the read or the write function.

0 = The 82443BX does not assert SERR# for thermal throttling.

SERR# Assertion Mode.

1 = SERR# is a level mode signal. Systems that connect SERR# to EXTSMI# for error reporting

should set this bit to 1.

0 = SERR# is asserted for 1 PCI clock (normal PCI mode). (default)

SERR# on Receiving Multiple-Bit ECC/Parity Error.

SERR# when it detects a multiple-bit error reported by the DRAM controller. For systems not supporting ECC this bit must be disabled.

1 = Enable. 0 = Disable. Note: Any ECC errors received during initialization should be ignored.

SERR# on Receiving Single-bit ECC Error.

when it detects a single-bit ECC error. For systems not supporting ECC, this bit must be disabled.

1 = Enable. 0 = Disable. Note: Any ECC errors received during initialization should be ignored.

AGP non-snoopable READ accesses to locations

When enabled, the 82443BX asserts

When enabled, the 82443BX asserts SERR#

When enabled and

When enabled, the

3-36

82443BX Host Bridge Datasheet

Page 63

3.3.30 ERRSTS—Error Status Register (Device 0)

Address Offset: 91–92h Default Value: 0000h Access: Read Only, Read/Write Clear Size: 16 bits

This 16-bit register is used to report error conditions via the SERR# mechanism. SERR # is generated on a zero to one transition of any of these flags (if enabled by the ERRCMD register).

Bit Description

15:13 Reserved.

Read thermal Throttling Condition.

1 = Read thermal throttling condition occurred. 0 = Software writes “1” to clear this bit. Default=0

Write Thermal Throttling Condition.

1 = Write thermal throttling condition occurred. 0 = Software writes “1” to clear this bit. Default=0

7:5

3:1

AGP non-snoopable access outside of Graphics Aperture.

1 = AGP access occurred to the address that is outside of the graphics aperture range. 0 = Software writes “1” to clear this bit. Default=0

Inv alid AGP non-snoopable DRAM read access (R/WC).

1 = AGP non-snoopable READ access was attempted outside of the graphics aperture and

outside of main memory (i.e,. in 640 KB – 1 MB range or above top of memory).

0 = Software must write a “1” to clear this status bit.

Access to Invalid Graphics Aperture Translation Table Entry (AIGATT) (R\WC).

1 = An invalid t ranslat ion tab le ent ry was returned in response to a graphics aperture read or write

access.

0 = Software must write a “1” to clear this bit.

Multi-bit First Error (MBFRE) (RO).

which the first multi-bit error occurred. A simple binary encoding is used to indicate the row containing the multi-bit error . When an error is detected, this field is updated and the MEF bit is set. This field will then be locked (no further updates) until the MEF flag has been reset. If MEF is 0, the value in this field is undefined.

000 = Row 0 001 = Row 1

... 111 = Row 7

Multiple-bit ECC (uncorrectable) Error Flag (MEF) (R/WC).

1 = Memory data transfer had an uncorrectable error(i.e., multiple-bit error). When enabled, a

multiple bit error is reported by the DRAM controller and propagated to the SERR# pin, if enabled by bit 1 in the ERRCMD register.

0 = BIOS writes a 1 to clear this bit and unlock the MBFRE field. (Default = 0).

Single-bit First Row Error (SBFRE) (RO).

in which the first single-bit error occurred. A simple binary encoding is used to indicate the row containing the single-bit error. When an error is detected, this field is updated and SEF is set. This field is then locked (no further updates) until the SEF flag has been reset. If SEF is 0, the value in this field is undefined.

000 = Row 0 001 = Row 1

... 111 = Row 7

Single-bit (correctable) ECC Error Flag (SEF) (R/WC).

1 = Memory data transfer had a single-bit correctable error and the corrected data was sent for the

access. When ECC is enabled, a single bit error is reported and propagated to the SERR# pin, if enabled by bit 0 in the ERRCMD register.

0 = BIOS writes a 1 to clear this bit and unlock the SBFRE field.

This field contains the encoded value of the DRAM row in

This field contains the encoded value of the DRAM row

82443BX Host Bridge Datasheet

3-37

Page 64

3.3.31 ACAPID—AGP Capability Identifier Register (Device 0)

Address Offset: A0–A3h Default Value: 00100002h/00000000h Access: Read Only Size: 32 bits

This register provides normal identifier for AGP capability.

Bit Description

31:24 Reserved

This field provides a major revision n umber of A GP specification to

These bits provide a minor revision number of AGP specification

AGP capability is the first and the last capability described via the

23:20

19:16

15:8

7:0

Major AGP Re vision Number.

which this version of the 82443BX conforms. When the AGP DIS bit (PMCR[1]) is set to 0, this number is set to value of “0001b” (i.e., implying Rev 1.x). When the AGP DIS bit (PMCR[1]) is set to 1, This number is set to “0000b”.

Minor AGP Revision Number.

to which this version of 82443BX conforms. This number is hardwired to value of “0000” (i.e., implying Rev x.0). Together with major revision number this field identifies 82443BX as an AGP REV 1.0 compliant device.

Next Capability Pointer.

capability pointer mechanism. 0s = Hardwired to 0s to indicate the end of the capability linked list.

AGP Capability ID.

AGP DIS bit (PMCR[1]) is set to 0, this field has a value of 0000_0010b assigned by the PCI SIG. When the AGP DIS bit (PMCR[1]) is set to 1, this field has a value of 00h.

This field identifies the linked list item as containing AGP registers. When the

3.3.32 AGPSTAT—AGP Status Regist er (Device 0)

Address Offset: A4–A7h Default Value: 1F000203h Access: Read Only Size: 32 bits

This register reports AGP compliant device capability/status.

Bit Description

31:24

23:10 Reserved

8:2 Reserved

1:0

AGP Maximum Request Queue Depth (RO).

maximum of 32 outstanding AGP command requests can be handled by the 82443BX.

AGP Side Band Addressin g Supported.

addressing. It is hardwired to 1.

AGP Data Transfer Type Supported (R/W).

data transfer mode and bit 1 identifies if AGP compliant device supports 2x data transfer mode. Configuration software will update this field by setting only one bit that corresponds to the capability of AGP master (after that capability has been verified by accessing the same functional register within the AGP masters configuration space).

00 = Not allowed 01 = 1x data transfer mode supported 10 = 2x data transfer mode supported 11 = (default) NOTE: The selected data transfer mode apply to both AD bus and SBA bus.

This field is hardwired to 1Fh to indicate a

This bit indicates that the 82443BX supports side band

Bit 0 identifies if AGP compliant device supports 1x

3-38

82443BX Host Bridge Datasheet

Page 65

3.3.33 AGPCMD—AGP Command Register (Device 0)

Address Offset: A8–ABh Default Value: 00000000h Access: Read/Write Size: 32 bits

This register provides control of the AGP operational parameters.

Bit Description

31:10 Reserved.

AGP Side Band Enable.

1 = Enable. 0 = Disable.

AGP Enable.

cycle. Any AGP operations received while this bit is set to 1 is serviced even if this bit is reset to 0. If this bit transitions from a 1 to a 0 on a clock edge in the middle of an SBA command being delivered in 1X mode the command will be issued. When this bit is set to 1 the 82443BX will respond to AGP operations delivered via PIPE#, or to operations delivered via SBA if the AGP Side Band Enable bit is also set to 1.

The AGP parameters in the AGPCMD and AGPCTRL registers must be set prior to setting this bit ‘1’. With the exception of the GTLB_ENABLE (bit 7, AGPCTRL), and ATTBASE register (offset B8h), which can be modified dynamically.

1 = Enable. 0 = Disable.

7:2 Reserved.

AGP Data Transfer Rate.

desired data transfer rate (Bit 0 for 1X, Bit 1 for 2X). The same bit must be set on both master and target. Configuration software will update this field by setting only one bit that corresponds to the capability of AGP master (after that capability has been verified by accessing the same functional register within the AGP masters configuration space.)

1:0

00 = default 01 = 1x data transfer rate. 10 = 2x data transfer rate. 11 = Illegal NOTE: This field applies to AD and SBA buses.

When disabled, the 82443BX ignores all AGP operations, including the sync

This bit enables the side band addressing mechanism.

One (and only one) bit in this field must be set to indicate the

82443BX Host Bridge Datasheet

3-39

Page 66

3.3.34 AGPCTRL—AGP Control Register (Device 0)

Address Offset: B0–B3h Default Value: 00000000h Access: Read/Write Size: 32 bits

This register provides for additional control of the AGP interface.

Bit Description

31:16 Reserved.

Snoopable Writes In Order With AGP Reads Disable (AGPDCD).

82443BX maintains ordering between snoopable write cycles and AGP reads. When set to 1, the 82443BX handles the AGP reads and snoopable writes as independent streams.

AGPDCD AGPRSE Description

14 Reserved

12:8 Reserved

6:0 Reserved.

(Bit 15) (Bit 13)

0 0 DWB is visible to AGP reads. DWB flushes only when address hit. 0 1 Illegal. 1 0 Illegal 1 1 DWB flushes when write to AGP occurs

Graphics Aperture Write-AGP Read Synchronization Enable (AGPRSE).

the 82443BX will ensure that all writes posted in the Global Write Buffer to the Graphics Aperture are retired to DRAM before the 82443BX will initiate any CPU-to-AGP cycle. This can be used to ensure synchronization between the CPU and AGP master. The AGPDCD bit description defines the interaction between the AG PRS E bit and the AGPDCD bit.

1 = Enable 0 = Disable (Default)

GTLB Enable (and GTLB Flush Control).

1 = Enable. Normal operations of the Graphics Translation Lookaside Buffer. 0 = Disable (default). The GTLB is flushed by clearing the valid bits associated with each entry .

When set to 0 (default), the

When this bit is set

3-40

82443BX Host Bridge Datasheet

Page 67

3.3.35 APSIZE—Aperture Size Register (Device 0)

Address Offset: B4h Default Value: 00h Access: Read/Write Size: 8 bits

This register determines the effective size of the Graphics Aperture used for a particular 82443BX configuratio n. This re gist er can be updated by t he 82443BX- specific BIOS configuration sequence before the PCI normal bus enumeration sequence takes place. If the register is not updated, a default value selects an aperture of maximum size (i.e., 256 MB). The size of the table that will correspond to a 256 MB aperture is not practical for most applications and, therefore, these bits must be programmed to a smaller practical value that forces adequate addr ess range to be requested via the APBASE register from the PCI configuration software.

Bit Description

7:6 Reserved.

Graphics Aperture Size (APSIZE) (R/W).

bits in APBASE[27:22] of the Aperture Base configuration register. When a particular bit of this field is “0”, it forces the similarly ordered bit in APBASE[27:22] to behave as “hardwired” to 0. When a particular bit of this field is set to “1”, it allows corresponding bit of the APBASE[27:22] to be read/ write accessible. Only the following combinations are allowed:

11 1111 = 4 MB 11 1110 = 8 MB 11 1100 = 16 MB

5:0

11 1000 = 32 MB 11 0000 = 64 MB 10 0000 = 128 MB 00 0000 = 256MB Default for APSIZE[5:0]=000000b forces default APBASE[27:22] =000000b (i.e., all bits respond as

“hardwired” to 0). This provides maximum aperture size of 256 MB. As another example, programming APSIZE[5:0]=111000b hardwires APBASE[24:22]=000b and while enabling APBASE[27:25] as read/write programmable.

Each bit in APSIZE[5:0] operates on similarly ordered

3.3.36 ATTBASE—Aperture Translation Table Base Register (Device 0)

Address Offset: B8–BBh Default Value: 00000000h Access: Read/Write Size: 32 bits

This register provides the starting address of the Graphics Aperture Translation Table base located in the main DRAM. The ATTBASE register may be dynamically changed.

Note: The address provided via ATTBASE is 4KB aligned.

Bit Description

Aperture Translation Table Base Address.

31:12

11:0 Reserved.

respectively. This field contains a pointer to the base of the translation table used to map memory space addresses in the aperture range to addresses in main memory.

82443BX Host Bridge Datasheet

Bits 31:12 correspond to address bits 31:12,

3-41

Page 68

3.3.37 MBFS—Memory Buffer Frequency Select Register (Device 0)

Address Offset: CA–CCh Default Value: 000000h Access: Read/Write Size: 24 bits

The settings in this register enable the 100 MHz or 66 MHz buf fers for each of th e follo wing signal groups.

Note: The choice of 100 MHz or 66 MHz buffer is independent of b u s freq uency. It is possible to select a

100 MHz memory buffer even though the bus frequency is 66 MHz (and vice versa).

Bit Description

23 Res erved

This bit enables

MAA[13:0], WEA#, SRASA#, SCASA# (100 MHz/66 MHz buffer select bit).

either 100 MHz or 66 MHz buffers for MA A[13:0], WEA#, SRASA#, SCASA #. 0 = 66 MHz 1 = 100 MHz

MAB[12:11, 9:0]# & MAB[13,10], WEB#, SRASB#, SCASB# (100 MHz/66 MHz buffer select

This bit enables either 100 MHz or 66 MHz buffers for MAB[12:11, 9:0]# & MAB[13,10],

bit).

WEB#, SRASB#, SCASB#. Note that the address’s MABx# are inverted copies of MAA, with the exception of MAB[13,10].

0 = 66 MHz 1 = 100 MHz

MD [63:0] (100 MHz/66 MHz buffer select bit [Control 2]).

66 MHz buffers for MD [63:0] [Control 2]. (Refer to the corresponding MBSC register for programming details).

0 = 66 MHz 1 = 100 MHz

MD [63:0] (100 MHz/66 MHz buffer select bit [Control 1]).

66 MHz buffers for MD [63:0] [Control 1]. (Refer to the corresponding MBSC register for programming details).

0 = 66 MHz 1 = 100 MHz

MECC [7:0] (100 MHz/66 MHz buffer select bit [Control 2]).

66 MHz buffers for MECC [7:0] [Control 2]. (Refer to the corresponding MBSC register for programming details).

0 = 66 MHz 1 = 100 MHz

MECC [7:0] (100 MHz/66 MHz buffer select bit [Control 1]).

66 MHz buffers for MECC [7:0] [Control 1]. (Refer to the corresponding MBSC register for programming details).

0 = 66 MHz 1 = 100 MHz

CSB7#/CKE5 (100 MHz/66 MHz buffer select bit).

buffers for CSB7#/CKE5. 0 = 66 MHz 1 = 100 MHz

This bit enables either 100 MHz or

This bit enables either 100 MHz or 66 MHz

3-42

82443BX Host Bridge Datasheet

Page 69

Bit Description

CSA7#/CKE3 (100 MHz/66 MHz buffer select bit).

buffers for CSA7#/CKE3. 0 = 66 MHz 1 = 100 MHz

CSB6#/CKE4 (100 MHz/66 MHz buffer select bit).

buffers for CSB6#/CKE4. 0 = 66 MHz 1 = 100 MHz

CSA6#/CKE2 (100 MHz/66 MHz buffer select bit).

buffers for CSA6#/CKE2. 0 = 66 MHz 1 = 100 MHz

CSA5#/RASA5#, CSB5#/RASB5# (100 MHz/66 MHz buffer select bit).

100 MHz or 66 MHz buffers for CSA5#/RASA5#, CSB5#/RASB5#. 0 = 66 MHz 1 = 100 MHz

CSA4#/RASA4#, CSB4#/RASB4# (100 MHz/66 MHz buffer select bit).

100 MHz or 66 MHz buffers for CSA4#/RASA4#, CSB4#/RASB4#. 0 = 66 MHz 1 = 100 MHz

CSA3#/RASA3#, CSB3#/RASB3# (100 MHz/66 MHz buffer select bit).

100 MHz or 66 MHz buffers for CSA3#/RASA3#, CSB3#/RASB3# 0 = 66 MHz 1 = 100 MHz

CSA2#/RASA2#, CSB2#/RASB2# (100 MHz/66 MHz buffer select bit).

100 MHz or 66 MHz buffers for CSA2#/RASA2#, CSB2#/RASB2#.

0 = 66 MHz 1 = 100 MHz

CSA1#/RASA1#, CSB1#/RASB1# (100 MHz/66 MHz buffer select bit).

100 MHz or 66 MHz buffers for CSA1#/RASA1#, CSB1#/RASB1#.

0 = 66 MHz 1 = 100 MHz

CSA0#/RASA0#, CSB0#/RASB0# (100 MHz/66 MHz buffer select bit). This bit enables either 100 MHz or 66 MHz buffers for CSA0#/RASA0#, CSB0#/RASB0#.

0 =66 MHz 1 = 100 MHz

DQMA5/CASA5# (100 MHz/66 MHz buffer select bit).

MHz buffers for DQMA5/CASA5#.

0 = 66 MHz 1 = 100 MHz

DQMA1/CASA1# (100 MHz/66 MHz buffer select bit).

MHz buffers for DQMA1/CASA1#.

0 = 66 MHz 1 = 100 MHz

DQMB5/CASB5# (100 MHz/66 MHz buffer select bit).

MHz buffers for DQMB5/CASB5#.

0 = 66 MHz 1 = 100 MHz

This bit enables either 100 MHz or 66 MHz

This bit enables either

This bit enables either 100 MHz or 66

82443BX Host Bridge Datasheet

3-43

Page 70

Bit Description

DQMB1/CASB1# (100 MHz/66 MHz buffer select bit).

MHz buffers for DQMB1/CASB1#.

0 = 66 MHz 1 = 100 MHz

DQMA[7:6,4:2,0]/CASA[7:6,4:2,0]# (100 MHz/66 MHz buffer select bit).

either 100 MHz or 66 MHz buffers for DQMA[7:6]/CASA[7:6]#, DQMA[4:2]/CASA[4:2]#, and the DQMA[0]/CASA[0]#.

0 = 66 MHz 1 = 100 MHz

CKE1/GCKE (100 MHz/66 MHz buffer select bit).

buffers forCKE1.

0 = 66 MHz 1 = 100 MHz

CKE0/FENA (100 MHz/66 MHz buffer select bit).

buffers for CKE0/FENA.

0 = 66 MHz 1 = 100 MHz

This bit enables either 100 MHz or 66 MHz

This bit enables either 100 MHz or 66

This bit enables

3.3.38 BSPAD—BIOS Scratch Pad Register (Device 0)

Address Offset: D0–D7h Default Value: 0000-0000-0000-0000h Access: Read/Write Size: 64 bits

This register provides 8 bytes general purpose read/write registers for the BIOS to perform the configuration routine. The 8244 3BX will provide this 8 b yte register in the PCI configur ation space of the 82443BX device0 on bus 0. The registers in this range will be defined as read/write and will be initialized to all 0’ s after PCIRST#. The BIOS will can access these re gisters through the normal PCI configuration register mechanism, accessing 1,2 or 4 bytes in every data access.

Bit Description

64:0

BIOS Work Space.

3-44

82443BX Host Bridge Datasheet

Page 71

3.3.39 DWTC—DRAM Write Thermal Throttling Control Register (Device 0)

Offset: E0h–E7h Default: 0000_0000_0000_0000h Access: Read/Write/Lock Size: 64 bits

A locking mechanism is included to protect contents of this register as well as the DRAM Read Thermal Throttling Control register described below.

Bits Description

Throttle Lock (TLOCK).

62:46 Reserved

45:38

37:26

25:20

19:13

12:3

2:0

1 = All configuration register bits in E0h–E7h and E8h–EFh (read throttle control) become read-

only.

0 = Default

Global DRAM Write Sampling Window (GDWSW).

the length of time in milliseconds (0–1020) over which the number of QWords written is counted.

Global QW ord Threshold (GQT).

at the number of QWords that must be written within the Global DRAM Write Sampling Window in order to cause the thermal throttling mechanism to be invoked.

Throttle Time (TT).

thermal throttling remains in effect as a number of Global DRAM Write Sampling Windows. For example, if GDWSW is programmed to 1000_0000b and TT is set to 01_0000b, then thermal throttling will be performed for ~2 seconds once invoked (128 ms * 16).

Throttle Mo nitoring Window (TMW).

a window of 0–2047 DRAM CLKs with 16 clock granularity. While the thermal throttling mechanism is invoked, DRAM writes are monitored during this window—if the n umber of QW ords written during the window reaches the Throttle QWord Maximum, then write requests are blocked for the remainder of the window.

Throttle QWord Maximum (TQM).

of QWords between 0–1023 which are permitted to be written to DRAM within one Throttle Monitoring Window while the thermal throttling mechanism is in effect.

DRAM Write Throttle Mode.

enabled when bits 2:0 are set to 100. All other combinations are Intel Reserved. 000-011 = Intel Reserved 100 = Normal Operations 101-111 = Intel Reserved

This bit secures the DRAM thermal throttling control registers.

This 8-bit value is multiplied by 4 to define

The 12-bit value held in this field is multiplied by 215 to arrive

This value provides a multiplier between 0 and 63 which specifies how long

The value in this register is padded with four 0’s to specify

The Throttle QWord Maximum defines the maximum number

Normal DRAM write monitoring and thermal throttling operation are

82443BX Host Bridge Datasheet

3-45

Page 72

3.3.40 DRTC—DRAM Read Thermal Throttling Control Register (Device 0)

Offset: E8h–EFh Default: 0000_0000_0000_0000h Access: Read/Write/Lock Size: 64 Bits

The contents of this register are protected by making the bits read-only once a ‘1’ is written to the Throttle Lock bit (bit 63 of configuration register E0–E7h)

Bits Description

63:46 Reserved

45:38

37:26

25:20

19:13

12:3

2:0

Global DRAM Read Sampling Window (GDRSW).

the length of time in milliseconds (0–1020) over which the number of QWords read from DRAM is counted.

Global Read QW or d Thresho ld (GRQT).

arrive at the number of QWor ds that must be written within the Global DRAM Read Sampling Window in order to cause the thermal throttling mechanism to be invoked.

Read Throttle Time (RTT

how long read thermal throttling remains in effect as a number of Global DRAM Read Sampling Windows. For e x ample, if GDRSW is programmed to 1000_0000b and RTT is set to 01_0000b, then read thermal throttling will be performed for ~2 seconds once invoked (128 ms * 16).

Read Throttle Monitoring Windo w (RTMW).

specify a window of 0–2047 DRAM CLKs with 16 clock granularity. While the thermal throttling mechanism is invoked, DRAM reads are monitored during this window—if the number of QWords read during the window reaches the Throttle QWord Maximum, then Host and PCI read requests, as well as all AGP requests, are block ed for the remainder of the window.

Read Throttle QWord Maximum (RTQM).

maximum number of QWords between 0–1023 which are permitted to be read from DRAM within one Read Throttle Monitoring Window while thermal throttling mechanism is in effect.

DRAM Read Throttle Mode.

enabled when bits 2:0 are set to 100. All other combinations are Intel Reserved. 000-011 = Intel Reserved 100 = Normal Operations 101-111 = Intel Reserved

). This value provides a multiplier between 0 and 63 which specifies

Normal DRAM read monitoring and thermal throttling operation are

The 12-bit value held in this field is multiplied b y 215 to

The Read Throttle QWord Maximum defines the

This 8-bit value is multiplied by 4 to define

The value in this register is padded with 4 0’s to

3-46

82443BX Host Bridge Datasheet

Page 73

3.3.41 BUFFC—Buffer Control Register (Device 0)

Offset: F0–F1h Default: 0000h Access: Read/Write Size: 16 bits

The Jam Latch design provides the AGP sub-system with a variable strength, to better accommodate the clamping requirements.

The Jam Latch Register should be enabled by the BIOS during the resume sequence from STR, if these Jam Latch control bits had been enabled before the STR was executed.

Bit Description

15:10 Reserved.

AGP Jam Latch Strength Select.

Bit 9 = 1; Enable strong pull-up Bit 8 = 1; Enable weak pull-up

9:6

Bit 7 = 1; Enable strong pull-down Bit 6 = 1; Enable weak pull-down

5:0 Intel Reserved.

82443BX Host Bridge Datasheet

3-47

Page 74

3.4 PCI-to-PCI Bridge Registers (Device 1)

The configuration space for device #1 is controlled by the AGP_DIS bit in the PMCR register.

Note: When AGP_DIS = 0, the configuration space for device #1 is enabled, and the registers defined

below are accessible through the configuration mechanism defined in the first section of this document.

Note: When the AGP_DIS = 1, the configuration space for device #1 is disabled. All configuration cycles

(reads and writes) to device #1 of bus 0 will cause the master abort status bit for de vice #0/ b us 0 to be set. Configuration read cycles will return data of all 1’s. Configuration write cycles will have no effect on the registers.

Table 3-4. 82443BX Configuration Space—Device 1

Address

Offset

00–01h VID1 Vendor Identification 8086h R O 02–03h DID1 Device Identification 7191h RO 04–05h PCICMD1 P CI Command Register 0000h R/W 06–07h PCISTS1 PCI Status Register 0220h RO, R/WC 08h RID1 Revision Identification 00/01h RO 09h — Reserved 00h — 0Ah SUBC1 Sub-Class Code 04h RO 0Bh BCC1 Base Class Code 06h RO 0Ch — Reserved 00h — 0Dh MLT1 Master Latency Timer 00h R/W 0Eh HDR1 Header Type 01h RO 0F–17h — Reserved 00h — 18h PBUSN Primary Bus Number 00h RO 19h SBUSN Secondary Bus Number 00h R/W 1Ah SUBUSN Subordinate Bus Number 00h R/W 1Bh SMLT Secondary Bus Mas ter Latency Timer 00h R/W 1Ch IOBASE I/O Base Address Register F0h R/W 1Dh IOLIMIT I/O Limit Address Register 00h R/W 1E–1Fh SSTS Secondary PCI-to-PCI Status Register 02A0h R/WC, RO 20–21h MBASE M emory Base Address Register FFF0h R/W 22–23h MLIMIT Memory Limit Address Register 0000h R/W 24–25h PMBASE Prefetchable Memory Base Address Reg. FFF0h R/W 26–27h PMLIMIT Prefetchable Memory Limit Address Reg. 0000h R/W 28–3Dh — Reserved 0 c 3Eh BCTRL Bridge Control Register 80h R/W 3F–FFh — Reserved 00h —

Symbol

Default

Value

Access

3-48

82443BX Host Bridge Datasheet

Page 75

3.4.1 VID1—Vendor Ide ntification Register (Device 1)

Address Offset: 00–01h Default Value: 8086h Attribute: Read Only Size: 16 bits

The VID Register contains the vendor identification number. This 16-bit register combined with the Device Identification Register uniquely identify any PCI device. Writes to this register have no effect.

Bit Description

15:0

Vendor Identification Number.

This is a 16-bit value assigned to Intel. Intel VID = 8086h.

3.4.2 DID1—Device Identification Register (Device 1)

Address Offset: 02–03h Default Value: 7191h Attribute: Read Only Size: 16 bits

This 16-bit register combined with the Vendo r Identification register uniquely identifies any PCI device. Writes to this register have no effect.

Bit Description

15:0

Device Identification Number.

82443BX device #1 DID =7191h.

This is a 16 bit value assigned to the 82443BX device #1.

82443BX Host Bridge Datasheet

3-49

Page 76

3.4.3 PCICMD1—PCI-to-PCI Command Register (Device 1)

Address Offset: 04–05h Default: 0000h Access: Read/Write Size 16 bi ts

Bit Descriptions

15:10 Reserved.

7 6 5

Fast Back-to-Back: SERR# Enable (SERRE1).

is enabled for error conditions that occur on AGP.If both SERRE and SERRE1 are reset to 0, then SERR# is never driv en by the 82443BX. Also , i f this bi t is set and the Parity Error Response Enable Bit (Dev 01h, Register 3Eh, Bit 0) is set, then the 82443BX will report ADDRESS and DATA parity errors on AGP.

1 = Enable. 0 = Disable.

Address/Data Stepping. Parity Error Enable (PERRE1). Reserved. Memory Write and Invalidate Enable: Not applicable.

to avoid the problems with normal PCI-to-PCI Bridge configuration software.

Special Cycle Enable: Not applicable.

problems with normal PCI-to-PCI Bridge configuration software.

Bus Master Enable (BME1): Not applicable.

the problems with normal PCI-to-PCI Bridge configuration software.

Memory Access Enable (MAE1): Not applicable.

avoid the problems with normal PCI-to-PCI Bridge configuration software.

I/O Access Enable (IOAE1): Not applicable.

the problems with normal PCI-to-PCI Bridge configuration software.

Not Applicable. Hardwired to 0.

When enabled the SERR# signal driver (common for PCI and AGP)

Not applicable. Hardwired to 0.

Hardwired to 0.

However, supported as a read/write bit

However, supported as a read/write bit to avoid the

However, supported as a read/write bit to avoid

However, supported as a read/write bit to

However, supported as a read/write bit to avoid

3-50

82443BX Host Bridge Datasheet

Page 77

3.4.4 PCISTS1—PCI-to-PCI Status Register (Device 1)

Address Offset: 06–07h Default Value: 0220h Access: Read Only, Read/Write Clear Size: 16 bits

PCISTS1 is a 16-bit status register that reports the occurrence of error conditions associated with primary side of the “virtual” PCI-to-PCI bridge embedded within the 82443BX.

Bit Descriptions

15 14 Reserved. 13 12 11

10:9

4:0 Reserved.

Detected Parity Error (DPE1).

Received Master Abort Status (RMAS1). Received Target Abort Status (RTAS1). Signaled Target Abort Status (STAS1). DEVSEL# Timing (DEVT1).

Data Parity Detected (DPD1).

Fast Back-to-Back (FB2B1).

6 Reserved. 5

66/60 MHz Capability.

Not Applicable. Hardwired to 0.

Not Applicable. Hardwired to “01b”.

Not Applicable. Hardwired to 0.

Hardwired to “1”.

3.4.5 RID1—Revision Identification Register (Device 1)

Address Offset: 08h Default Value: 00/01h Access: Read Only Size: 8 bits

This register contains the revision number of the 82443BX device #1. These bits are read only and writes to this register have no effect. For the A-0 Stepping, this value is 00h.

Bit Description

This is an 8-bit value that indicates the revision identification

7:0

Revision Identification Number.

number for the 82443BX device #1. 02h = B1 stepping

82443BX Host Bridge Datasheet

3-51

Page 78

3.4.6 SUBC1—Sub-Class Code Register (Device 1)

Address Offset: 0Ah Default Value: 04h Access: Read Only Size: 8 bits

This register contains the Sub-Class Code for the 82443BX de vice #1. This code is 04h indicating a PCI-to-PCI Bridge device. The register is read only.

Bit Description

This is an 8-bit value that indicates the category of Bridge into which

7:0

Sub-Class Code (SUBC1).

the 82443BX falls. 04h = Host Bridge.

3.4.7 BCC1—Base Class Code Register (Device 1)

Address Offset: 0Bh Default Value: 06h Access: Read Only Size: 8 bits

This register contain s the Base Class C ode of the 824 43BX de vice #1. This code is 06h in dicating a Bridge device. This register is read only.

Bit Description

This is an 8-bit value that indicates the Base Class Code for the

7:0

Base Class Code (BASCC).

82443BX device #1. 06h = Bridge device.

3.4.8 MLT1—Master Latency Timer Register (Device 1)

Address Offset: 0Dh Default Value: 00h Access: Read/Write Size: 8 bits

This functionality is not applicable. It is described here since these bits should be implemented as a read/write to comply with the normal PCI-to-PCI bridge configuration software.

Bit Description

7:3 2:0 Reserved.

Not applicable but support read/write operations.

(Reads return previously written data.)

3-52

82443BX Host Bridge Datasheet

Page 79

3.4.9 HDR1—Header Type Register (De vice 1)

Offset: 0Eh Default: 01h Access: Read Only Size: 8 bits

This register identifies the header layout of the configuration space. No physical register exists at this location.

Bit Descriptions

7:0

Header Type (HEADT).

This read only field always returns 01h when read. Writes have no effect.

3.4.10 PBUSN—Primary Bus Number Register (Device 1)

Offset: 18h Default: 00h Access: Read Only Size: 8 bits

This register identifies that “virtual” PCI-to-PCI bridge is connected to bus #0.

Bit Descriptions

7:0

Bus Number.

Hardwired to “0”.

3.4.11 SBUSN—Secondary Bus Number Register (Device 1)

Offset: 19h Default: 00h Access: Read /Write Size: 8 bits

This register identifies the bus number assigned to the second bus side of the “virtual” PCI-to-PCI bridge i.e. to AGP. This number is programmed by the PCI configuration software to allow mapping of configuration cycles to AGP.

Bit Descriptions

7:0

Bus Number.

Default “0”.

Programmable

82443BX Host Bridge Datasheet

3-53

Page 80

3.4.12 SUBUSN—Subordinate Bus Number Register (Device 1)

Offset: 1Ah Default: 00h Access: Read /Write Size: 8 bits

This register identifies the subordinate bus (if any) that resides at the level below AGP.This number is programmed by the PCI con figur ation softwar e to allo w mapping of co nfigu ration cycles to A GP.

Bit Descriptions

7:0

Bus Number.

Programmable.

3.4.13 SMLT—Secondary Master Latency Timer Register (Device 1)

Address Offset: 1Bh Default Value: 00h Access: Read/Write Size: 8 bits

This register control the bus tenure of the 82443BX on AGP the same way the Device 0 MLT controls the access to the PCI bus.

Bit Description

7:3 2:0 Reserved.

Secondary MLT Counter Value.

The default is 0s (i.e,. SMLT disabled)

3.4.14 IOBASE—I/O Base Address Register (De vice 1)

Address Offset: 1Ch Default Value: F0h Access: Read/Write Size: 8 bits

This register control the CPU to AGP I/O access routing based on the following formula:

IO_BASE=< address =<IO_LIMIT

Bit Description

7:4 3:0 Reserved.

I/O Address Base.

Corresponds to A[15:12] of the I/O address. Default = Fh

3-54

82443BX Host Bridge Datasheet

Page 81

3.4.15 IOLIMIT—I/O Limit Address Register (Device 1)

Address Offset: 1Dh Default Value: 00h Access: Read/Write Size: 8 bits

This register controls the CPU to AGP I/O access routing based on the following formula:

IO_BASE=< address =<IO_LIMIT

Bit Description

7:4 3:0

I/O Address Limit. Reserved.

(Only 16 bit addressing supported.)

Corresponds to A[15:12] of the I/O address. Default=0

82443BX Host Bridge Datasheet

3-55

Page 82

3.4.16 SSTS—Secondary PCI-to-PCI Status Register (Device 1)

Address Offset: 1E–1Fh Default Value: 02A0h Access: Read Only, Read/Write Clear Size: 16 bits

SSTS is a 16-bit status register that reports the occurrence of error conditions associated with secondary side (i.e. AGP side) of the “virtual” PCI-to-PCI bridge embedded within 82443BX.

Bit Descriptions

Detected Parity Error (DPE1).

10:9

4:0 Reserved.

Also the PERR# is not implemented in the 82443BX. 1 = 82443BX detected of a parity error in the address or data phase of AGP bus transactions. 0 = Software sets DPE1 to 0 by writing a 1 to this bit.

Received System Error (SSE1).

1 = 82443BX asserted SERR# for any enabled error condition under device 1. Device 1 error

conditions are enabled in the SSTS and BCTRL registers.

0 = Software clears SSE1 to 0 by writing a 1 to this bit.

Received Master Abort Status (RMAS1).

1 = 82443BX terminates a Host-to-AGP with an unexpected master abort. 0 = Software resets this bit to 0 by writing a 1 to it.

Received Ta rget Abort St atus (RTAS1).

1 = 82443BX-initiated transaction on AGP is terminated with a target abort. 0 = Software resets RTAS1 to 0 by writing a 1 to it.

Signaled Target Abort Status (STAS1).

generate target abort on AGP.

DEVSEL# Timing (DEVT1).

82443BX responds as a target on AGP, and is hard-wired to the value 01b (medium) to indicate the time when a valid DEVSEL# can be sampled by the initiator of the PCI cycle.

01 = Medium. (hardwired)

Data Parity Detected (DPD1).

However, data parity errors are still detected and reported on SERR# (if enabled by SERRE,

SERRE1 and the BCTRL register, bit 0).

Fast Back-to-Back (FB2B1).

back-to-back transactions on AGP. 6 Reserved. 5

66/60MHZ Capability.

Note that the PERRE1 bit does not affect the function of this bit.

STAS1 is hardwired to a 0, since the 82443BX does not

This 2-bit field indicates the timing of the DEVSEL# signal when the

Hardwired to 0. 82443BX does not implement G_PERR# function.

This bit is hardwired to 1. The 82443BX as a target supports fast

Hardwired to 1.

3-56

82443BX Host Bridge Datasheet

Page 83

3.4.17 MBASE—Memory Base Address Register (Device 1)

Address Offset: 20–21h Default Value: FFF0h Access: Read/Write Size: 16 bits

This register controls the CPU to AGP non-prefetchable memory access routing based on the following formula:

MEMORY_BASE=< address =<MEMORY_LI MIT

This register must be initialized by the configuration software.

Bit Description

15: 4

3:0 Reserved.

Memory Address Base (MEM_BASE).

Default=FFF0h

Corresponds to A[31:20] of the memory address.

3.4.18 MLIMIT—Memory Limit Address Register (Device 1)

Address Offset: 22–23h Default Value: 0000h Access: Read/Write Size: 16 bits

This register controls the CPU to AGP non-prefetchable memory access routing based on the following formula:

MEMORY_BASE=< address =<MEMORY_LI MIT

This register must be initialized by the configuration software.

Note: Memory range covered by MBASE and MLIMIT registers are used to map non-prefetchable AGP

address ranges (typically where control/status memory-mapped I/O data structures of the graphics controller will reside) and PMBASE and PMLIMIT are used to map prefetchable address ranges (typically graphics local memory). This segregation allows application of USWC space attribute to be performed in a true plug-and-play manner to the prefetchable address range for improved CPUAGP memory access performance.

Note: The configuration software is responsible for programming all address range registers

(prefetchable, non-prefetchable) with the values that provide exclusive address ranges i.e. prevent overlap with each other and/or with the ranges covered with the main memory. There is no provision in the 82443BX hardware to enforce prevention of overlap and operations of the system in the case of overlap are not guaranteed.

Bit Description

15: 4

82443BX Host Bridge Datasheet

Memory Address Limit (MEM_LIMIT).

3:0 Reserved.

Corresponds to A[31:20] of the memory address. Default=0

3-57

Page 84

3.4.19 PMBASE—Prefetchable Memory Base Address Register (Device 1)

Address Offset: 24–25h Default Value: FFF0h Access: Read/Write Size: 16 bits

This register controls the CPU to AGP prefetchable memory accesses routing based on the following formula:

PREFETCHABLE_MEMORY_BASE=< address =<PREFETCHABLE_MEMORY_LIMIT

This register must be initialized by the configuration software.

Bit Description

Prefetchable Memory Address Base(PMEM_BASE).

15: 4

3:0 Reser ved.

address. Default=FFF0h

Corresponds to A[31:20] of the memory

3.4.20 PMLIMIT—Prefetchable Memory Limit Address Register (Device 1)

Address Offset: 26–27h Default Value: 0000h Access: Read/Write Size: 16 bits

This register controls the CPU to AGP prefetchable memory accesses routing based on the following formula:

PREFETCHABLE_MEMORY_BASE=< address =<PRE FETCHAB LE_MEMORY_LIMIT

This register must be initialized by the configuration software.

Note: The prefetchable memory range is supported to allow segregation by the configuration software

between the memory ranges that must be defined as Uncachable and the ones that can be designated as a USWC (i.e. prefetchable) from the CPU perspective.

3-58

Bit Description

15: 4

3:0 Reser ved.

Prefetchable Memory Address Limit (PMEM_LIMIT).

address. Default=0

Corresponds to A[31:20] of the memory

82443BX Host Bridge Datasheet

Page 85

3.4.21 BCTRL— PC I-to-PCI Bridge Control Register (Device 1)

Address Offset: 3Eh Default: 80h Access: Read/Write Size 8 bits

This register provides extensions to the PCICMD1 register that are specific to PCI-to-PCI bridges. The BCTRL provides additional control for the secondary interface (i.e., AGP) as well as some bits that affect the overall behavior of the “virtual” PCI-to-PCI bridge in the 82443BX (e.g., VGA compatible address ranges mapping).

Bit Descriptions

Fast Back to Back Enable.

this bit is hardwired to 1.

Secondary Bus Reset:

and therefore this bit is hardwired to 0.

NOTE: The only way to perform a hard reset of the AGP is via the system reset either initiated by software or hardware via PIIX4E.

Master Abort Mode.

AGP the 82443BX will drop writes on the “floor” and return all 1s during reads.)

4 Reserved.

VGA Enable.

and memory address ranges. 1 = 82443BX will forward the following CPU accesses to AGP:

• memory accesses in the range 0A0000h to 0BFFFFh

• I/O addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh (inclusive of ISA address aliases - A[15:10] are not decoded)

1 Reserved.

When this bit is set, forwarding of these accesses issued by the CPU is independent of the I/O address and memory address ranges defined by the previously defined base and limit registers. Forwarding of these accesses is also independent of the settings of bit 2 (ISA Enable) of this register or of bit 5 (VGA Palette Snoop Enable) of the PCICMD1 register if this bit is 1.

0 = VGA compatible memory and I/O range accesses are mapped to PCI unless they are

redirected to AGP via I/O and memory range registers defined above (IOBASE, IOLIMIT, MBASE, MLIMIT, PMBASE, PMLIMIT). (default)

ISA Enable.

target ISA I/O addresses. This applies only to I/O addresses that are enabled by the IOBASE and IOLIMIT registers.

1 = When this bit is set to 1 82443BX will not forward to AGP any I/O transactions addressing

the last 768 bytes in each 1KB block even if the addresses are within the range defined by the IOBASE and IOLIMIT registers. Instead going to AGP these cycles will be forwarded to PCI where they can be subtractively or positively claimed by the ISA bridge.

0 = All addresses defined by the IOBASE and IOLIMIT f or CPU I/O transactions will be mapped

to AGP. (default)

Parity Error Response Enable.

AGP. G_PERR# is not implemented by the 82443BX. However, when this bit is set to 1, address and data parity errors on AGP are reported via SERR# mechanism, if enabled by SERRE1 and SERRE. If this bit is reset to 0, then address and data parity errors on AGP are not reported via the 82443BX SERR# signal. Other types of error conditions can still be signaled via SERR# independent of this bit’s state.

1 = Enable. 0 = Disable.

Controls the routing of CPU-initiated transactions targeting VGA compatible I/O

Modifies the response by the 82443BX to an I/O access issued by the CPU that

82443BX supports fast back-to-back cycles on AGP, and therefore

82443BX does not support generation of reset via this bit on the AGP

Not applicable. Hardwired to 0. (This means when acting as a master on

Controls 82443BX’s response to data phase parity errors on

82443BX Host Bridge Datasheet

3-59

Page 86

Page 87

Functional Description

This chapter describes the 82443BX interfaces on-chip functional units. Section 4.1, “System Address Map” on page 4-1 provides a system-level address memory map and describes the memory space controls provided b y the 82443B X. This section also describes the I/O add ress map. Note that 82443BX register maps are provided in Chapter 3, “Register Description”.

The 82443BX Host-to-PCI Bridge functions are described Host, PCI, and AGP interfaces are described in Section 4.2, “Host Interface” on page 4-10, Section 4.4, “PCI Interface” on page 4-24, and Section 4.5, “AGP Interface” on page 4-24.

The DRAM interface includin g supported DRAM types, or ga nizations, conf igu rations, and r egist er programming considerations is provided in Section 4.3, “DRAM Interface” on page 4-14. Data integrity support on the Host bus, PCI bus, and DRAM interface is described in Section 4.6, “Data Integrity Support” on page 4-25.

System clocking requirements is provided in Section 4.7, “System Clocking” on page 4-28. The 82443BX has various power management capabilities. Suspend resume, clock control,

SDRAM power down, and SMRAM functions are described in Section 4.8, “Power Management” on page 4-28. This section also contains information on the 82443BX reset operations.

4.1 System Address Map

A Pentium® Pro processor-based system with the Intel® 440BX AGPset supports 4 GB of addressable memory space and 64 KB + 3 of addressable I/O space. (The Pentium bus I/O addressability is 64 KB + 3). There is a programmable memory address space under the 1 MB region which is divided into regions which can be individually controlled with programmable attributes such as Disable, Read/Write, Write Only, or Read Only. Attribute programming is described in the Register Description section. This section focuses on how the memory space is partitioned and what these separate memory regions are used for. The I/O address space requires much simpler mapping and it is explained at the end of this section.

The Pentium Pro processor family supports addressing of memory ranges larger than 4 GB. The 82443BX Host Bridge claims any access ov er 4 GB b y terminating transaction (witho ut forwarding it to PCI or AGP). Writes are terminated simply by dropping the data and for reads the 82443BX returns all zeros on the host bus. Note that the 82443BX as a target does not support the PCI Dual Address Cycle Mechanism (DAC) which allows addressing of >4GB on either the PCI or AGP interface.

In the following sections, it is assumed that all of the compatibility mem ory ranges reside on PCI. The exception to this rule are the VGA ranges which may be mapped to AGP. In the absence of more specific references, cy cle descriptions referencing PCI should be interpreted as PCI, while cycle descriptions referencing AGP are relate to AGP.

Pro processor

82443BX Host Bridge Datasheet

4-1

Page 88

Functional Description

4.1.1 Memory Address Ranges

Figure 4-1 provides a detailed 82443BX memory map indicating specific memory regions defined by AGP and supported by the Intel

440BX AGPset.

Figure 4-1. Memory System Address Space

System Memory Space

64 GB

Window For Non-Prefetchable

PCI accesses to AGP

(Base=MBASE Reg. (20h); Dev 0)

(Size=MLIMIT Reg. (22h); Dev 0)

Window For Prefetchable

PCI accesses to AGP

(Base=PMBASE Reg. (24h); Dev 1)

(Size=PMLIMIT Reg. (26h); Dev 1)

AGP Aperture Range

(Base=APBASE Reg. (10h); Dev 0)

(Size=APSIZE Reg. (B4h); Dev 0)

TOM (1 GB Max.)

Graphics Address Re-Mapping Table

(Base=ATTBASE Reg. (B8h); Dev 0)

0FFFFFh

C0000h BFFFFh

A0000h

00000h

Notes:

1. Graphics Device accesses to the AGP aperture invoke AGP transfer protocol on the AGP Bus and use GART to re- map the accesses to graphics data structures located in main memory.

2. The two window regions provide PCI accesses over the AGP.

Extended CPU

Memory Space

4 GB

Graphics Device

(e.g., memory-mapped

control/status registers)

Local Graphics Memory

- Frame Buffer

- Rendering Buffer

- Depth Buffer (Z)

- Video Capture Buffer

AGP Aperture

- Textures

- Other Surfaces

- Instruction Stream

AGP Data AGP Data AGP Data

Optional ISA Hole

Video BIOS

(shadowed in memory)

Graphics Adapter

System/Application SW

Access

GART

(128 KB)

PCI Memory

accesses to AGP

PCI Memory

accesses to AGP

PCI Memory

AGP

Aperture

PCI Memory

DOS

Main

Memory

16 MB 15 MB

1 MB

Compatibility

Memory

AGP aperture, GART, and Graphics data structures mapped by GART

PCI memory accesses to AGP

PCI memory accesses to primary PCI bus

Main memory (physical memory) and CPU extended memory (above 4 GB)

0FFFFFh 1 MB

Upper BIOS Area

(64 KB)

0F0000h

0EFFFFh

0E0000h

0DFFFFh

0C0000h

0BFFFFh

0A0000h 09FFFFh

080000h

07FFFFh

000000h

Lower BIOS Area

(64 KB)

16KBx4

Expansion Card BIOS

and Buffer Area

(128 KB) 16KBx8

Standard PCI/ISA Video

Memory (SMM Mem)

128 KB

Optional Fixed Memory

Hole

DOS Area

(512 KB)

960 KB

896 KB

768 KB

640 KB

512 KB

0 KB

mem_map2.vsd

4-2

82443BX Host Bridge Datasheet

Page 89

4.1.1.1 Compatibility Area

This area is divided into the following address regions:

0–512 KB DOS Area

•

512 KB – 640 KB DOS Area - Optional ISA/PCI Memory

•

640KB – 768 KB Video Buffer Area

•

768 KB – 896 KB in 16KB sections (total of 8 sections) - Expansion Area

•

896KB – 960 KB in 16KB sections (total of 4 sections) - Extended System BIOS Area

•

960 KB – 1 MB Memory (BIOS Area) - System BIOS Area

•

There are sixteen memory segments in the compatibility area. Thirteen of the memory ranges can be enabled or disabled independently for both read and write cycles. One segment (512 KB–640 KB) which can be mapped to either main DRAM or PCI.

Table 4-1. Memory Segments and their Attributes

Memory Segments Attributes Comments

000000h–07FFFFh fixed - always mapped to main DRAM 0 – 512 KB; DOS Region 080000h–09FFFFh c onfigurable as PCI or main DRAM 512 KB – 640 KB; DOS Region

0A0000h–0BFFFFh 0C0000h–0C3FFFh W E ; RE Add-on BIOS

0C4000h–0C7FFFh W E ; RE Add-on BIOS 0C8000h–0CBFFFh WE; RE Add-on BIOS 0CC000h–0CFFFFh WE; RE A dd-on BIOS 0D0000h–0D3FFFh W E ; RE Add-on BIOS 0D4000h–0D7FFFh W E ; RE Add-on BIOS 0D8000h–0DBFFFh WE; RE Add-on BIOS 0DC000h–0DFFFFh WE; RE A dd-on BIOS 0E0000h–0E3FFFh WE; RE BIOS Extension 0E4000h–0E7FFFh WE; RE BIOS Extension 0E8000h–0EBFFFh W E ; RE BIOS Extension 0EC000h–0EFFFFh WE; RE BIOS Extension 0F0000h–0FFFFFh WE; RE BIOS Area

mapped to PCI - configurable as SMM space

Functional Description

Video Buffer (physical DRAM configurable as SMM space)

DOS Area (00000h–9FFFh)

The DOS area is 640 KB an d it is further di v ided into tw o part s. T he 512 KB area at 0 to 7FFFFh i s always mapped to the main memory controlled by the 82443BX, while the 128 KB address range from 080000 to 09FFFFh can be mapped to PCI or to main DRAM. By default this range is mapped to main memory and can be declared as a main memory hole (accesses forwarded to PCI) via the 82443BX’s FDHC configuration register.

Video Buffer Area (A0000h–B FFFFh)

The 128 KB graphics adapter memory region is normally mapped to a legacy video device on PCI (typically VGA controller). This area is not controlled by attribute bits and CPU-initiated cycles in this region are forwarded to PCI or AGP for termination. This region is also the default region for SMM space.

The SMRAM Control register controls how SMM accesses to this space are treated.

82443BX Host Bridge Datasheet

4-3

Page 90

Functional Description

Monochrome Adapter (MDA) Range (B0000h–B7FFFh)

Legacy support requires the ability to have a second graphics controller (monochrome) in the system. In an A GP system, accesses in the normal V GA ra nge are f orwarded to the AGP bus. Since the monochrome adapter may be on the PCI (or ISA) bus, the 82443BX must decode cycles in the MDA range and forward them to PCI.

Expansion Area (C0000h–DFFFFh)

This 128 KB ISA Expansion region is divided into eight 16 KB segments. Each segment can be assigned one of four Read/Write states: read-only, write-only, read/write, or disabled. Typically, these blocks are mapped through the Host-to-PCI bridge and are subtractively decoded to ISA space. Memory that is disabled is not remapped.

Extended System BIOS Area (E0000h–EFFFFh)

This 64 KB area is divided into four 16 KB segments. Each segment can be assigned independent read and write attributes so it can be mapped either to m ain DRAM or to PCI. Typically , this area is used for RAM or ROM. Memory segments that are disabled are not remapped elsewhere.

System BIOS Area (F0000h–FFFFFh)

This area is a single 64 KB segment. This segment can be assigned read and write attributes. It is by default (after reset) Read/Write disabled and cycles are forwarded to PCI. By manipulating the Read/Write attributes, the 82443BX can “shadow” BIOS into the main DRAM. When disabled, this segment is not remapped.

4.1.1.2 Extended Memory Area

This memory area covers 10000 0h (1 MB) to FFFFFFF Fh (4 GB-1) address ran ge and it is di vi ded into the following regions:

Main DRAM Memory from 1 MB to the Top of Memory; maximum of 256 MB using 16M

•

DRAM technology or 1 GB using 64M technology PCI Memory space from the Top of Memory to 4 GB with two specific ranges:

•

— APIC Configuration Space from FEC0_0000h (4 GB-20 MB) to FECF_FFFFh and

EE0_0000h to FEEF_FFFFh

— High BIOS area from 4 GB to 4 GB – 2 MB

Main DRAM Address Range (0010_0000h to Top of Main Memory)

The address range from 1 MB to the top of main memory is mapped to main DRAM address range controlled by the 82443BX. All accesses to addresses within this range will be forwarded by the 82443BX to the DRAM unless a hole in this range is created using the fixed hole as controlled by the FDHC register. Accesses within this hole are forwarded to PCI.

The range of physical DRAM memory disabled by opening the hole is not remapped to the Top of the Memory.

4-4

Extended SMRAM Address Range (Top of Main Memory – TSEG)

An extended SMRAM space of up to 1 MB can be defined in the address range at the top of memory. The size of the SMRAM space is determined by the TSEG value in the ESMRAMC register. When the extended SMRAM space is enabled, non-SMM CPU accesses and all PCI and

82443BX Host Bridge Datasheet

Page 91

Functional Description

AGP accesses in this range are forwarded to PCI. When SMM is enabled the amount of memory available to the system is equal to the amount of physical DRAM minus the value in the TSEG register.

Note: When extended SMRAM is used, th e maximu m amount of DRAM su pported i s limit ed to 256 MB.

PCI Memory Address Range (Top of Main Memory to 4 GB)

The address range from the top of main DRAM to 4 GB (top of physical memory space supported by the Intel

•

440BX AGPset) is normally mapped to PCI. There are two exceptions to this rule:

Addresses decoded to the AGP Memory Window defined by the MBASE, MLIMIT, PMBASE, and PMLIMIT registers are mapped to AGP.

Addresses decoded to the Graphics Aperture range defined by the APBASE and APSIZE

•

registers are mapped to the main DRAM.

There are two sub-ranges within the PCI Memory address range defined as APIC Configuration Space and High BIOS Address Range. The A GP Memory W indo w and Graphics Aperture W ind ow MUST NOT overlap with these two ranges. These ranges are described in detail in the following paragraphs.

APIC Configuration Space (FEC0_0000h -FECF_FFFFh, FEE0_0000h- FEEF_FFFFh)

This range is reserved for APIC configuration space which includes the default I/O APIC configuration space. The default Local APIC configuration space is FEE0_0000h to FEEF_0FFFh.

CPU accesses to the Local APIC configuration space do not result in external bus activity since the Local APIC configuration space is internal to the CPU. Ho we v er, a MTRR must be programmed to make the Local APIC range uncacheable (UC). The Local APIC base address in each CPU should be relocated to the FEC0_00 00h (4 GB – 20 MB) to F ECF_F FFFh r ange so that one MTRR can be programmed to 64 KB for the Local and I/O APICs. The I/O APIC(s) usually reside in the I/O Bridge portion of the A GPset or as a stand-alone co mponent(s). For I ntel

440BX AGPset systems

using the PIIX4E, the I/O APIC is supported as a stand-alone component residing on the X-Bus. I/O APIC units will be located beginning at the default address FEC0_0000h. The first I/O APIC

will be located at FEC0_0000h. Each I/O APIC unit is located at FEC0_x000h where x is I/O APIC unit number 0 through F (hex). This address range will be normally mapped to PCI.

Note: There is no provision to support an I/O APIC de vice on A GP. Also the I/O APIC is not supported in

a mobile platform. The address range between the APIC configuration space and the High BIOS (FED0_0000h to

FEDF_FFFFh) is always mapped to the PCI.

High BIOS Area (FFE0_0000h –FFFF_FFFFh)

The top 2 MB of the Extended Memory Region is reserved for System BIOS (High BIOS), extended BIOS for PCI devices, and the A20 alias of the system BIOS. CP U be gins e xecu tion from the High BIOS after reset. This region is mapped to PCI so that the upper subset of this region aliases to 16 MB–256 KB rang e. The actual address space required for the BIOS is less than 2 MB but the minimum CPU MTRR range for this region is 2 MB so that full 2 MB must be considered. The PIIX4E supports a maximum of 1 MB in the High BIOS range.

82443BX Host Bridge Datasheet

4-5

Page 92

Functional Description

4.1.1.3 AGP Memory Address Range

The 82443BX can be programmed to direct memory accesses to the AGP bu s interface when addresses are within either of two ranges specified via registers in 82443BX Device #1 configuration space. The first range is controlled via the Memory Base Register (MBASE) and Memory Limit Register (MLIMIT) registers. The second range is controlled via the Prefetchable Memory Base (PMBASE) and Prefetchable Memory Limit (PMLIMIT) registers

The 82443BX positively decodes memory accesses to AGP memory address space as defined by the following equations:

Memory_Base_Address ≤ Address ≤ Memory_Limit_Address

Prefetchable_Memor

The effective size of the range is programmed by the plug-and-play configuration software and it depends on the size of memory claimed by the AGP compliant device. Normally, these ranges reside above the Top-of-Main-DRAM and below High BIOS and APIC address ranges.

Note: The 82443BX Device #1 memory range registers described above are used to allocate memory

address space for any devices on AGP that require such a window. These devices include the AGP compliant device, and multifunctional AGP compliant devices where one or more functions are implemented as PCI devices.

_Base_Address ≤ Address ≤ Prefetchable_Memory_Limit_Address

4.1.1.4 AGP DRAM Graphics Aperture

Memory-mapped, graphics data structures can reside in a Graphics Aperture to main DRAM memory. This aperture is an address range defined by the APBASE configuration register of the 82443BX Host Bridge. The APBASE register follows the normal base address reg i ster t emplate as defined by the PCI 2.1 specif ication. Th e size of the range claimed b y the APB ASE is prog rammed via “back-end” register APSIZE (programmed by the chip-set specific BIOS before plug-and-play session is performed). APSIZE allows selection of the aperture size of 4 MB, 8 MB,16 MB, 32 MB, 64 MB, 128 MB and 256 MB. By programming APSIZE to a specific size, the corresponding lower bits of APBASE are forced to “0” (behave as hardwired). Default value of APSIZE forces aperture size of 256 MB. Aperture address range is naturally aligned.

Although this aperture appears to be established in PCI memory space, in fact the 82443BX forwards accesses within the aperture range to the main DRAM subsystem. The originally issued addresses are translated (within 82443BX’s DRAM controller subsystem) via a translation table maintained in main memory. Translation table entries may be partially cached in a Graphics Translation Look-aside Buffer (GTLB) implemented within the 82443BX’s DRAM subsystem. The aperture range will not be cacheable in the processor caches.

4.1.1.5 System Management Mode (SMM) Memory Range

82443BX supports the use of main memory as System Managemen t RAM (SMRAM) enabling the use of System Management Mode. The 82443BX supports two SMRAM options: Compatible SMRAM (C_SMRAM) and Extended SMRAM (E_SMRAM). System Management RAM (SMRAM) space provides a memory area that is available for the SMI handler's and code and data storage. This memory resource is normally hidden from the system OS so that the processor has immediate access to this memory space upon entry to SMM. The 82443BX provides three SMRAM options:

4-6

82443BX Host Bridge Datasheet

Page 93

Below 1 MB option that support s compat ible SMI handlers.

•

Above 1 MB option that allows new SMI handlers to execute with write-back cacheable

•

SMRAM. Optional larger write-back cacheable T_SEG area from 128KB to 1MB in size above 1 MB

•

that is reserved from the highest area in system DRAM memory. The above 1 MB solutions require changes to compatible SMRAM handlers code to properly execute abo ve 1 MB.

Table 4-2 summarizes the operation of SMRAM space cycles targeting the SMI space addresses.

Table 4-2. SMRAM Decoding

Name of Range Transaction Address DRAM Address

compatible (Range A) A 0000–B FFFFh A0000–BFFFFh HI-SMRAM (RANGE H) 256M + A0000h to 256M + FFFFFh A0000–FFFFFh TSEG (RANGE T) 256M + TOM to 256M + TOM - TSEG_SIZE TOM to TOM - TSEG_SIZE

Table 4-3. SMRAM Range Decode

Global SMRAM H_SMRAME TSEG_EN A Range H Range T Range

0 x x Disable Disable Disable 1 0 0 Enable Disable Disable 1 0 1 Enable Disable Enable 1 1 0 Disabled Enable Disable 1 1 1 Disabled Enable Enable

Functional Description

NOTE:

1 = Enabled and 0 = Disabled

Table 4-4 defines the control of the decode fo r all co de fetches and d ata fetches to SMRAM ran ges (as defined by Table 4-3). The G_SMRAM bit provides a global disable for all SMRAM memory. The D_OPEN bit allows software to write to the SMRAM ranges without being in SMM. BIOS software can use this bit to initialize SMM code at Power up. The D_LCK bit limits the SMRAM range access to only SMM mode accesses. The D_CLS bit causes SMM data accesses to be forwarded to PCI. The SMM software can use this bit to write to video memory while running code out of DRAM.

Table 4-4. SMRAM Decode Control

G_SMRAME D_LCK D_CLS D_OPEN SMM Mode

0 xxxxDisableDisable 1 0 x 0 0 Disable Disable 1 0001EnableEnable 1 0 0 1 x Enable Enabl e 1 0101EnableDisable 1 0 1 1 x Invalid Invalid 1 1 x x 0 Disab le Disable 1 1 0 x 1 Enable Enabl e 1 1 1 x 1 Enable Disable

NOTE:

1 = Enabled and 0 = Disabled

SMM Code

Fetch

SMM Data

Fetch

82443BX Host Bridge Datasheet

4-7

Page 94

Functional Description

Refer to Section 4.8, “Power Management” on page 4-28 for more details on SMRAM support. Reiteration:

Only un-cacheable SMM regions may overlap PCI or AGP Windows.

•

SMM regions will not overlap the AGP aperture.

•

Software (not in SMM) will not access PCI memory behind cacheable SMM regions.

•

PCI or AGP masters cannot access the SMM space.

•

4.1.2 Memory Shadowing

Any block of memory that can be designated as read-only or write-only can be “shadowed” into 82443BX DRAM memory. Typically, this is done to allow ROM code to execute more rapidly out of main DRAM. ROM is used as a read-only during the copy process while DRAM at the same time is designated write-only. After copying, the DRAM is designated read-only so that ROM is shadowed. CPU bus transactions are routed accordingly.

4.1.3 I/O Address Space

The 82443BX does not support the existence of any other I/O devices besides itself on the CPU bus. The 82443BX generates either PCI or A GP bus c ycles for all CPU I/O accesses. The 82443BX contains three internal registers in the CPU I/O space, Configuration Address Register (CONFIG_ADDRESS) and the Configuration Data Register (CONFIG_DATA) and Power Management Control Register. These locations are used to implement PCI configuration space access mechanism and as described in Section 3.1, “I/O Mapped Registers” on page 3-2.

The CPU allows 64K+3 bytes to be addressed within the I/O space. The 82443BX propagates the CPU I/O address without any translation on to the destination bus and therefore provides addressability for 64K+3 byte locations. Note that the upper 3 locations can be accessed only during I/O address wrap-around when CPU bus A16# address signal is asserted. A16# is asserted on the CPU bus whenever an I/O access is made to 4 bytes from address 0FFFDh, 0FFFEh, or 0FFFFh. A16# is also asserted when an I/O access is made to 2 bytes from address 0FFFFh.

The I/O accesses (other than ones used for PCI co nf iguration space access) ar e forw arded n ormally to the PCI bus unless they fall within the PCI1/AGP I/O address range as defined by the mechanisms in Section 4.1.4. The 82443BX will not post I/O write cycles to IDE.

4.1.4 AGP I/O Address Mapping

The 82443BX can be programmed to direct non-memory (I/O) accesses to the AGP bus interface when CPU-initiated I/O cycle addresses are within the AGP I/O address range. This range is controlled via the I/O Base Address (IOBASE) and I/O Limit Address (IOLIMIT) registers in 82443BX Device #1 configuration space.

The 82443BX positively decodes I/O accesses to AGP I/O address space as defined by the following equation:

4-8

I/O_Base_Address ≤ CPU I/O Cycle Address ≤ I/O_Limit_Address

The effective size of the range is programmed by the plug-and-play configuration software and it depends on the size of I/O space claimed by the AGP compliant device.

82443BX Host Bridge Datasheet

Page 95

Functional Description

Note that the 82443BX Device #1 I/O address range registers defined above are used for all I/O space allocation for any de vices requirin g such a windo w on AGP . These devices would include the AGP compliant device and multifunctional AGP compliant devices where one or more functions are implemented as PCI devices.

4.1.5 Decode Rules and Cross-Bridge Address Mapping

The address map described above applies globally to accesses arriving on any of the three interfaces (i.e., Host bus, PCI or AGP).

4.1.5.1 PCI Interface Decode Rules

The 82443BX accepts accesses from PCI to the following address ranges:

All memory read and write accesses to Main DRAM

•

Memory Write accesses to AGP memory range defined by MBASE, MLIMIT, PMBASE, and

•

PMLIMIT. 82443BX will not respond to memory read accesses to this range. Memory read/write accesses to the Graphics Aperture defined by APBASE and APSIZE.

•

PCI accesses that fall elsewhere within the PCI memory range will n ot be accepted. PCI cycles not explicitly claimed by the 82443BX are either subtractively decoded or master-aborted on PCI.

4.1.5.2 AGP Interface Decode Rules

Cycles Initiated Using PCI Protocol

Accesses between AGP and PCI are limited to memory writes using the PCI protocol. Write cycles are forwarded to PCI if the addresses are not within main DRAM range, AGP memory ranges, or Graphics Aperture range.

The 82443BX will claim AGP initiated memory read transactions decoded to the main DRAM range or the Graphics Aperture range. All other memory read requests will be master-aborted by the AGP initiator as a consequence of 82443BX not responding to a transaction.

If agent on AGP issues an I/O, PCI Configuration or PCI Special Cycle transaction, the 82443BX will not respond and cycle will result in a master-abort.

Cycles Initiated Using AGP Protocol

All cycles must reference main memory (i.e., main DRAM address range or Graphics Aperture range which is also physically mapped within DRAM but using different address range). AGP-initiated cycles that target DRAM are not snooped on the host bus, even if they fall outside of the AGP aperture range.

If cycle is outside of main memory range then it will terminate as follows:

Reads: return random value

•

Writes: dropped “on the floor” i.e. terminated internally without affecting any buffers or main

•

memory ECC errors that occur on reads outside of DRAM are not reported or scrubbed.

•

82443BX Host Bridge Datasheet

4-9

Page 96

Functional Description

4.1.5.3 Legacy VGA Ranges

The legacy VGA memory rang e A0000h–BFFFFh is mapped either to PCI or to A GP depending on the programming of the BCTRL conf igu ration re gister in 82 443BX Device #1 configuration space, and the NBXCONF (MD AP bit) configuration register in Device #0 configur ation space. The same registers control mapping of VGA I/O address ranges. VGA I/O range is defined as addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3 DFh (inclusi v e of ISA add ress aliases A[15:10] are not decoded).

Topic Definition

AGP IO range

ISA_EN

VGA_EN

MDAP

The AGP bus can be allocated with 1 block of IO space with a granularity of 4KB. The IO base address register points to the beginning of the AGP IO range while IO limit address register points to the end of this range. The IO range definition is based on the PCI to PCI specification.

The ISA_EN bit in the 82443BX device1 is necessary in ISA bus based systems where there is a need to allocate IO space to AGP bus devices. This is necessary since legacy ISA devices decode IO range of address [9:0] only and thus the IO address of the devices are aliased for every 1 KB of the 64 KB IO range. Therefore, to provide IO range to AG P bus and maintain the ISA IO legacy rules, the ISA_EN is set. As a result, all CPU cycles in the address ranges: “xxxx_xx01_0000_0000”b to “xxxx_xx11_1111_1111”b, that is the top 768 bytes of each 1KB aligned block, are sent to the PCI bus independent of whether this particular address is inside or outside the range allocated to the AGP bus.

The above is relev ant only to CPU-initiated cycles, as PCI and AGP master IO cycles are never claimed by the 82443BX. The ISA_EN functional definition is based on the PCI to PCI specification.

VGA IO range is defined in the following ranges: 3B0-3BBh, 3C0-3DFh. When the VGA_EN is set, all CPU initiated IO cycles in the VGA IO range are forwarded to the AGP bus, independent of whether the ISA_EN bit is set or not. Thus the VGA_EN bit setting takes precedence relative to the setting of the ISA_EN bit. The VGA_EN functional definition is based on the PCI to PCI specification.

The MDA IO range includes the ports 3B4h, 3B5h, 3B8h, 3B9h, 3BAh, 3BFh. Once the VGA_EN is set, it is legal to set the MDAP bit to indicate that a second CRT controller (Monochrome Display Adapter) resides in the PCI or ISA bus. I n this case, all the CPU-initiated IO cycles in the VGA range that are not in to the above ports are sent to AGP bus while the cycles to the above six IO ports (and to all the aliased ports) are sent to PCI bus.

Note that the CPU IO cycles to the above ports are sent to AGP bus independent of the AGP IO range and ISA_EN setting.

4.2 H ost Interface

The host interface of the 82443BX is optimized to support the Pentium I I pr ocessor with bus clock frequencies of 100 MHz and 66/60 MHz. The 82443BX implements the host address, control, and data bus interfaces within a single device. Host bus addresses are decoded by the 82443BX for accesses to main memory, PCI memory, PCI I/O, PCI configuration space and AGP space (memory, I/O and configuration). The 82443BX takes advantage of the pipelined addressing capability of the Pentium II processor to improve the overall system performance.

4.2.1 Host Bus Device Support

The 82443BX recognizes and supports a large subset of the transaction types that are defined for the Pentium Pro processor bus interface. However, each of these transaction types have a multitude of response types, some of which are not supported by this controller. All transactions are processed in the order that they are received on the Pentium summarizes the transactions supported by the 82443BX.

4-10

Pro processor bus. Table 4-5

82443BX Host Bridge Datasheet

Page 97

Table 4-5. Host Bus Transactions Supported By 82443BX

Transaction REQA[4:0]# REQB[4:0]# 82443BX Support

Functional Description

Deferred Reply 0 0 0 0 0 X X X X X Reserved 0 0 0 0 1 X X X X X Reserved

Interrupt Acknowledge 0 1 0 0 0 0 0 0 0 0 Special Transactions 0 1 0 0 0 0 0 0 0 1 See separate table in Special Cycles section.

Reserved 0 1 0 0 0 0 0 0 1 x Reser ved Reserved 0 1 0 0 0 0 0 1 x x Reserved

Branch Trace Message 0 1 0 0 1 0 0 0 0 0 Reserved 0 1 0 0 1 0 0 0 0 1 Reserved

Reserved 0 1 0 0 1 0 0 0 1 x Reser ved Reserved 0 1 0 0 1 0 0 1 x x Reserved

I/O Read 1 0 0 0 0 0 0 x LEN#

I/O Write 1 0 0 0 1 0 0 x LEN#

Reserved 1 1 0 0 x 0 0 x x x Reserved

Memory Read & Invalidate

Reserved 0 0 0 1 1 0 0 x LEN# Reserved

Memory Code Read 0 0 1 0 0 0 0 x LEN#

Memory Data Read 0 0 1 1 0 0 0 x LEN#

Memory Write (no retry) 0 0 1 0 1 0 0 x LEN#

Memory Write (can be retried)

0 0 0 1 0 0 0 x LEN#

0 0 1 1 1 0 0 x LEN#

The 82443BX initiates a deferred reply for a previously deferred transaction.

Interrupt acknowledge cycles are forwarded to the PCI bus.

The 82443BX terminates a branch trace message without latching data.

I/O read cycles are forwarded to PCI or AGP. I/O cycles which are in the 82443BX configuration space are not forwarded to PCI.

I/O write cycles are forwarded to PCI or AG P. I/O cycles which are in the 82443BX configuration space are not forwarded to PCI.

Host initiated memory read cycles are forwarded to DRAM or the PCI/1 bus. The 82443BX initiates an MRI cycle for a PCI/1 initiated write cycle to DRAM.

Memory code read cycles are forwarded to DRAM or PCI/1.

Host initiated memory read cycles are forwarded to DRAM or the PCI/1 bus. The 82443BX initiates a memory read cycle for a PCI/1 initiated read cycle to DRAM.

This memory write is a writeback cycle and cannot be retried. The 82443BX forwards the write to DRAM.

The normal memory wr ite cycle is forwarded to DRAM or PCI/1.

NOTE:

1. For Memory cycles, REQa[4:3]# = ASZ#. The 82443BX only supports ASZ# = 00 (32 bit address).

2. REQb[4:3]# = DSZ#. For the Pentium

3. LEN# = data transfer length as follows:

LEN# Data length

00 01 Length = 16 bytes BE[7:0]# all active 10 Length = 32 bytes BE[7:0]# all active 11 Reserved

≤

8 bytes (BE[7:0]# specify granularity)

82443BX Host Bridge Datasheet

Pro processor, DSZ# = 00 (64 bit data bus size).

4-11

Page 98

Functional Description

Table 4-6. Host Responses supported by the 82443BX

RS2# RS1# RS0# Description 82443BX Support

000idle

0 0 1 Retry Response

0 1 0 Deferred Response

0 1 1 Reserved Reserved 1 0 0 Hard Failure Not suppor ted.

1 0 1 No Data Response

1 1 0 Implicit Writeback

111

Normal Data Response

To avoid deadlock, this response is generated when a resource cannot currently be accessed by the processor. PCI-directed reads, writes, DRAM locked reads, AGP reads and writes can be retried.

This response can be returned for all transactions that can be executed ‘out of order.’ PCI-directed reads (memory, I/O and Interrupt Acknowledge) and writes (I/O only), and AGP directed reads (memory and I/O) and writes (I/O only) can be deferred.

This is for transactions where the data has already been transferred or for transactions where no data is transferred. Writes and zero length reads receive this response.

This response is given for those transac tions where the initial transactions snoop hits on a modified cache line.

This response is for transactions where data accompanies the response phase. Reads receive this response.

Special Cycles

A Special Cycle is defined when REQa[4:0] = 01000 and REQb[4:0]= xx001. The first address phase Aa[35:3]# is undef ined and can be driven to any value. Th e second address phase, Ab[15: 8]# defines the type of Special Cycle issued by the processor.

Table 4-3 specifies the cycle type and definition as well as the action taken by the 82443BX when the corresponding cycles are identified.

Table 4-7. Host Special Cycles with 82443BX

BE[7:0}#

0000 0000

0000 0001

0000 0010

0000 0011

0000 0100

Special

Cycle Type

NOP This transaction has no side-effects.

This transaction is issued when an agent detects a severe software error that

Shutdown

Flush

Halt

Sync

prevents further processing. This cycle is claimed by the 82443BX. The 82443BX issues a shutdown special cycle on the PCI bus. This cycle is retired on the CPU bus after it is terminated on the PCI via a master abort mechanism.

This transaction is issued when an agent has invalidated its internal caches without writing back any modified lines. The 82443BX claims this cycle and retires it.

This transaction is issued when an agent executes a HLT instruction and stops program ex ecution. This cycle i s claimed b y t he 82443BX and propagated to PCI as a Special Halt Cycle. This cycle is retired on the CPU bus after it is terminated on the PCI via a master abort mechanism.

This transaction is issued when an agent has written back all modified lines and has invalidated its internal caches. The 82443BX claims this cycle and retires it.

Action Taken

4-12

82443BX Host Bridge Datasheet

Page 99

Table 4-7. Host Special Cycles with 82443BX

Functional Description

BE[7:0}#

0000 0101

0000 0110

0000 0111

all others Reserved

NOTE:

1. None of the host bus special cycles is propagated to the AGP interface.

Special

Cycle Type

Flush Acknowledge

Stop Clock Acknowledge

SMI Acknowledge

This transaction is issued when an agent has completed a cache sync and flush operation in response to an earlier FLUSH# signal assertion. The 82443BX claims this cycle and retires it.

This transaction is issued when an agent enters Stop Clock mode. This cycle is claimed by the 82443BX and propagated to the PCI as a Special Stop Grant Cycle. This cycle is completed on the CPU bus after it is terminated on the PCI via a master abort mechanism.

This transaction is first issued when an agent enters the System Management Mode (SMM).

Action T aken

4.2.2 Symmetric Multiprocessor (SMP) Protocol Support

The Intel® 440BX AGPset is optimized for uniprocessor system and also supports the symmetrical multiprocessor configurations of up to two CPUs on the host bus.

When configured for dual-processor, the Intel

440BX AGPset-based platform must integrate an

I/O APIC functionality and WSC# sign aling mechanism must be enabled.

4.2.3 In-Order Queue Pipelining

The 82443BX interface to the CPU bus includes a four deep in-order queue to track pipelined bus transactions.

4.2.4 Frame Buffer Memory Su pport (USWC)

To allow for high speed write capability for graph ics, th e Pentium Pro processor family has introduced USWC memory type. The USWC (uncacheable, speculati v e, write-combining) memory type provides a write-combining buffering mechanism for write operations. A high percentage of graphics transactions are writes to the memory-mapped graphics region, normally known as the linear frame buffer. Reads and writes to USWC are non-cached and can have no side effects.

In the case of graphics, current 32-bit drivers (without modifications) would use Partial Write protocol to update the frame buffer. The highest performance write transaction on the CPU bus is the Line Write.

82443BX Host Bridge Datasheet

4-13

Page 100

Functional Description

4.3 DRAM Interface

The 82443BX integrates a main memory DRAM controller that supports a 64-bit or 72-bit (64-bit memory data plus 8 ECC) DRAM array. The DRAM types supported are Synchronous (SDRAM) and Extended Data Out (EDO). The 82443BX does not support mixing of SDRAM and EDO. When the CPU bus is running at 100 MHz, the 82443BX DRAM interface runs at 100 MHz (SDRAM only). When the CPU bus is operating at 66 MHz, the 824 43BX DRAM interf ace runs at 66 MHz (SDRAM or EDO). EDO DRAM technology is supported in mobile designs only at 66 MHz. The DRAM controller interface is fully configurable through a set of control registers. Complete descriptions of these registers are given in the Register Section. A brief overview of the registers which configure the DRAM interface is provided in this section.

The 82443BX supports industry standard 64/72-bit wide DIMM modules with SDRAM and EDO DRAM devices. The fourteen multiplexed address lines, MA[13:0], allow the 82443BX to support 1M, 2M, 4M, 8M, and 16M x72/64 DIMMs. Both symmetric and asymmetric addressing is supported. The 82443BX has sixteen CS# lines, used in pairs enabling the support of up to eight 64/72-bit rows of DRAM. For write operations of less than a QWord in size, the 82443BX will either perform a byte-wise write (non-ECC protected configuration) or a read-modify-write cycle by merging the write data on a byte basis with the previously read data (ECC or EC configurations). The 82443BX targets 60 ns EDO DRAMs and SDRAM with CL2 and CL3 and supports both single and double-sided DIMMs. When usi ng EDO DRAM, up to 6 ro ws of memory ar e support ed. The 82443BX provides refresh functionality with programmable rate (normal DRAM rate is 1 refresh/15.6ms). When using SDRAMs the 82443BX can be configured via the Paging Policy Register to keep multiple pages open within the memory array. Pages can be kept open in all rows of memory. When 4 bank SDRAM devices (64Mb technology) are used for a particular row, up to 4 pages can be kept open within that row.

The DRAM interface of the 82443BX is configured by the DRAM Control Register, DRAM Timing Register, SDRAM Control Register, bits in the NBXCFG and the eight DRAM Row Boundary (DRB) Registers. The DRAM configuration registers noted above control the DRAM interface to select EDO or SDRAM DRAMs, RAS timings, and CAS rates. The eight DRB Registers define the size of each row in the memory array, enabling the 82443BX to assert the proper CSA/B# pair for accesses to the array.

4.3.1 DRAM Organization and Configuration

The 82443BX supports 64/72-bit DRAM configurations. In the following discussion the term row refers to a set of memory devices that are simultaneously selected by a CSA/B# or RASA/B# pair. The 82443BX will support a maximum of 8 rows of memory when using SDRAMs in a desktop configuration. Up to 6 rows of memory are supported when using EDO DRAM. A row may be composed of discrete DRAM devices, single-sided or double-sided DIMMs.

The 82443BX has multiple copies of many of the signals interfacing to memory. The interface consists of the following pins.

Multiple copies

•

— MAA[13:0], MAB[12:11,9:0]# and MAB[13,10] — CSA[7:0]#, CSB[7:0]# —SRASA#, SRASB# —SCASA#, SCASB# — WEA#, WEB# — DQMA[7:0], DQMB[5,1] — CKE[5:0] (for 3 DIMM configuration)

4-14

82443BX Host Bridge Datasheet

Datasheet 82443BX Datasheet (Standard Microsystems Corporation)

Specifications and Main Features

Frequently Asked Questions

User Manual

Intel 82443BX Features

Contents

Figures

Tables

Architectural Overview

Signal Description

2.1 Host Interface Signals

2.2 DRAM Interface

2.3 PCI Interface (Primary)

2.4 Primary PCI Sideband Interface

2.5 AGP Interface Signals

2.6 Clocks, Reset, and Miscellaneous

2.7 Power-Up/Reset Strap Options

Register Description

3.1 I/O Mapped Registers

3.2 PCI Configuration Space Access

3.3 Host-to-PCI Bridge Registers (Device 0)

3.4 PCI-to-PCI Bridge Registers (Device 1)

Functional Description

4.1 System Address Map

4.2 H ost Interface

4.3 DRAM Interface