Datasheet 80C88 Datasheet (intersil)

Page 1

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80C88

Data Sheet February 22, 2008

CMOS 8-/16-Bit Microprocessor

The Intersil 80C88 high performance 8-/16-bit CMOS CPU is manufactured using a self-aligned silicon gate CMOS process (Scaled SAJI IV). Two modes of operation, MINimum for small systems and MAXimum for larger applications such as multiprocessing, allow user configuration to achieve the highest performance level.

Full TTL compatibility (with the exception of CLOCK) and industry-standard operation allow use of existing NMOS 8088 hardware and Intersil CMOS peripherals.

Complete software compatibility with the 80C86, 8086, and 8088 microprocessors allows use of existing software in new designs.

FN2949.4

Features

• Compatible with NMOS 8088

• Direct Software Compatibility with 80C86, 8086, 8088

• 8-Bit Data Bus Interface; 16-Bit Internal Archi tecture

• Completely Static CMOS Design

- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5MHz (80C88)

- DC . . . . . . . . . . . . . . . . . . . . . . . . . . . .8MHz (80C88-2)

• Low Power Operation

- ICCSB. . . . . . . . . . . . . . . . . . . . . . . . . 500µA Maximum

- ICCOP . . . . . . . . . . . . . . . . . . . . .10mA/MHz Maximum

• 1 Megabyte of Direct Memory Addressing Capability

• 24 Operand Addressing Modes

• Bit, Byte, Word, and Block Move Operations

• 8-Bit and 16-Bit Signed/Unsigned Arithmetic

• Bus-Hold Circuitry Eliminates Pull-up Resistors

• Wide Operating Temperature Ranges

- C80C88 . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

- I80C88 . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

- M80C88 . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C

• Pb-Free Available (RoHS Compliant)

Ordering Information

TEMPERATURE

PART NUMBER

(5MHz)

CP80C88 CP80C88 CP80C88-2 CP80C88-2 0 to +70 40 LD PDIP E40.6

IP80C88 IP80C88 IP80C88-2 IP80C88-2 -40 to +85 40 LD PDIP E40.6

MD80C88/B MD80C88/B -55 to +125 40 LD CERDIP F40.6

CP80C88Z (Note)

NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

PART

MARKING

CP80C88Z 0 to +70 40 LD PDIP*

PART NUMBER

(8MHz)

PART

MARKING

RANGE

(°C) PACKAGE PKG. DWG. #

(Pb-Free)

E40.6

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774

| Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

Page 2

Pinouts

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80C88

(40 LD PDIP, 40 LD CERIDP)

GND

A14

A13

A12

A11

A10

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

NMI

INTR

CLK

GND

TOP VIEW

MIN MAX

A15

A16/S3

A17/S4

A18/S5

A19/S6

SS0

MN/MX

HOLD

HLDA

IO/M

DT/R

DEN

ALE

INTA

TEST

READY

RESET

MODEMODE

(HIGH)

(RQ/GT0)

(RQ

/GT1)

)

(LOCK

(S2

)

(S1

)

(S0

(QS0)

(QS1)

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February 22, 2008

Page 3

Functional Diagram

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EXECUTION UNIT

DATA POINTER

AND

INDEX REGS

(8 WORDS)

80C88

BUS INTERFACE UNIT

RELOCATION

SEGMENT REGISTERS

INSTRUCTION POINTER

AND

(5 WORDS)

TEST

INTR

NMI

/GT0, 1

HOLD HLDA

16-BIT ALU

FLAGS

CONTROL AND TIMING

CLK RESET READY

MEMORY INTERFACE

MN/MX

C-BUS

BUS

INTERFACE

UNIT

4-BYTE

INSTRUCTION

QUEUE

GND V

LOCK

QS0, QS1

, S1, S0

SSO/HIGH

A19/S6. . . A16/S3

AD7-AD0

A8-A15

, RD, WR

INTA

DT/R, DEN, ALE, IO/M

BUS

INTERFACE

UNIT

EXECUTION

UNIT

AH BH

B-BUS

AL BL CL

INSTRUCTION

STREAM BYTE

QUEUE

A-BUS

ARITHMETIC/

LOGIC UNIT

FLAGS

EXECUTION UNIT

CONTROL SYSTEM

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80C88

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Pin Description

The following pin function descriptions are for 80C88 systems in either minimum or maximum mode. The “local bus” in these descriptions is the direct multiplexed bus in te rf ace c onn ection to the 80C88 (without regard to additional bus buffers).

SYMBOL

MAXIMUM OR MINIMUM MODE. THE “LOCAL BUS” IN THESE DESCRIPTIONS IS THE DIRECT MULTIPLEXEDBUS INTERFACE CONNECTION TO THE 80C88 (WITHOUT REGARD TO ADDITIONAL BUS BUFFERS).

AD7 thru

AD0

A15,

A14 thru A8

A19/S6, A18/S5, A17/S4,

A16/S3

READY 22 I READY: is the acknowledgment from the address memory or I/O device that it will complete the data

INTR 18 I INTERRUPT REQUEST: is a level triggered input which is sampled during the last clock cycle of each

TEST

NMI 17 I NONMASKABLE INTERRUPT : is an edge triggered input which causes a type 2 interrupt. A subroutine is

RESET 21 I RESET: cases the processor to immediately terminate its present activity . The signal must transition LOW

CLK 19 I CLOCK: provides the basic timing for the processor and bus controller. It is asymmetric with a 33% duty

GND 1, 20 GND: are the ground pins (both pins must be connected to system ground). A 0.1µF capacitor between

MN/MX

NUMBER TYPE DESCRIPTION

9 thru 16 I/O ADDRESS DATA BUS: These lines constitute the time multiplexed memory/IO address (T1) and data

(T2,T3,Tw and T4) bus. These lines are active HIGH and are held at high impedance to the last valid level during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”

39, 2 thru 8 O ADDRESS BUS: These lines provide address bits 8 through 15 for the entire bus cycle (T1-T4). These

lines do not have to be latched by ALE to remain valid. A15-A8 are active HIGH and are held at high impedance to the last valid logic level during interrupt acknowledge and local bus “hold acknowledge” or “grant sequence”.

35 36 37 38

32 O READ: Read strobe indicates that the processor is performing a memory or I/O read cycle, depending on

23 I TEST: input is examined by the “wait for test” instruction. If the TEST input is LOW, execution continues,

40 VCC: is the +5V power supply pin. A 0.1µF capacitor between pins 20 and 40 recommended for

33 I MINIMUM/MAXIMUM: indicates the mode in which the processor is to operate. The two modes are

ADDRESS/STATUS: During T1, these are the four most

significant address lines for memory operations. During I/O

operations, these lines are LOW. During memory and I/O

operations, status information is available on these lines during T2, T3, TW and T4. S6 is always LOW. The status of the interrupt enable flag bit (S5) is updated at the beginning of each clock cycle. S4 and S3 are encoded as shown.

This information indicates which segment register is presently being used for data accessing.

These lines are held at high impedance to the last valid logic level during local bus “hold acknowledge” or “grant Sequence”.

the state of the IO/M

is active LOW during T2, T3, Tw of any read cycle, and is guaranteed to remain HIGH in T2 until the

RD 80C88 local bus has floated. This line is held at a high impedance logic one state during “hold acknowledge” or “grant sequence”.

transfer. The RDY signal from memory or I/O is synchronized by the 82C84A clock generator to from READY. This signal is active HIGH. The 80C88 READY input is not synchronized. Correct operation is not guaranteed if the set up and hold times are not met.

instruction to determine if the processor should enter into an interrupt acknowledge operation. A subroutine is vectored to via an interrupt vector lookup table located in system memory. It can be internally masked by software resetting the interrupt enable bit. INTR is internally synchronized. This signal is active HIGH.

otherwise the processor waits in an “idle” state. This input is synchronized internally during each clock cycle on the leading edge of CLK.

vectored to via an interrupt vector lookup table located in system memory. NMI is not maskable internally by software. A transition from a LOW to HIGH initiates the interrupt at the end of the current instruction. This input is internally synchronized.

to HIGH and remain active HIGH for at least four clock cycles. It restarts execution, as described in the instruction set description, when RESET returns LOW. RESET is internally synchronized.

cycle to provide optimized internal timing.

decoupling.

pins 1 and 20 is recommended for decoupling.

discussed in the following sections.

pin or S2. This signal is used to read devices which reside on the 80C88 local bus.

S4 S3 CHARACTERISTICS

0 0 Alternate Data 01Stack 1 0 Code or None 11Data

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80C88

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Pin Description

The following pin function descriptions are for 80C88 system in minimum mode (i.e., MN/MX = VCC). Only the pin functions which are unique to the minimum mode are described; all other pin functions are as described above.

SYMBOL

MINIMUM MODE SYSTEM (i.e., MN/MX

IO/M 28 O STATUS LINE: is an inverted maximum mode S2. It is used to distinguish a memory access from an I/O

WR 29 O Write: strobe indicates that the processor is performing a write memory or write I/O cycle, depending on

INTA

ALE 25 O ADDRESS LATCH ENABLE: is provided by the processor to latch the address into the 82C82/82C83

DT/R

DEN

HOLD,

HLDA

SS0

NUMBER TYPE DESCRIPTION

= VCC)

access. IO/M (I/O = HIGH, M = LOW). IO/M

the state of the IO/M to high impedance logic one during local bus “hold acknowledge”.

24 O INTA: is used as a read strobe for interrupt acknowledge cycles. It is active LOW during T2, T3 and T w of

each interrupt acknowledge cycle. Note that INTA

address latch. It is a HIGH pulse active during clock low of T1 of any bus cycle. Note that ALE is never floated.

27 O DATA TRANSMIT/RECEIVE: is needed in a minimum system that desires to use an 82C86/82C87 data

26 O DATA ENABLE: is provided as an output enable for the 82C86/82C87 in a minimum system which uses

31 30

34 O STATUS LINE: is logically equivalent to S0 in

bus transceiver. It is used to control the direction of data flow through the transceiver. Logically, DT/R equivalent to S1 signal is held to a high impedance logic one during local bus “hold acknowledge”.

the transceiver. DEN or INTA the beginning of T2 until the middle of T4. DEN acknowledge”.

HOLD: indicates that another master is requesting a local bus “hold”. To be acknowledged, HOLD must be

active HIGH. The processor receiving the “hold” request will issue HLDA (HIGH) as an acknowledgment, in the middle of a T4 or T1 clock cycle. Simultaneous with the issuance of HLDA the processor will float the local bus and control lines. After HOLD is detected as being LOW, the processor lowers HLDA, and when the processor needs to run another cycle, it will again drive the local bus and control lines. Hold is not an asynchronous input. External synchronization should be provided if the system cannot otherwise guarantee the set up time.

the maximum mode. The combination of SS0 IO/M decode the current bus cycle status. SS0 to high impedance logic one during local bus “hold acknowledge”.

becomes valid in the T4 preceding a bus cycle and remains valid until the final T4 of the cycle

is held to a high impedance logic one during local bus “hold acknowledge”.

signal. WR is active for T2, T3, and Tw of any write cycle. It is active LOW, and is held

is never floated.

in the maximum mode, and its timing is the same as for IO/M (T = HIGH, R = LOW). This

is active LOW during each memory and I/O access, and for INTA cycles. For a read

cycle, it is active from the middle of T2 until the middle of T4, while for a write cycle, it is active from

is held to high impedance logic one during local bus “hold

IO/M DT/R SS0 CHARACTERISTICS

and DT/R allows the system to completely

is held

1 0 0 Interrupt Acknowledge 1 0 1 Read I/O Port 1 1 0 Write I/O Port 111Halt 0 0 0 Code Access 0 0 1 Read Memory 0 1 0 Write Memory 011Passive

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80C88

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Pin Description (Continued)

The following pin function descriptions are for 80C88 system in maximum mode (i.e., MN/MX = GND). Only the pin functions which are unique to the maximum mode are described; all other pin functions are as described above.

SYMBOL

MAXIMUM MODE SYSTEM (i.e., MN/MX

S0 S1 S2

NUMBER TYPE DESCRIPTION

= GND).

26 27 28

STATUS: is active during clock high of T4, T1 and T2,

and is returned to the passive state (1, 1, 1) during T3 or

during Tw when READY is HIGH. This status is used by the 82C88 bus controller to generate all memory and I/O access control signals. Any change by S2 during T4 is used to indicate the beginning of a bus cycle, and the return to the passive state in T3 or Tw is used to indicate the end of a bus cycle. These signals are held at a high impedance logic one state during “grant sequence”.

, S1 or S0

S2 S1 S0 CHARACTERISTICS

0 0 0 Interrupt Acknowledge 001 Read I/O Port 010 Write I/O Port 011 Halt 100 Code Access 101 Read Memory

1 1 0 Write Memory 1 11Passive

/GT0,

RQ RQ/GT1

LOCK

31 30

29 O LOCK: indicates that other system bus masters are not to gain control of the system bus while LOCK is

I/O REQUEST/GRANT: pins are used by other local bus masters to force the processor to release the local

bus at the end of the processor’s current bus cycle. Each pin is bidirectional with RQ/GT0 having higher priority than RQ The request/grant sequence is as follows (see RQ

1. A pulse of one CLK wide from another local bus master indicates a local bus request (“hold”) to the 80C88 (pulse 1).

2. During a T4 or T1 clock cycle, a pulse one clock wide from the 80C88 to the requesting master (pulse

2), indicates that the 80C88 has allowed the local bus to float and that it will enter the “grant sequence” state at the next CLK. The CPUs bus interface unit is disconnected logically from the local bus during “grant sequence”.

3. A pulse one CLK wide from the requesting master indicates to the 80C88 (pulse 3) that the “hold” request is about to end and that the 80C88 can reclaim the local bus at the next CLK. The CPU then enters T4 (or T1 if no bus cycles pending).

Each master-master exchange of the local bus is a sequence of three pulses. There must be one idle CLK cycle after bus exchange. Pulses are active LOW. If the request is made while the CPU is performing a memory cycle, it will release the local bus during T4 of the cycle when all the following conjugations are met:

1. Request occurs on or before T2.

2. Current cycle is not the low bit of a word.

3. Current cycle is not the first acknowledge of an interrupt acknowledge sequence.

4. A locked instruction is not currently executing.

If the local bus is idle when the request is made the two possible events will follow:

1. Local bus will be released during the next clock.

2. A memory cycle will start within 3 clocks. Now the four rules for a currently active memory cycle apply with condition number 1 already satisfied.

active (LOW). The LOCK completion of the next instruction. This signal is active LOW, and is held at a high impedance logic one state during “grant sequence”. In Max Mode, LOCK cycle and removed during T2 of the second INTA

/GT1. RQ/GT has internal bus-hold high circuitry and, if unused, may be left unconnected.

/GT Timing Sequence):

signal is activated by the “LOCK” prefix instruction and remains active until the

is automatically generated during T2 of the first INTA

cycle.

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80C88

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Pin Description (Continued)

SYMBOL

MAXIMUM MODE SYSTEM (i.e., MN/MX

QS1, QS0 24, 25 O QUEUE STATUS: provide status to allow external

NUMBER TYPE DESCRIPTION

= GND).

tracking of the internal 80C88 instruction queue. The queue status is valid during the CLK cycle after which the queue operation is performed. Note that the queue status never goes to a high impedance statue (floated).

34 O Pin 34 is always a logic one in the maximum mode and is held at a high impedance logic one during a “grant

sequence”.

QS1 QS0 CHARACTERISTICS

00No Operation 0 1 First Byte of Opcode from

Queue 1 0 Empty the Queue 1 1 Subsequent Byte from

Queue

Functional Description

Static Operation

All 80C88 circuitry is static in design. Internal registers, counters and latches are static and require not refresh as with dynamic circuit design. This eliminates the minimum operating frequency restriction placed on other microprocessors. The CMOS 80C88 can operate from DC to the specified upper frequency limit. The processor clock may be stopped in either state (high/low) and held there indefinitely. This type of operation is especially useful for system debug or power critical applications.

The 80C88 can be single stepped using only the CPU clock. This state can be maintained as long as is necessary. Single step clock operation allows simple interface circuitry to provide critical information for start-up.

Static design also allows very low frequency operation (as low as DC). In a power critical situation, this can provide extremely low power operation since 80C88 power dissipation is directly related to operation frequency. As the system frequency is reduced, so is the operating power until, at a DC input frequency, the power requirement is the 80C88 standby current.

Internal Architecture

The internal functions of the 80C88 processor are partitioned logically into two processing units. The first is the Bus Interface Unit (BIU) and the second is the Execution Unit (EU) as shown in the CPU block diagram.

this unit serves to increase processor performance through improved bus bandwidth utilization. Up to 4-bytes of the instruction stream can be queued while waiting for decoding and execution.

The instruction stream queuing mechanism allows the BIU to keep the memory utilized very efficiently. Whenever there is space for at least 1-byte in the queue, the BIU will attempt a byte fetch memory cycle. This greatly reduces “dead time”: on the memory bus. The queue acts as a First-In-First-Out (FIFO) buffer, from which the EU extracts instruction bytes as required. If the queue is empty (following a branch instruction, for example), the first byte into the queue immediately becomes available to the EU.

The execution unit receives pre-fetched instructions from the BIU queue and provides unrelocated operand addresses to the BIU. Memory operands are passed through the BIU for processing by the EU, which passes results to the BIU for storage.

Memory Organization

The processor provides a 20-bit address to memory which locates the byte being referenced. The memory is organized as a linear array of up to 1 million bytes, addressed as 00000(H) to FFFFF(H). The memory is logically divided into code, data, extra, and stack segments of up to 64-bytes each, with each segment falling on 16-byte boundaries. (See Figure 1).

These units can interact directly but for the most part perform as separate asynchronous operational processors. The bus interface unit provides the functions related to instruction fetching and queuing, operand fetch and store, and address relocation. This unit also provides the basic bus control. The overlap of instruction pre-fetching provided by

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80C88

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SEGMENT

64K-BIT

+ OFFSET

FIGURE 1. MEMORY ORGANIZATION

WORD

LSB

BYTE

MSB

FFFFFH

CODE SEGMENT

XXXXOH

STACK SEGMENT

DATA SEGMENT

EXTRA SEGMENT

00000H

All memory references are made relative to base addresses contained in high speed segment registers. The segment types were chosen based on the addressing needs of programs. The segment register to be selected is automatically chosen according to specific rules as shown in Table1. All information in one se gment type share the same logical attributes (e.g., code or data). By structuring memory into relocatable areas of similar characteristics and by automatically selecting segment registers, programs are shorter, faster, and more structured.

TABLE 1.

MEMORY

REFERENCE

NEED

Instructions CODE (CS) Automatic with all instruction

Stack STACK (SS) All stack pushes and pops.

Local Data DATA (DS) Data references when: relative

External Data (Global)

SEGMENT

USED

prefetch.

Memory references relative to BP base register except data references.

to stack, destination of string operation, or explicitly overridden.

EXTRA (ES) Destination of string

operations: Explicitly selected using a segment override.

SEGMENT

SELECTION RULE

Word (16-bit) operands can be located on even or odd address boundaries. For address and data operands, the least significant byte of the word is stored in the lower valued address location and the most significant byte in the next higher address location.

Certain locations in memory are reserved for specific CPU operations. (See Figure 2). Locations from addresses FFFF0H through FFFFFH are reserved for operations including a jump to initial system initialization routine. Following RESET, the CPU will always begin execution at location FFFF0H where the jump must be located. Locations 00000H through 003FFH are reserved for interrupt operations. Each of the 256 possible interrupt service routines is accessed through its own pair of 16-bit pointers segment address pointer and offset address pointer. The first pointer, used as the offset address, is loaded into the IP, and the second pointer, which designates the base address, is loaded into the CS. At this point program control is transferred to the interrupt routine. The pointer elements are assumed to have been stored at their respective places in reserved memory prior to the occurrence of interrupts.

Minimum and Maximum Modes

The requirements for supporting minimum and maximum 80C88 systems are sufficiently different that they cannot be done efficiently with 40 uniquely defined pins. Consequently, the 80C88 is equipped with a strap pin (MN/MX defines the system configuration. The definition of a certain subset of the pins changes, dependent on the condition of the strap pin. When the MN/MX

pin is strapped to GND, the

80C88 defines pins 24 through 31 and 34 in maximum mode. When the MN/MX

pins is strapped to VCC, the 80C88 generates bus control signals itself on pins 24 through 31 and 34.

The minimum mode 80C88 can be used with either a muliplexed or demultiplexed bus. This architecture provides the 80C88 processing power in a highly integrated form.

The demultiplexed mode requires one latch (for 64k address ability) or two latches (for a full megabyte of addressing). An 82C86 or 82C87 transceiver can also be used if data bus buffering is required. (See Figure 3). The 80C88 provides DEN

and DT/R to control the transceiver, and ALE to latch the addresses. This configuration of the minimum mode provides the standard demultiplexed bus structure with heavy bus buffering and relaxed bus timing requirements.

The maximum mode employs the 82C88 bus controller (See Figure 4). The 82C88 decode status lines S0, S1 and S2, and provides the system with all bus control signals. Moving the bus control to the 82C88 provides better source and sink current capability to the control lines, and frees the 80C88 pins for extended large system features. Hardware lock, queue status, and two request/grant interfaces are provided by the 80C88 in maximum mode. These features allow coprocessors in local bus and remote bus configurations.

) which

The BIU will automatically execute two fetch or write cycles for 16-bit operands.

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80C88

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AVAILABLE INTERRUPT

POINTERS

(224)

RESERVED

INTERRUPT

POINTERS

(27)

DEDICATED INTERRUPT

POINTERS

(5)

FFFFFH

FFFF0H

3FFH

3FCH

084H

080H

07FH

014H

010H

00CH

008H

004H

000H

RESET BOOTSTRAP

PROGRAM JUMP

TYPE 255 POINTER

(AVAILABLE)

TYPE 33 POINTER

(AVAILABLE)

TYPE 32 POINTER

(AVAILABLE)

TYPE 31 POINTER

(AVAILABLE)

TYPE 5 POINTER

(RESERVED)

TYPE 4 POINTER

OVERFLOW

TYPE 3 POINTER

1 BYTE INT INSTRUCTION

TYPE 2 POINTER NON MASKABLE

TYPE 1 POINTER

SINGLE STEP

TYPE 0 POINTER

DIVIDE ERROR

CS BASE ADDRESS

IP OFFSET

16-BITS

FIGURE 2. RESERVED MEMORY LOCATIONS

Bus Operation

The 80C88 address/data bus is broken into three parts: the lower eight address/data bits (AD0-AD7), the middle eight address bits (A8-A15), and the upper four address bits (A16A19). The address/data bits and the highest four address bits are time multiplexed. This technique provides the most efficient use of pins on the processor, permitting the use of standard 40 lead package. The middle eight address bits are not multiplexed, i.e., they remain valid throughout each bus cycle. In addition, the bus can be demultiplexed at the processor with a single address latch if a standard, non multiplexed bus is desired for the system.

Each processor bus cycle consists of at least four CLK cycles. These are referred to as T1, T2, T3 and T4. (See Figure 5). The address is emitted from the processor during T1 and data transfer occurs on the bus during T3 and T4. T2 is used primarily for changing the direction of the bus during read operations. In the event that a “Not Ready” indication is given by the addressed device, “wait” states (TW) are inserted between T3 and T4. Each inserted “wait” state is of the same duration as a CLK cycle. Periods can occur between 80C88 driven bus cycles. These are referred to as “idle” states (TI), or inactive CLK cycles. The processor uses these cycles for internal housekeeping.

During T1 of any bus cycle, the ALE (Address latch enable) signal is emitted (by either the processor or the 82C88 bus controller, depending on the MN/MX

strap). At the trailing edge of this pulse, a valid address and certain status information for the cycle may be latched.

Status bits S0

, S1, and S2 are used by the bus controller, in maximum mode, to identify the type of bus transaction according to Table 2.

Status bits S3 through S6 are multiplexed with high order address bits and are therefore valid during T2 through T4. S3 and S4 indicate which segment register was used to this bus cycle in forming the address according to Table 3.

S5 is a reflection of the PSW interrupt enable bit. S6 is always equal to 0.

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80C88

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GND

82C84A/85

RES

RDY

CLOCK

GENERATOR

C1 = C2 = 0.1μF

CLK

READY

RESET

80C88

CPU

GND

AD0-AD7

GND

INTR

MN/MX

IO/M

INTA

DT/R

DEN

ALE

A8-A19

STB

GND

ADDR/DATA

82C82

LATCH

(1, 2 OR 3)

82C86

TRANSCEIVER

82C59A

INTERRUPT

CONTROL

INT

ADDRESS

DATA

HM-65162

CMOS PROM

FIGURE 3. DEMULTIPLEXED BUS CONFIGURATION

IR0-7

HS-6616

CMOS PROM

CS RDWR

82CXX

PERIPHERALS

GND

82C84A/85

RES

RDY

C1 = C2 = 0.1μF

CLK

S1 S2 DEN DT/R ALE

STB

(1, 2 OR 3)

TRANSCEIVER

82C88

82C82

LATCH

82C86

MRDC MWTC

AMWC

AIOWC

IORC

IOWC

INTA

INTERRUPT

ADDRESS

DATA

82C59A

CONTROL

CLK

READY

RESET

80C88

CPU

GND

AD0-AD7

GND

INT

MN/MX

A8-A19

GND

ADDR/DATA

FIGURE 4. FULLY BUFFERED SYSTEM USING BUS CONTROLLER

HM-65162

CMOS PROM

IR0-7

HS-6616

CMOS PROM

CS RDWR

82CXX

PERIPHERALS

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80C88

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CLK

ALE

-S0

ADDR

STATUS

ADDR

ADDR DATA

, INTA

READY

(4 + NWAIT) = TCY

T1 T2 T3 T4TWAIT T1 T2 T3 T4TWAIT

A19-A16

A7-A0

S6-S3

A15-A8

BUS RESERVED

FOR DATA IN

D15-D0

VALID

A19-A16

(4 + NWAIT) = TCY

GOES INACTIVE IN THE STATE

JUST PRIOR TO T4

S6-S3

A15-A8

A7-A0 DATA OUT (D7-D0)

READYREADY

WAIT WAIT

DT/R

DEN

MEMORY ACCESS TIME

FIGURE 5. BASIC SYSTEM TIMING

TABLE 2.

0 0 0 Interrupt Acknowledge 0 0 1 Read I/O 010Write I/O 011Halt 1 0 0 Instruction Fetch 1 0 1 Read Data from Memory 1 1 0 Write Data to Memory 111 Passive (No Bus Cycle)

S1 S0 CHARACTERISTICS

TABLE 3.

S4 S3 CHARACTERISTICS

0 0 Alternate Data (Extra Segment) 01Stack 1 0 Code or None 11Data

I/O Addressing

In the 80C88, I/O operations can address up to a maximum of 64k I/O registers. The I/O address appears in the same format as the memory address on bus lines A15-A0. The address lines A19-A16 are zero in I/O operations. The variable I/O instructions, which use register DX as a pointer, have full address capability, while the direct I/O instructions directly address one or two of the 256 I/O byte locations in page 0 of the I/O address space. I/O ports are addressed in the same manner as memory locations.

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80C88

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Designers familiar with the 8085 or upgrading an 8085 design should note that the 8085 addresses I/O with an 8-bit address on both halves of the 16-bit address bus. The 80C88 uses a full 16-bit address on its lower 16 address lines.

External Interface

Processor Reset and Initialization

Processor initialization or start up is accomplished with activation (HIGH) of the RESET pin. The 80C88 RESET is required to be HIGH for greater than four clock cycles. The 80C88 will terminate operations on the high-going edge of RESET and will remain dormant as long as RESET is HIGH. The low-going transition of RESET triggers an internal reset sequence for approximately 7 clock cycles. After this interval the 80C88 operates normally, beginning with the instruction in absolute location FFFFOH (see Figure 2). The RESET input is internally synchronized to the processor clock. At initialization, the HIGH to LOW transition of RESET must occur no sooner than 50μs after power up, to allow complete initialization of the 80C88.

NMI will not be recognized if asserted prior to the second CLK cycle following the end of RESET.

appropriate element to the new interrupt service program location.

BOND

PAD

OUTPUT

DRIVER

INPUT

BUFFER

FIGURE 6A. BUS HOLD CIRCUITRY PINS 2-16 AND 35-39

OUTPUT

DRIVER

INPUT

BUFFER

FIGURE 6B. BUS HOLD CIRCUITRY PINS 26-32 AND 34

INPUT

PROTECTION

CIRCUITRY

INPUT

PROTECTION

CIRCUITRY

FIGURE 6.

BOND

PAD

EXTERNAL PIN

Bus Hold Circuitry

To avoid high current conditions caused by floating inputs to CMOS devices and to eliminate the need for pull-up/down resistors, “bus-hold” circuitry has been used on 80C88 pins 2-16, 26-32 and 34-39 (see Figure 6A and 6B). These circuits maintain a valid logic state if no driving source is present (i.e., an unconnected pin or a driving source which goes to a high impedance state).

T o override the “bus hold” circuits, an external driver must be capable of supplying 400μA minimum sink or source current at valid input voltage levels. Since this “bus hold” circuitry is active and not a “resistive” type element, the associated power supply current is negligible. Power dissipation is significantly reduced when compared to the use of passive pull-up resistors.

Interrupt Operations

Interrupt operations fall into two classes: software or hardware initiated. The software initiated interrupts and software aspects of hardware interrupts are specified in the instruction set description. Hardware interrupts can be classified as nonmusical or maskable.

Interrupts result in a transfer of control to a new program location. A 256 element table containing address pointers to the interrupt service program locations resides in absolute locations 0 through 3FFH (see Figure 2), which are reserved for this purpose. Each element in the table is 4-bytes in size and corresponds to an interrupt “type”. An interrupting device supplies an 8-bit type number, during the interrupt acknowledge sequence, which is used to vector through the

Non-Maskable Interrupt (NMI)

The processor provides a single non-maskable interrupt (NMI) pin which has higher priority than the maskable interrupt request (INTR) pin. A typical use would be to activate a power failure routine. The NMI is edge-triggered on a LOW to High transition. The activation of this pin causes a type 2 interrupt.

NMI is required to have a duration in the HIGH state of greater than two clock cycles, but is not required to be synchronized to the clock. An high going transition of NMI is latched on-chip and will be serviced at the end of the current instruction or between whole moves (2-bytes in the case of word moves) of a block type instruction. Worst case response to NMI would be for multiply, divide, and variable shift instructions. There is no specification on the occurrence of the low-going edge; it may occur before, during, or after the servicing of NMI. Another high-going edge triggers another response if it occurs after the start of the NMI procedure.

The signal must be free of logical spikes in general and be free of bounces on the low-going edge to avoid triggering extraneous responses.

Maskable Interrupt (INTR)

The 80C88 provides a singe interrupt request input (INTR) which can be masked internally by software with the resetting of the interrupt enable (IF) flag bit. The interrupt request signal is level triggered. It is internally synchronized during each clock cycle on the high-going edge of CLK.

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80C88

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To be responded to, INTR must be present (HIGH) during the clock period preceding the end of the current instruction or the end of a whole move for a block type instruction. INTR may be removed anytime after the falling edge of the first INTA

signal. During interrupt response sequence, further interrupts are disabled. The enable bit is reset as part of the response to any interrupt (INTR, NMI, software interrupt, or single step). The FLAGS register, which is automatically pushed onto the stack, reflects the state of the processor prior to the interrupt. The enable bit will be zero until the old FLAGS register is restored, unless specifically set by an instruction.

During the response sequence (see Figure 7), the processor executes two successive (back-to-back) interrupt acknowledge cycles. The 80C88 emits to LOCK (maximum mode only) from T2 of the first bus cycle until T2 of the second. A local bus “hold” request will not be honored until the end of the second bus cycle. In the second bus cycle, a byte is fetched from the external interrupt system (e.g., 82C59A PIC) which identifies the source (type) of the interrupt. This byte is multiplied by four and used as a pointer into the interrupt vector lookup table.

An INTR signal left HIGH will be continually responded to within the limitations of the enable bit and sample period. INTR may be removed anytime after the falling edge of the first INTA flags pop which returns the status of the original interrupt enable bit when it restores the flags.

LOCK

signal. The interrupt return instruction includes a

T1 T2 T3 T4

ALE

INTA

AD0-

AD7

FIGURE 7. INTERRUPT ACKNOWLEDGE SEQUENCE

signal

TYPE

VECTOR

Halt

When a software HALT instruction is executed, the processor indicates that it is entering the HALT state in one of two ways, depending upon which mode is strapped. In minimum mode, the processor issues ALE, delayed by one clock cycle, to allow the system to latch the halt status. Halt status is available on IO/M mode, the processor issues appropriate HALT status on S2 S1

and S0, and the 82C88 bus controller issues one ALE. The 80C88 will not leave the HALT state when a local bus hold is entered while in HALT. In this case, the processor reissues the HALT indicator at the end of the local bus hold.

, DT/R, and SS0. In maximum

An interrupt request or RESET will force the 80C88 out of the HALT state.

Read/Modify/Write (Semaphore) Operations Via LOCK

The LOCK status information is provided by the processor when consecutive bus cycles are required during the execution of an instruction. This allows the processor to perform read/modify/write operations on memory (via the “exchange register with memory” instruction), without another system bus master receiving intervening memory cycles. This is useful in multiprocessor system configurations to accomplish “test and set lock” operations. The LOCK following decoding of the LOCK deactivated at the end of the last bus cycle of the instruction following the LOCK on a RQ end of the LOCK

signal is activated (LOW) in the clock cycle

prefix instruction. It is

prefix. While LOCK is active, a request

/GT pin will be recorded, and then honored at the

External Synchronization Via TEST

As an alternative to interrupts, th e 80 C 8 8 provides a single software-testable input pin (TEST executing a WAIT instruction. The single WAIT instruction is repeatedly executed until the TEST The execution of WAIT does not consume bus cycles once the queue is full.

If a local bus request occurs during WAIT execution, the 80C88 three-states all output drivers while inputs and I/O pins are held at valid logic levels by internal bus-hold circuits. If interrupts are enabled, the 80C88 will recognize interrupts and process them when it regains control of the bus.

). This input is utilized by

input goes active (LOW).

Basic System Timing

In minimum mode, the MN/MX pin is strapped to VCC and the processor emits bus control signals (RD directly. In maximum mode, the MN/MX GND and the processor emits coded status information which the 82C88 bus controller uses to generate MULTIBUS™ compatible bus control signals.

, WR, IO/M, etc.)

pin is strapped to

System Timing - Minimum System

The read cycle begins in T1 with the assertion of the address latch enable (ALE) signal (see Figure 5). The trailing (low going) edge of this signal is used to latch the address information, which is valid on the address data bus (ADOAD7) at this time, into the 82C82/82C83 latch. Address lines A8 through A15 do not need to be latched because they remain valid throughout the bus cycle. From T1 to T4 the IO/M

signal indicates a memory or I/O operation. At T2 the

address is removed from the address data bus and the bus is held at the last valid logic state by internal bus-hold devices. The read control signal is also asserted at T2. The read (RD data bus drivers to the local bus. Some time later, valid data

) signal causes the addressed device to enable its

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80C88

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will be available on the bus and the addressed device will drive the READY line HIGH. When the processor returns the read signal to a HIGH level, the addressed device will again three-state its bus drivers. If a transceiver (82C86/82C87) is required to buffer the local bus, signals DT/R provided by the 80C88.

A write cycle also begins with the assertion of ALE and the emission of the address. The IO/M to indicate a memory or I/O write operation. In T2, immediately following the address emission, the processor emits the data to be written into the addressed location. This data remains valid until at least the middle of T4. During T2, T3, and Tw, the processor asserts the write control signal. The write (WR T2, as opposed to the read, which is delayed somewhat into T2 to provide time for output drivers to become inactive.

The basic difference between the interrupt acknowledge cycle and a read cycle is that the interrupt acknowledge (INTA

) signal is asserted in place of the read (RD) signal and the address bus is held at the last valid logic state by internal bus-hold devices (see Figure 6. In the second of two successive INTA the data bus, as supplied by the interrupt system logic (i.e., 82C59A priority interrupt controller). This byte identifies the source (type) of the interrupt. It is multiplied by four and used as a pointer into the interrupt vector lookup table, as described earlier.

) signal becomes active at the beginning of

cycles, a byte of information is read from

signal is again asserted

and DEN are

Bus Timing - Medium Complexity Systems

For medium complexity systems, the MN/MX pin is connected to GND and the 82C88 bus controller is added to the system, as well as an 82C82/82C83 latch for latching the system address, and an 82C86/82C87 transceiver to allow for bus loading greater than the 80C88 is capable of handling (see Figure 8). Signals ALE, DEN generated by the 82C88 instead of the processor in this configuration, although their timing remains relatively the same. The 80C88 status outputs (S2 type of cycle information and become 82C88 inputs. This bus cycle information specifies read (code, data or I/O), write (data or I/O), interrupt acknowledge, or software halt. The 82C88 thus issues control signals specifying memory read or write, I/O read or write, or interrupt acknowledge. The 82C88 provides two types of write strobes, normal and advanced, to be applied as required. The normal write strobes have data valid at the leading edge of write. The advanced write strobes have the same timing as read strobes, and hence, data is not valid at the leading edge of write. The 82C86/82C87 transceiver receives the usual T and OE

The pointer into the interrupt vector table, which is passed during the second INTA located on either the local bus or the system bus. If the master 82C59A priority interrupt controller is positioned on the local bus, the 82C86/82C87 transceiver must be

inputs from the 82C88 DT/R and DEN outputs.

cycle, can derive from an 82C59A

, and DT/R are

, S1 and S0) provide

disabled when reading from the master 82C59A during the interrupt acknowledge sequence and software “poll”.

The 80C88 Compared to the 80C86

The 80C88 CPU is a 8-bit processor designed around the 8086 internal structure. Most internal functions of the 80C88 are identical to the equivalent 80C86 functions. The 80C88 handles the external bus the same way the 80C86 does with the distinction of handling only 8-bits at a time. Sixteen-bit operands are fetched or written in two consecutive bus cycles. Both processors will appear identical to the software engineer, with the exception of execution time. The internal register structure is identical and all instructions have the same end result. Internally, there are three differences between the 80C88 and the 80C86. All changes are related to the 8-bit bus interface.

• The queue length is 4-bytes in the 80C88, whereas the 80C86 queue contains 6-bytes, or three words. The queue was shortened to prevent overuse of the bus by the BIU when prefetching instructions. This was required because of the additional time necessary to fetch instructions 8-bits at a time.

• To further optimize the queue, the prefetching algorithm was changed. The 80C88 BIU will fetch a new instruction to load into the queue each time there is a 1-byte space available in the queue. The 80C86 waits until a 2-byte space is available.

The internal execution time of the instruction set is affected by the 8-bit interface. All 16-bit fetches and writes from/to memory take an additional four clock cycles. The CPU is also limited by the speed of instruction fetches. This latter problem only occurs when a series of simple operations occur. When the more sophisticated instructions of the 80C88 are being used, the queue has time to fill the execution proceeds as fast as the execution unit will allo w.

The 80C88 and 80C86 are completely software compatible by virtue of their identical execution units. Software that is system dependent may not be completely transferable, but software that is not system dependent will operate equally as well on an 80C88 or an 80C86.

The hardware interface of the 80C88 contains the major differences between the two CPUs. The pin assignments are nearly identical, however, with the following functional changes:

• A8-A15: These pins are only address outputs on the 80C88. These address lines are latched internally and remain valid throughout a bus cycle in a manner similar to the 8085 upper address lines.

•BHE

has no meaning on the 80C88 and has been

eliminated.

provides the S0 status information in the minimum

• SS0 mode. This output occurs on pin 34 in minimum mode

FN2949.4

February 22, 2008

Page 15

only. DT/R, IO/M and SS0 provide the complete bus status

www.BDTIC.com/Intersil

in minimum mode.

has been inverted to be compatible with the 8085

• IO/M bus structure.

• ALE is delayed by one clock cycle in the minimum mode when entering HALT, to allow the status to be latched with ALE.

T1 T2 T3 T4

CLK

QS1, QS0

80C88

, S1, S0

80C88

A19/S6 - A16/S3

READY

80C88

ALE

82C84RDY

80C88

AD7 - AD0

A15 - A8

DT/R

MRDC

DATA OUT

A19 - A16

A7-A0

S6 - S3

DATA IN

A15 - A8

DEN

FIGURE 8. MEDIUM COMPLEXITY SYSTEM TIMING

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80C88

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Absolute Maximum Ratings Thermal Information

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +8.0V

Input, Output or I/O Voltage. . . . . . . . . . . GND - 0.5V to V

ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1

+ 0.5V

Thermal Resistance (Typical). . . . . . . . . . . . . . . . . . . . . .

PDIP Package* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

CERDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Maximum Junction Temperature

Operating Conditions

Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . .+4.5V to +5.5V

M80C88-2 Only . . . . . . . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V

Operating Temperature Range

C80C88/-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

I80C88/-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C

M80C88 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-55°C to +125°C

Ceramic Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175°C

Plastic Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C

Storage Temperature Range . . . . . . . . . . . . . . . . . -65°C to +150°C

Pb-free reflow profile. . . . . . . . . . . . . . . . . . . . . . . . . . see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp *Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications.

Die Characteristics

Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9750 Gates

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.

(oC/W)

Electrical Specifications V

= 5.0V, ±10%; TA = 0°C to +70°C (C80C88, C80C88-2)

= 5.0V, ±10%; TA = -40°C to +85°C (l80C88, I80C88-2)

= 5.0V, ±10%; TA = -55°C to +125°C (M80C88)

SYMBOL PARAMETER TEST CONDITION MIN MAX UNITS

Logical One Input Voltage C80C88, I80C88 (Note 4) 2.0 - V

M80C88 (Note 4) 2.2 V

VIHC CLK Logical One Input Voltage V

Logical Zero Input Voltage - 0.8 V

- 0.8 - V

VILC CLK Logical Zero Input Voltage - 0.8 V

Output High Voltage lOH = -2.5mA 3.0 - V

lOH = -100µA V

- 0.4 V

Output Low Voltage lOL = +2.5mA - 0.4 V Input Leakage Current VIN = 0V or V

-1.0 1.0 µA

Pins 17 thru 19, 21 thru 23 and 33 lBHH Input Current-Bus Hold High V lBHL Input Current-Bus Hold Low V

Output Leakage Current V ICCSB Standby Power Supply Current V ICCOP Operating Power Supply Current FREQ = Max, V

= - 3.0V (Note 1) -40 -400 µA

= - 0.8V (Note 2) 40 400 µA

= 0V (Note 5) - -10.0 µA

OUT

= 5.5V (Note 3) - 500 µA

Outputs Open

= VCC or GND,

-10mA/MHz

NOTES:

1. lBHH should be measured after raising V

2. IBHL should be measured after lowering V

3. lCCSB tested during clock high time after HALT instruction executed. V

4. MN/MX

is a strap option and should be held to VCC or GND.

5. IO should be measured by putting the pin in a high impedance state and then driving V

to VCC and then lowering to 3.0V on the following pins 2 thru16, 26 thru 32, 34 thru 39.

to GND and then raising to 0.8V on the following pins: 2 thru16, 35 thru 39.

= VCC or GND, VCC = 5.5V, Outputs unloaded.

to GND on the following pins: 26-29 and 32.

OUT

Capacitance T

= +25°C

SYMBOL PARAMETER TEST CONDITIONS TYPICAL UNITS

Input Capacitance FREQ = 1MHz. All measurements are referenced to device GND 25 pF

Output Capacitance FREQ = 1MHz. All measurements are referenced to device GND 25 pF

OUT

CI/O I/O Capacitance FREQ = 1MHz. All measurements are referenced to device GND 25 pF

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80C88

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AC Electrical Specifications V

SYMBOL PARAMETER MINIMUM COMPLEXITY SYSTEM Timing Requirements

(1) TCLCL CLK Cycle Period 200 - 125 - ns (2) TCLCH CLK Low Time 118 - 68 - ns (3) TCHCL CLK High Time 69 - 44 - ns (4) TCH1CH2 CLK Rise Time From 1.0V to 3.5V - 10 - 10 ns (5) TCL2CL1 CLK FaIl Time From 3.5V to 1.0V - 10 - 10 ns (6) TDVCL Data In Setup Time 30 - 20 - ns (7) TCLDX1 Data In Hold Time 10 - 10 - ns (8) TR1VCL RDY Setup Time into 82C84A

(Notes 6,7)

(9) TCLR1X RDY Hold Time into

(10) TRYHCH READY Setup Time into 80C88 118 - 68 - ns (11) TCHRYX READY Hold Time into 80C88 30 - 20 - ns (12) TRYLCL READY Inactive to CLK (Note 8) -8 - -8 - ns

THVCH HOLD Setup Time 35 - 20 - ns

(13)

TINVCH lNTR, NMI, TEST Setup Time

(14)

(15) TILIH Input Rise Time (Except CLK) From 0.8V to 2.0V - 15 - 15 ns (16) TIHIL Input FaIl Time (Except CLK) From 2.0V to 0.8V - 15 - 15 ns

Timing Responses

(17) TCLAV Address Valid Delay CL = 100pF 10 110 10 60 ns (18) TCLAX Address Hold Time CL = 100pF 10 - 10 - ns (19) TCLAZ Address Float Delay CL = 100pF TCLAX 80 TCLAX 50 ns (20) TCHSZ Status Float Delay CL = 100pF - 80 - 50 ns (21) TCHSV Status Active Delay CL = 100pF 10 110 10 60 ns (22) TLHLL ALE Width CL = 100pF TCLCH-20 - TCLCH-10 - ns (23) TCLLH ALE Active Delay CL = 100pF - 80 - 50 ns (24) TCHLL ALE Inactive Delay CL = 100pF - 85 - 55 ns (25) TLLAX Address Hold Time to ALE

(26) TCLDV Data Valid Delay CL = 100pF 10 110 10 60 ns (27) TCLDX2 Data Hold Time CL = 100pF 10 - 10 - ns (28) TWHDX Data Hold Time After WR (29) TCVCTV Control Active Delay 1 CL = 100pF 10 110 10 70 ns (30) TCHCTV Control Active Delay 2 CL = 100pF 10 110 10 60 ns (31) TCVCTX Control Inactive Delay CL = 100pF 10 110 10 70 ns (32) TAZRL Address Float to READ Active CL = 100pF 0 - 0 - ns

(Notes 6,7)

(Note 7)

Inactive

= 5.0V ±10%; TA = 0°C to +70°C (C80C88, C80C88-2)

5.0V ±10%; TA = -40°C to +85°C (I80C88, I80C88-2)

CC =

= 5.0V ±10%; TA = -55° to +125°C (M80C88)

TEST

CONDITIONS

35 - 35 - ns

82C84A

CL = 100pF TCHCL-10 - TCHCL-10 - ns

CL = 100pF TCLCL-30 - TCLCL-30 - ns

0-0-ns

30 - 15 - ns

80C88 80C88-2

UNITSMIN MAX MIN MAX

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80C88

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AC Electrical Specifications V

SYMBOL PARAMETER

(33) TCLRL RD Active Delay CL = 100pF 10 165 10 100 ns (34) TCLRH RD (35) TRHAV RD Inactive to Next Address

(36) TCLHAV HLDA Valid Delay CL = 100pF 10 160 10 100 ns (37) TRLRH RD (38) TWLWH WR (39) TAVAL Address Valid to ALE Low CL = 100pF TCLCH-60 - TCLCH-40 - ns (40) TOLOH Output Rise Time From 0.8V to 2.0V - 15 - 15 ns (41) TOHOL Output Fall Time From 2.0V to 0.8V - 15 - 15 ns

NOTES:

6. Signal at 82C84A shown for reference only.

7. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.

8. Applies only to T2 state (8ns into T3).

Inactive Delay CL = 100pF 10 150 10 80 ns

Active

Width CL = 100pF 2TCLCL-75 - 2TCLCL-50 - ns

Width CL = 100pF 2TCLCL-60 - 2TCLCL-40 - ns

= 5.0V ±10%; TA = 0°C to +70°C (C80C88, C80C88-2)

5.0V ±10%; TA = -40°C to +85°C (I80C88, I80C88-2)

CC =

= 5.0V ±10%; TA = -55° to +125°C (M80C88) (Continued)

TEST

CONDITIONS

CL = 100pF TCLCL-45 - TCLCL-40 - ns

80C88 80C88-2

UNITSMIN MAX MIN MAX

FN2949.4

February 22, 2008

Page 19

Waveforms

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80C88

CLK (82C84A OUTPUT)

(30) TCHCTV

IO/M, SSO

A15-A8 A15-A8 (FLOAT DURING INTA)

A19/S6-A16/S3

RDY (82C84A INPUT)

SEE NOTE 9, 10

READY (80C88 INPUT)

(23) TCLLH

ALE

(17)

TCLAV

T1 T2 T3

(1)

TCLCL

(26) TCLDV (18) TCLAX

TLHLL

(22)

TCHLL

TAVAL

(39)

(3)

A19-A16

(24)

TCH1CH2

(4)

TCHCL

TLLAX

(25)

TRYLCL

(12)

(5)

TCL2CL1

S6-S3

TR1VCL (8)

(2)

TCLCH

TCLR1X (9)

(11)

TCHRYX

TCHCTV

(30)

TCLAV

(17)

(10)

TRYHCH

TDVCL

TRLRH

(37)

TCVCTX

(34) TCLRH

READ CYCLE

, INTA = VOH)

(WR

AD7-AD0

DT/R

DEN

(30)

TCHCTV

AD7-AD0

(32) TAZRL

TCLRL

(33)

(29) TCVCTV

(19)

TCLAZ

FIGURE 9. BUS TIMING - MINIMUM MODE SYSTEM

NOTES:

9. RDY is sampled near the end of T2, T3, TW to determine if TW machine states are to be inserted.

10. Signals at 82C84A are shown for reference only.

(16)

DATA IN

(31)

(7)

TCLDX1

TRHAV

TCHCTV

(35)

(30)

FN2949.4

February 22, 2008

Page 20

Waveforms (Continued)

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80C88

CLK (82C84A OUTPUT)

WRITE CYCLE

INTA CYCLE

(NOTE 11)

, WR = V

AD7-AD0

DEN

AD7-AD0

DT/R

INTA

DEN

(17)

TCLAV

(19)

TCLAZ

TCVCTV

(29) TCVCTV

TCHCTV

(30)

(29) TCVCTV

(4)

TCH1CH2

(26)

TCLDV TCLAX

AD7-AD0

(29)

(29) TCVCTV

(18)

TCL2CL1

DATA OUT

(38)

TWLWH

TCVCTX

(5)

(31) TCVCTX

TCVCTX

TDVCL

POINTER

(31)

(6)

T4T3T2T1

(27)

TCLDX2

TWHDX

TCLDX1 (7)

TCHCTV (30)

(28)

SOFTWARE

, INTA = V

DEN

HALT -

, RD,

AD7-AD0

ALE

IO/M

DT/R

SSO

TCLAV

(17)

FIGURE 10. BUS TIMING - MINIMUM MODE SYSTEM (Continued)

NOTES:

1. Two INT A second INTA

cycles run back-to-back. The 80C88 local ADDR/DATA bus is floating during both INTA cycles. Control signals are shown for the

cycle.

2. Signals at 82C84A are shown for reference only.

TCHCTV

(30)

INVALID ADDRESS

TCLLH

(23)

SOFTWARE HALT

TCHLL

(24)

TCVCTX

(31)

FN2949.4

February 22, 2008

Page 21

80C88

www.BDTIC.com/Intersil

AC Electrical Specifications V

MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER)

SYMBOL PARAMETER TEST CONDITIONS

TIMING REQUIREMENTS

(1) TCLCL CLK Cycle Period 200 - 125 - ns (2) TCLCH CLK Low Time 118 - 68 - ns (3) TCHCL CLK High Time 69 - 44 - ns (4) TCH1CH2 CLK Rise Time From 1.0V to 3.5V - 10 - 10 ns (5) TCL2CL1 CLK Fall Time From 3.5V to 1.0V - 10 - 10 ns (6) TDVCL Data in Setup Time 30 - 20 - ns (7) TCLDX1 Data In Hold Time 10 - 10 - ns (8) TR1VCL RDY Setup Time into 82C84

(Notes 13,14)

(9) TCLR1X RDY Hold Time into 82C84

(Notes 13,14)

(10) TRYHCH READY Setup Time into 80C88 118 - 68 - ns (11) TCHRYX READY Hold Time into 80C88 30 - 20 - ns (12) TRYLCL READY Inactive to CLK (Note15) -8 - -8 - ns (13) TlNVCH Setup Time for Recognition

(lNTR, NMl, TEST

(14) TGVCH RQ/GT Setup Time 30 - 15 - ns (15) TCHGX RQ

(16) TILlH Input Rise Time (Except CLK) From (17) TIHIL Input Fall Time

TIMING RESPONSES

(18) TCLML Command Active Delay (Note13) (19) TCLMH Command Inactive (Note 13) 535535ns (20) TRYHSH READY Active to Status Passive

(21) TCHSV Status Active Delay 10 110 10 60 ns (22) TCLSH Status Inactive Delay (Note 17) 10 130 10 70 ns (23) TCLAV Address Valid Delay 10 110 10 60 ns (24) TCLAX Address Hold Time 10 - 10 - ns (25) TCLAZ Address Float Delay TCLAX 80 TCLAX 50 ns (26) TCHSZ Status Float Delay - 80 - 50 ns (27) TSVLH Status Valid to ALE High (Note 13)-20-20ns (28) TSVMCH Status Valid to MCE High (Note 13)-30-30ns (29) TCLLH CLK Low to ALE Valid (Note 13)-20-20ns (30) TCLMCH CLK Low to MCE High (Note 13)-25-25ns (31) TCHLL ALE Inactive Delay (Note 13) 418418ns

Hold Time into 80C88 (Note 16) 40 TCHCL +

(Notes 15, 17)

= 5.0V±10%; TA = 0°C to +70°C (C80C88, C80C88-2)

= 5.0V±10%; TA = -40°C to +85°C (I80C88, I80C88-2)

= 5.0V±10%; TA = -55°C to +125°C (M80C88)

80C88 80C88-2

UNITSMIN MAX MIN MAX

35 - 35 - ns

0-0-ns

30 - 15 - ns

) (Note 14)

30 TCHCL + 10ns

0.8V to 2.0V -15-15ns

(Except CLK) From 2.0V to 0.8V -15-15ns

535535ns

-110- 65ns

CL = 100pF for all 80C88 outputs in addition to internal loads.

FN2949.4

February 22, 2008

Page 22

80C88

www.BDTIC.com/Intersil

AC Electrical Specifications V

MAX MODE SYSTEM (USING 82C88 BUS CONTROLLER) (Continued)

SYMBOL PARAMETER TEST CONDITIONS

(32) TCLMCL MCE Inactive Delay (Note 13) (33) TCLDV Data Valid Delay 10 110 10 60 ns (34) TCLDX2 Data Hold Time 10 - 10 - ns (35) TCVNV Control Active Delay (Note 13) 545545ns (36) TCVNX (37) TAZRL Address Float to Read Active 0-0-ns (38) TCLRL RD (39) TCLRH RD (40) TRHAV RD

(41) TCHDTL Direction Control Active Delay

(42) TCHDTH Direction Control Inactive Delay

(43) TCLGL GT (44) TCLGH GT (45) TRLRH RD Width 2TCLCL

(46) TOLOH Output Rise Time From 0.8V to 2.0V -15-15ns (47) TOHOL Output Fall Time From 2.0V to 0.8V -15-15ns

NOTES:

3. Signal at 82C84A or 82C88 shown for reference only.

4. Setup requirement for asynchronous signal only to guarantee recognition at next CLK.

5. Applies only to T2 state (8ns into T3).

6. The 80C88 actively pulls the RQ

7. Status lines return to their inactive (logic one) state after CLK goes low and READY goes high.

Control Inactive Delay (Note 13)

Active Delay 10 165 10 100 ns Inactive Delay 10 150 10 80 ns Inactive to Next Address Active TCLCL

(Note 13)

(Note 1)

Active Delay 085050ns Inactive Delay 085050ns

= 5.0V±10%; TA = 0°C to +70°C (C80C88, C80C88-2)

= 5.0V±10%; TA = -40°C to +85°C (I80C88, I80C88-2)

= 5.0V±10%; TA = -55°C to +125°C (M80C88)

CL = 100pF for all 80C88 outputs in addition to internal loads.

/GT pin to a logic one on the following clock low time.

80C88 80C88-2

UNITSMIN MAX MIN MAX

-15-15ns

10 45 10 45 ns

- 45

-50-50ns

-30-30ns

- 75

- TCLCL

- 40

- 2TCLCL

- 50

-ns

FN2949.4

February 22, 2008

Page 23

Waveforms

www.BDTIC.com/Intersil

80C88

NOTES 18, 19

QS0, QS1

, S1, S0 (EXCEPT HALT)

A19/S6-A16/S3

ALE (82C88 OUTPUT)

RDY (82C84 INPUT)

CLK

(21) TCHSV

(23) TCLAV

TSVLH

(27)

(23)

TCLAV

TCLLH

(29)

T1 T2 T3 T4

(1)

TCLCL

TCLDV

TCLAX

A19-A16

(31)

TCHLL

(12) TRYLCL

(4)

TCH1CH2

TCHCL (3)

(33) (24)

TR1VCL

TCLR1X

(5)

TCL2CL1 TW

TCLSH

(22)

(SEE NOTE 20)

A15-A8A15-A8

S6-S3

(8)

(9)

TCLCH

(2)

TCLAV

(23)

READ CYCLE

82C88

OUTPUTS

SEE NOTES 19, 21

READY 80C86 INPUT)

AD7-AD0

DT/R

MRDC

OR IORC

DEN

TCLAV

(41) TCHDTL

(23)

(24)

TCLAX

(25)

TCLAZ

AD7-AD0

(37) TAZRL

TCLML

(35) TCVNV

TCLRL

(38)

(18)

TRYHSH

(20)

TRYHCH

(10)

TDVCL

(39) TCLRH TRHAV

TRLRH

(45)

TCLMH

TCVNX

FIGURE 11. BUS TIMING - MAXIMUM MODE (USING 82C88)

NOTES:

8. RDY is sampled near the end of T2, T3, TW to determine if TW machine states are to be inserted.

9. Signals at 82C84A or 82C88 are shown for reference only .

10. Status inactive in state just prior to T4.

11. The issuance of the 82C88 command and control signals (MRDC

, MWTC, AMWC, IORC, IOWC, AIOWC, INTA, and DEN) lags the active high

82C88 CEN.

(6)

DATA IN

(11)

TCHRYX

(7)

TCLDX1

(40)

(42)

TCHDTH

(19)

(36)

FN2949.4

February 22, 2008

Page 24

Waveforms (Continued)

www.BDTIC.com/Intersil

80C88

82C88

OUTPUTS

SEE NOTES 22, 23

82C88 OUTPUTS

SEE NOTES 22, 23, 25

CLK

TCHSV (21)

, S1, S0 (EXCEPT HALT)

WRITE CYCLE

AD7-AD0

DEN

AMWC OR AIOWC

MWTC OR IOWC

INTA

CYCLE

(SEE NOTES 25, 26)

A15-A8

(25) TCLAZ

AD7-AD0

(28) TSVMCH

MCE/PDEN

(30) TCLMCH

DT/R

INTA

TCLAV

T1 T2 T3 T4

(6)

(22)

DATA

TCLMH

(19)

TDVCL

POINTER

TCLDV

(23)

TCLAX

TCVNV

(35)

(18) TCLML

RESERVED FOR CASCADE ADDR

TCLMCL

(18) TCLML

(41)

TCHDTL

(33) (24)

(18)TCLML

(32)

TCLSH

(SEE NOTE 24)

TCLDX2

TCLMH (19)

TCLDX1 (7)

(42)

(34)

TCVNX (36)

TCHDTH

DEN

SOFTWARE HALT - RD

, MRDC, IORC, MWTC, AMWC, IOWC, AIOWC, INTA, S0, S1 = VOH

AD7-AD0

A15-A8

TCLAV

(23)

, S1, S0

TCHSV

(21)

FIGURE 12. BUS TIMING - MAXIMUM MODE SYSTEM (USING 82C88) (Continued)

NOTES:

12. Signals at 82C84A or 82C86 are shown for reference only.

13. The issuance of the 82C88 command and control signals (MRDC 82C88 CEN.

14. Status inactive in state just prior to T4.

15. Cascade address is valid between first and second INTA

16. Two INT A for second INTA

cycles run back-to-back. The 80C88 local ADDR/DATA bus is floating during both INTA cycles. Control for pointer address is shown

cycle.

cycles.

TCVNV

(35)

INVALID ADDRESS

TCLSH

(22)

(19) TCLMH

TCVNX

(36)

, MWTC, AMWC, IORC, IOWC, AIOWC, INTA and DEN) lags the active high

FN2949.4

February 22, 2008

Page 25

Waveforms (Continued)

www.BDTIC.com/Intersil

80C88

> 0-CLK CYCLES

TGVCH (14)

TCHGX (15)

PULSE 1 COPROCESSOR

TCLGL

(43)

PULSE 2

80C88 GT

TCLGH (44)

TCLAZ (25)

CLK

TCLGH

/GT

AD7-AD0

, LOCK

A19/S6-A16/S3

, S1, S0

(44)

(1)

TCLCL

PREVIOUS GRANT

80C88

ANY CLK

CYCLE

FIGURE 13. REQUEST/GRANT SEQUENCE TIMING (MAXIMUM MODE ONLY)

NOTE: The coprocessor may not drive the busses outside the region shown without risking contention.

AD7-AD0

A19/S6-A16/S3

, WR, I/O/M, DT/R, DEN, SSO

CLK

HOLD

HLDA

A15-A8

80C88

≥ 1CL

CYCLE

THVCH (13)

TCLHAV (36)

TCLAZ (19)

TCHSZ (20)

1 OR 2

CYCLES

THVCH (13)

(SEE NOTE)

COPROCESSOR

TCHSV (21)

(SEE NOTE)TCHSZ (26)

TCLHAV (36)

80C88

TCHSV (21)

PULSE 3 COPROCESSOR RELEASE

NOTE: Setup requirements for asynchronous signals only to guarantee recognition at next CLK.

FIGURE 14. HOLD/HOLD ACKNOWLEDGE TIMING (MINIMUM MODE ONLY)

CLK

(13)

NMI

INTR

TEST

SIGNAL

TINVCH (SEE NOTE)

FIGURE 15. ASYNCHRONOUS SIGNAL RECOGNITION

NOTE: Setup requirements for asynchronous signals only to

CLK

LOCK

FIGURE 16. BUS LOCK SIGNAL TIMING (MAXIMUM MODE

ANY CLK CYCLE

ONLY)

guarantee recognition at next CLK.

TCLAV

(23)

ANY CLK CYCLE

TCLAV

(23)

February 22, 2008

FN2949.4

Page 26

80C88

www.BDTIC.com/Intersil

Waveforms (Continued)

≥ 50µS

CLK

(7) TCLDX1

(6) TDVCL

RESET

≥ 4 CLK CYCLE

FIGURE 17. RESET TIMING

AC Test Circuit AC Testing Input, Output Waveform

OUTPUT FROM

DEVICE UNDER TEST

NOTE: Includes stay and jig capacitance.

CL (NOTE)

TEST POINT

INPUT

+ 20% V

VIL - 50% V

17. All input signals (other than CLK) must switch between V

1.5V 1.5V

and V

-0.4V. Input rise and fall times are driven at 1ns/V.

+20% VIH. CLK must switch between 0.4V and

IHMIN

OUTPUT

ILMAX

-50%

Burn-In Circuits

GND

VCL

GND

VCL

GND

VCL

OPEN

GND

RIO

MD80C88 (CERDIP)

GND

A14

A13

A12

A11

A10

AD7

AD6

AD5

AD4

AD3

AD2

AD1

AD0

NMI

INTR

CLK

GND

A15

A16

A17

A18

A19

BHE

RQ0

RQ1

LOCK

QS0

QS2

TEST

READY

RESET

GND

RIO

VCL

VCC/2

GND

VIL

VCL

VCC/2

GND

VCL

NODE FROM PROGRAM CARD

FN2949.4

February 22, 2008

Page 27

Burn-In Circuits (Continued)

www.BDTIC.com/Intersil

80C88

NOTES:

1. V

= 5.5V ±0.5V, GND = 0V.

2. Input voltage limits (except clock): (Maximum) = 0.4V

(Minimum) = 2.6V, VIH (Clock) = VCC - 0.4V) minimum.

3. VCC/2 is external supply set to 2.7V ±10%.

is generated on program card (VCC - 0.65V).

4. V

5. Pins 13 - 16 input sequenced instructions from internal hold

devices, (DIP Only).

6. F0 = 100kHz ±10%.

7. Node = a 40μs pulse every 2.56ms.

COMPONENTS:

1. RI = 10kΩ ±5%, 1/4W

2. RO = 1.2kΩ ±5%, 1/4W

3. RIO = 2.7kΩ ±5%, 1/4W

4. RC = 1kΩ ±5%, 1/4W

5. C = 0.01μF (Minimum)

FN2949.4

February 22, 2008

Page 28

Die Characteristics

www.BDTIC.com/Intersil

METALLIZATION:

Type: Silicon - Aluminum Thickness: 11K

Å ±2kÅ

GLASSIVATION:

Type: SiO

Thickness: 8kÅ ±1kÅ

WORST CASE CURRENT DENSITY:

1.5 x 10

A/cm

Metallization Mask Layout

80C88

A10

AD7

AD6

AD5

AD4

AD3

AD2

A11 A12 A13 A14 A17/S4 A18/S5GND A16/S3V

A15

A19/S6

SSO

MN/MX

HOLD

HLDA

IO/M

AD1

AD0

NMI INTR CLK GND RESET READY TEST

INTA

ALE DEN

DT/R

FN2949.4

February 22, 2008

Page 29

Instruction Set Summary

www.BDTIC.com/Intersil

80C88

MNEMONIC AND

DESCRIPTION

DATA TRANSFER MOV = MOVE:

Immediate to Register/Memory

Immediate to Register 1 0 1 1 w reg data data if w 1

Memory to Accumulator 1 0 1 0 0 0 0 w addr-low addr-high

Accumulator to Memory 1 0 1 0 0 0 1 w addr-low addr-high

Segment Register to Register/Memory

PUSH = Push:

Segment Register 0 0 0 reg 1 1 0

POP = Pop:

Segment Register 0 0 0 reg 1 1 1

XCHG = Exchange:

IN = Input from:

Fixed Port 1 1 1 0 0 1 0 w port

Variable Port 1 1 1 0 1 1 0 w

OUT = Output to:

Fixed Port 1 1 1 0 0 1 1 w port

Variable Port 1 1 1 0 1 1 1 w

XLAT = Translate Byte to AL

LEA = Load EA to Register2

LDS = Load Pointer to DS 1 1 0 0 0 1 0 1 mod reg r/m

LES = Load Pointer to ES 1 1 0 0 0 1 0 0 mod reg r/m

LAHF = Load AH with

Flags

SAHF = Store AH into Flags

PUSHF = Push Flags 1 0 0 1 1 1 0 0

POPF = Pop Flags 1 0 0 1 1 1 0 1

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

1 0 0 0 1 0 d w mod reg r/m

1 1 0 0 0 1 1 w mod 0 0 0 r/m data data if w 1

1 0 0 0 1 1 1 0 mod 0 reg r/m

1 0 0 0 1 1 0 0 mod 0 reg r/m

1 0 0 0 0 1 1 w mod reg r/m

1 0 0 1 0 reg

1 1 0 1 0 1 1 1

1 0 0 0 1 1 0 1 mod reg r/m

1 0 0 1 1 1 1 1

1 0 0 1 1 1 1 0

INSTRUCTION CODE

FN2949.4

February 22, 2008

Page 30

Instruction Set Summary (Continued)

www.BDTIC.com/Intersil

80C88

MNEMONIC AND

DESCRIPTION

ARITHMETIC ADD = Add:

Immediate to Register/Memory

Immediate to Accumulator

ADC = Add with Carry:

Immediate to Register/Memory

Immediate to Accumulator

INC = Increment:

AAA = ASCll Adjust for Add

DAA = Decimal Adjust for Add

SUB = Subtract:

Immediate from Register/Memory

Immediate from Accumulator

SBB = Subtract with Borrow

Immediate from Register/Memory

Immediate from Accumulator

DEC = Decrement:

NEG = Change Sign 1 1 1 1 0 1 1 w mod 0 1 1 r/m

CMP = Compare:

Immediate with Register/Memory

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

0 0 0 0 0 0 d w mod reg r/m

1 0 0 0 0 0 s w mod 0 0 0 r/m data data if s:w = 01

0 0 0 0 0 1 0 w data data if w = 1

0 0 0 1 0 0 d w mod reg r/m

1 0 0 0 0 0 s w mod 0 1 0 r/m data data if s:w = 01

0 0 0 1 0 1 0 w data data if w = 1

0 0 1 1 0 1 1 1

0 0 1 0 0 1 1 1

0 0 1 0 1 0 d w mod reg r/m

1 0 0 0 0 0 s w mod 1 0 1 r/m data data if s:w = 01

0 0 1 0 1 1 0 w data data if w = 1

0 0 0 1 1 0 d w mod reg r/m

1 0 0 0 0 0 s w mod 0 1 1 r/m data data if s:w = 01

0 0 0 1 1 1 0 w data data if w = 1

0 0 1 1 1 0 d w mod reg r/m

1 0 0 0 0 0 s w mod 1 1 1 r/m data data if s:w = 01

INSTRUCTION CODE

FN2949.4

February 22, 2008

Page 31

Instruction Set Summary (Continued)

www.BDTIC.com/Intersil

80C88

MNEMONIC AND

DESCRIPTION

Immediate with Accumulator

AAS = ASCll Adjust for Subtract

DAS = Decimal Adjust for Subtract

MUL = Multiply (Unsigned)

IMUL = Integer Multiply (Signed)

AAM = ASCll Adjust for Multiply

DlV = Divide (Unsigned) 1 1 1 1 0 1 1 w mod 1 1 0 r/m

IDlV = Integer Divide

(Signed)

AAD = ASClI Adjust for Divide

CBW = Convert Byte to Word

CWD = Convert Word to Double Word

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

0 0 1 1 1 1 0 w data data if w = 1

0 0 1 1 1 1 1 1

0 0 1 0 1 1 1 1

1 1 1 1 0 1 1 w mod 1 0 0 r/m

1 1 1 1 0 1 1 w mod 1 0 1 r/m

1 1 0 1 0 1 0 0 0 0 0 0 1 0 1 0

1 1 1 1 0 1 1 w mod 1 1 1 r/m

1 1 0 1 0 1 0 1 0 0 0 0 1 0 1 0

1 0 0 1 1 0 0 0

1 0 0 1 1 0 0 1

INSTRUCTION CODE

LOGIC

NOT = Invert 1 1 1 1 0 1 1 w mod 0 1 0 r/m

SHL/SAL = Shift Logi-

cal/Arithmetic Left

SHR = Shift Logical Right 1 1 0 1 0 0 v w mod 1 0 1 r/m SAR = Shift Arithmetic

Right

ROL = Rotate Left 1 1 0 1 0 0 v w mod 0 0 0 r/m

ROR = Rotate Right 1 1 0 1 0 0 v w mod 0 0 1 r/m

RCL = Rotate Through

Carry Flag Left

RCR = Rotate Through Carry Right

AND = And:

Reg./Memory and Register to Either

Immediate to Register/Memory

Immediate to Accumulator

TEST = And Function to Flags, No Result:

Immediate Data and Register/Memory

1 1 0 1 0 0 v w mod 1 0 0 r/m

1 1 0 1 0 0 v w mod 1 1 1 r/m

1 1 0 1 0 0 v w mod 0 1 0 r/m

1 1 0 1 0 0 v w mod 0 1 1 r/m

0 0 1 0 0 0 0 d w mod reg r/m

1 0 0 0 0 0 0 w mod 1 0 0 r/m data data if w = 1

0 0 1 0 0 1 0 w data data if w = 1

1 0 0 0 0 1 0 w mod reg r/m

1 1 1 1 0 1 1 w mod 0 0 0 r/m data data if w = 1

FN2949.4

February 22, 2008

Page 32

Instruction Set Summary (Continued)

www.BDTIC.com/Intersil

80C88

MNEMONIC AND

DESCRIPTION

Immediate Data and Accumulator

OR = Or:

Immediate to Register/Memory

Immediate to Accumulator

XOR = Exclusive or:

Immediate to Register/Memory

Immediate to Accumulator

STRING MANIPULATION

REP = Repeat 1 1 1 1 0 0 1 z

MOVS = Move Byte/Word 1 0 1 0 0 1 0 w

CMPS = Compare

Byte/Word

SCAS = Scan Byte/Word 1 0 1 0 1 1 1 w

LODS = Load Byte/Word

to AL/AX

STOS = Stor Byte/Word from AL/A

CONTROL TRANSFER

CALL = Call:

Direct Within Segment 1 1 1 0 1 0 0 0 disp-low disp-high

Indirect Within Segment 1 1 1 1 1 1 1 1 mod 0 1 0 r/m

Direct Intersegment 1 0 0 1 1 0 1 0 offset-low offset-high

Indirect Intersegment 1 1 1 1 1 1 1 1 mod 0 1 1 r/m

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

1 0 1 0 1 0 0 w data data if w = 1

0 0 0 0 1 0 d w mod reg r/m

1 0 0 0 0 0 0 w mod 1 0 1 r/m data data if w = 1

0 0 0 0 1 1 0 w data data if w = 1

0 0 1 1 0 0 d w mod reg r/m

1 0 0 0 0 0 0 w mod 1 1 0 r/m data data if w = 1

0 0 1 1 0 1 0 w data data if w = 1

1 0 1 0 0 1 1 w

1 0 1 0 1 1 0 w

1 0 1 0 1 0 1 w

INSTRUCTION CODE

seg-low seg-high

FN2949.4

February 22, 2008

Page 33

Instruction Set Summary (Continued)

www.BDTIC.com/Intersil

80C88

MNEMONIC AND

DESCRIPTION

JMP = Unconditional Jump:

Direct Within Segment 1 1 1 0 1 0 0 1 disp-low disp-high

Direct Within SegmentShort

Indirect Within Segment 1 1 1 1 1 1 1 1 mod 1 0 0 r/m

Direct Intersegment 1 1 1 0 1 0 1 0 offset-low offset-high

Indirect Intersegment 1 1 1 1 1 1 1 1 mod 1 0 1 r/m

RET = Return from CALL:

Within Segment 1 1 0 0 0 0 1 1

Within Seg Adding lmmed to SP

Intersegment 1 1 0 0 1 0 1 1

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

1 1 1 0 1 0 1 1 disp

1 1 0 0 0 0 1 0 data-low data-high

INSTRUCTION CODE

seg-low seg-high

FN2949.4

February 22, 2008

Page 34

Instruction Set Summary (Continued)

www.BDTIC.com/Intersil

80C88

MNEMONIC AND

DESCRIPTION

Intersegment Adding Immediate to SP

JE/JZ = Jump on Equal/Zero

JL/JNGE = Jump on Less/Not Greater or Equal

JLE/JNG = Jump on Less or Equal/ Not Greater

JB/JNAE = Jump on Below/Not Above or Equal

JBE/JNA = Jump on Below or Equal/Not Above

JP/JPE = Jump on Parity/Parity Even

JO = Jump on Overflow 0 1 1 1 0 0 0 0 disp

JS = Jump on Sign 0 1 1 1 1 0 0 0 disp

JNE/JNZ = Jump on Not

Equal/Not Zero

JNL/JGE = Jump on Not Less/Greater or Equal

JNLE/JG = Jump on Not Less or Equal/Greater

JNB/JAE = Jump on Not Below/Above

JNBE/JA = Jump on Not Below or Equal/Above

JNP/JPO = Jump on Not Par/Par Odd

JNO = Jump on Not Overflow

JNS = Jump on Not Sign 0 1 1 1 1 0 0 1 disp

LOOP = Loop CX Times 1 1 1 0 0 0 1 0 disp

LOOPZ/LOOPE = Loop

While Zero/Equal

LOOPNZ/LOOPNE = Loop While Not Zero/Equal

JCXZ = Jump on CX Zero 1 1 1 0 0 0 1 1 disp

INT = Interrupt

Type Specified 1 1 0 0 1 1 0 1 type

Type 3 1 1 0 0 1 1 0 0

INTO = Interrupt on Overflow

IRET = Interrupt Return 1 1 0 0 1 1 1 1

or Equal

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

1 1 0 0 1 0 1 0 data-low data-high

0 1 1 1 0 1 0 0 disp

0 1 1 1 1 1 0 0 disp

0 1 1 1 1 1 1 0 disp

0 1 1 1 0 0 1 0 disp

0 1 1 1 0 1 1 0 disp

0 1 1 1 1 0 1 0 disp

0 1 1 1 0 1 0 1 disp

0 1 1 1 1 1 0 1 disp

0 1 1 1 1 1 1 1 disp

0 1 1 1 0 0 1 1 disp

0 1 1 1 0 1 1 1 disp

0 1 1 1 1 0 1 1 disp

0 1 1 1 0 0 0 1 disp

1 1 1 0 0 0 0 1 disp

1 1 1 0 0 0 0 0 disp

1 1 0 0 1 1 1 0

INSTRUCTION CODE

PROCESSOR CONTROL

FN2949.4

February 22, 2008

Page 35

Instruction Set Summary (Continued)

www.BDTIC.com/Intersil

80C88

MNEMONIC AND

DESCRIPTION

CLC = Clear Carry 1 1 1 1 1 0 0 0

CMC = Complement Car-

STC = Set Carry 1 1 1 1 1 0 0 1

CLD = Clear Direction 1 1 1 1 1 1 0 0

STD = Set Direction 1 1 1 1 1 1 0 1

CLl = Clear Interrupt 1 1 1 1 1 0 1 0

ST = Set Interrupt 1 1 1 1 1 0 1 1

HLT = Halt 1 1 1 1 0 1 0 0

WAIT = Wait 1 0 0 1 1 0 1 1

ESC = Escape (to Exter-

nal Device)

LOCK = Bus Lock Prefix 1 1 1 1 0 0 0 0

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

1 1 1 1 0 1 0 1

1 1 0 1 1 x x x mod x x x r/m

INSTRUCTION CODE

FN2949.4

February 22, 2008

Page 36

Instruction Set Summary (Continued)

www.BDTIC.com/Intersil

80C88

MNEMONIC AND

DESCRIPTION

NOTES: AL = 8-bit accumulator AX = 16-bit accumulator CX = Count register DS= Data segment ES = Extra segment Above/below refers to unsigned value. Greater = more positive; Less = less positive (more negative) signed values if d = 1 then “to” reg; if d = 0 then “from” reg if w = 1 then word instruction; if w = 0 then byte

instruction if mod = 11 then r/m is treated as a REG field if mod = 00 then DISP = 0†, disp-low and disp-high

are absent if mod = 01 then DISP = disp-low sign-extended

16-bits, disp-high is absent if mod = 10 then DISP = disp-high:disp-low if r/m = 000 then EA = (BX) + (SI) + DISP if r/m = 001 then EA = (BX) + (DI) + DISP if r/m = 010 then EA = (BP) + (SI) + DISP if r/m = 011 then EA = (BP) + (DI) + DISP if r/m = 100 then EA = (SI) + DISP if r/m = 101 then EA = (DI) + DISP if r/m = 110 then EA = (BP) + DISP † if r/m = 111 then EA = (BX) + DISP DISP follows 2nd byte of instruction (before data

if required) † except if mod = 00 and r/m = 110 then

EA = disp-high: disp-

low. †† MOV CS, REG/MEMORY not allowed.

INSTRUCTION CODE

7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

if s:w = 01 then 16-bits of immediate data form the operand. if s:w = 11 then an immediate data byte is sign extended

to form the 16-bit operand. if v = 0 then “count” = 1; if v = 1 then “count” in (C x = don't care z is used for string primitives for comparison with ZF FLAG.

)

SEGMENT OVERRIDE PREFIX

001 reg 11 0

REG is assigned according to the following table:

16-BIT (w = 1) 8-BIT (w = 0) SEGMENT

000 AX 000 AL 00 ES

001 CX 001 CL 01 CS

010 DX 010 DL 10 SS

011 BX 011 BL 11 DS

100 SP 100 AH

101 BP 101 CH

110 SI 110 DH

111 DI 111 BH

Instructions which reference the flag register file as a 16-bit object use the symbol FLAGS to represent the file:

FLAGS =

X:X:X:X:(OF):(DF):(IF):(TF):(SF):(ZF):X:(AF):X:(PF):X:(CF)

FN2949.4

February 22, 2008

Page 37

Dual-In-Line Plastic Packages (PDIP)

www.BDTIC.com/Intersil

80C88

-C-

-B-

INDEX

AREA

BASE

PLANE

SEATING

PLANE

12 3 N/2

-AD

0.010 (0.25) C AM BS

NOTES:

1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control.

2. Dimensioning and tolerancing per ANSI Y14.5M-1982.

3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of Publication No. 95.

4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3.

5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).

6. E and are measured with the leads constrained to be per-

7. e

pendicular to datum .

and eC are measured at the lead tips with the leads uncon-

strained. e

must be zero or greater.

-C-

8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm).

9. N is the maximum number of terminal positions.

10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).

E40.6 (JEDEC MS-011-AC ISSUE B)

40 LEAD DUAL-IN-LINE PLASTIC PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.250 - 6.35 4

A1 0.015 - 0.39 - 4

A2 0.125 0.195 3.18 4.95 -

B 0.014 0.022 0.356 0.558 -

B1 0.030 0.070 0.77 1.77 8

C 0.008 0.015 0.204 0.381 -

D 1.980 2.095 50.3 53.2 5

D1 0.005 - 0.13 - 5

E 0.600 0.625 15.24 15.87 6

E1 0.485 0.580 12.32 14.73 5

e 0.100 BSC 2.54 BSC -

0.600 BSC 15.24 BSC 6

- 0.700 - 17.78 7

L 0.115 0.200 2.93 5.08 4

N40 409

NOTESMIN MAX MIN MAX

Rev. 0 12/93

FN2949.4

February 22, 2008

Page 38

80C88

www.BDTIC.com/Intersil

Ceramic Dual-In-Line Frit Seal Packages (CERDIP)

LEAD FINISH

-A-

-B-

bbb C A - B

BASE

PLANE

SEATING

PLANE

ccc C A - BMD

NOTES:

1. Index area: A notch or a pin one identification mark shall be located adjacent to pin one and shall be located within the shaded area shown. The manufacturer’s identification shall not be used as a pin one identification mark.

2. The maximum limits of lead dimensions b and c or M shall be measured at the centroid of the finished lead surfaces, when solder dip or tin plate lead finish is applied.

3. Dimensions b1 and c1 apply to lead base metal only. Dimension M applies to lead plating and finish thickness.

4. Corner leads (1, N, N/2, and N/2+1) may be configured with a partial lead paddle. For this configuration dimension b3 replaces dimension b2.

5. This dimension allows for off-center lid, meniscus, and glass overrun.

6. Dimension Q shall be measured from the seating plane to the base plane.

7. Measure dimension S1 at all four corners.

8. N is the maximum number of terminal positions.

9. Dimensioning and tolerancing per ANSI Y14.5M - 1982.

10. Controlling dimension: INCH.

-D-

BASE

-C-

METAL

(b)

SECTION A-A

(c)

eA/2

aaa CA - B

F40.6 MIL-STD-1835 GDIP1-T40 (D-5, CONFIGURATION A)

40 LEAD CERAMIC DUAL-IN-LINE FRIT SEAL PACKAGE

INCHES MILLIMETERS

SYMBOL

A - 0.225 - 5.72 -

b 0.014 0.026 0.36 0.66 2

b1 0.014 0.023 0.36 0.58 3

b2 0.045 0.065 1.14 1.65 -

b3 0.023 0.045 0.58 1.14 4

c 0.008 0.018 0.20 0.46 2

c1 0.008 0.015 0.20 0.38 3

D - 2.096 - 53.24 5

E 0.510 0.620 12.95 15.75 5

e 0.100 BSC 2.54 BSC -

eA 0.600 BSC 15.24 BSC -

eA/2 0.300 BSC 7.62 BSC -

L 0.125 0.200 3.18 5.08 -

Q 0.015 0.070 0.38 1.78 6

S1 0.005 - 0.13 - 7

105

aaa - 0.015 - 0.38 -

bbb - 0.030 - 0.76 -

ccc - 0.010 - 0.25 -

M - 0.0015 - 0.038 2, 3

N40 408

NOTESMIN MAX MIN MAX

Rev. 0 4/94

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implic atio n or other wise u nde r any p a tent or patent rights of Intersil or it s sub sidi ari es.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN2949.4

February 22, 2008

Datasheet 80C88 Datasheet (intersil)

Specifications and Main Features

Frequently Asked Questions

User Manual