Page 1
March 1997
80C286/883
High Performance Microprocessor with Memory
Management and Protection
Features
• This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
• Compatible with NMOS 80286/883
• Static CMOS Design for Low Power Operation
- ICCSB = 5mA Maximum
- ICCOP = 185mA Maximum (80C286-10/883)
- ICCOP = 220mA Maximum (80C286-12/883)
• Large Address Space
- 16 Megabytes Physical
- 1 Gigabyte Virtual per Task
• Integrated Memory Management, Four-Level Memory
Protection and Support for Virtual Memory and
Operating Systems
• Two 80C86 Upward Compatible Operating Modes
- 80C286/883 Real Address Mode
- Protected Virtual Address Mode
• Compatible with 80287 Numeric Data Co-Processor
Description
The Intersil 80C286/883 is a static CMOS version of the
NMOS 80286 microprocessor. The 80C286/883 is an
advanced, high-performance microprocessor with specially
optimized capabilities for multiple user and multi-tasking systems. The 80C286/883 has built-in memory protection that
supports operating system and task isolation as well as program and data privacy within tasks. The 80C286/883
includes memory management capabilities that map 230
(one gigabyte) of virtual address space per task into 2
bytes (16 megabytes) of physical memory.
The 80C286/883 is upwardly compatible with 80C86 and
80C88 software (the 80C286/883 instruction set is a superset of the 80C86/80C88 instruction set). Using the 80C286/
883 real address mode, the 80C286/883 is object code compatible with existing 80C86 and 80C88 software . In protected
virtual address mode, the 80C286/883 is source code compatible with 80C86 and 80C88 software but may require
upgrading to use virtual address as supported by the
80C286/883’s integrated memory management and protection mechanism. Both modes operate at full 80C286/883
performance and execute a superset of the 80C86 and
80C88 instructions.
The 80C286/883 provides special operations to support the
efficient implementation and execution of operating systems.
For example, one instruction can end execution of one task,
save its state, switch to a new task, load its state, and start
execution of the new task. The segment-not-present exception and restartable instructions.
24
Ordering Information
PACKAGE TEMP. RANGE 10MHz 12.5MHz 16MHz 20MHz 25MHz PKG. NO.
68 Pin PGA 0oC to +70oC - CG80C286-12 CG80C286-16 CG80C286-20 - G68.B
-40oC to +85oC IG80C286-10 IG80C286-12 - - - G68.B
-55oC to +125oC MG80C286-10/883 MG80C286-12/883 - - - G68.B
5962-9067801MXC 5962-9067802MXC - - - G68.B
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
| Copyright © Intersil Corporation 1999
3-128
File Number 2948.1
Page 2
80C286/883
Pinout
68 LEAD PGA, COMPONENT PAD VIEW
As viewed from underside of the component when mounted on the board.
SS
D8
V
D1
D0
35 37
D0
V
A11
A13
A0
A1
A2
CLK
CC
RESET
A3
A4
A5
A6
A7
A8
A9
A10
A12
36
38 40
34
33
32
31
30
29
28
27
26
25
24
23
22
2120
1918
1517
A15
A12
A16
A14
As viewed from the component side of the P.C. board.
D11
D10
D9
D4
D3
D2
39 41
1416
A17
A18
42 44
1113
A19
A20
43 45
10
A21
SS
V
P.C. BOARD VIEW
D12
D5
46 48
A22
A23
D13
D6
47 49
6812
579
PEACK
S0
D15
D14
ERROR
D7
51
50
55
57
59
61
63
65
67
2
4
13
S1
NC
NC
BHE
ERROR
5253
NC
54
INTR
56
NMI
58
PEREQ
60
READY
62
HLDA
64
66
M/
IO
68
NC
NC
BUSY
NC
NC
V
SS
V
CC
HOLD
COD/INTA
LOCK
PIN 1 INDICATOR
NC
BUSY
NC
NC
V
SS
V
CC
HOLD
COD/
INTA
LOCK
PIN 1 INDICATOR
ERROR
NC
INTR
NMI
PEREQ
READY
HLDA
M/
NC
D1
3840
15 17
A15
A16
SS
V
D0
3537
36
33
31
29
27
25
23
21 20
19 18
A12
A14
D0
A1
CLK
RESET
A4
A6
A8
A10
A12
A0
A2
V
A3
A5
A7
A9
A11
A13
CC
34
32
30
28
26
24
22
D15
D14
D13
D12
D11
D10D9D8
ERROR
D7
D6
D5
D4
D3
D2
A21
SS
V
4244
11 13
A19
A20
3941
14 16
A17
A18
4749
51
50
52 53
54
55
56
57
58
59
60
61
62
63
64
65
66
68
67
2
4
13
S1
NC
NC
BHE
IO
4345
4648
10
68 12
579
A22
PEACK
S0
A23
3-129
Page 3
80C286/883
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+8.0V
Input, Output or I/O Voltage Applied. . . . . .GND -1.0V to VCC+1.0V
Storage Temperature Range . . . . . . . . . . . . . . . . . -65oC to +150oC
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +175oC
Lead Temperature (Soldering 10s). . . . . . . . . . . . . . . . . . . . +300oC
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. θJA is measured with the component mounted on an evaluation PC board in free air.
Operating Conditions
Operating Voltage Range . . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC
System Clock (CLK) RISE Time (From 1.0V to 3.6V . . . . 8ns (Max)
System Clock (CLK) FALL Time (from 3.6V to 1.0V) . . . . 8ns (Max)
TABLE 1. 80C286/883 D.C. ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER SYMBOL CONDITIONS
Input LOW Voltage V
Input HIGH Voltage V
CLK Input LOW Voltage V
CLK Input HIGH Voltage V
Output LOW Voltage V
Output HIGH Voltage V
Input Leakage Current I
Input Sustaining Current
LOW
Input Sustaining Current
I
BHL
I
BHH
HIGH
Input Sustaining Current
BUSY and ERROR
on
I
Pins
Output Leakage Current I
Active Power Supply
I
CCOP
Current
Standby Power
I
CCSB
Supply Current
NOTES:
2. I
should be measured after lowering VIN to GND and then raising to 1.0V on the following pins: 36-51, 66, 67.
BHL
3. I
should be measured after raising VIN to VCC and then lowering to 3.0V on the following pins: 4-6, 36-51, 66-68.
BHH
4. I
5. I
should be tested with the clock stopped in phase two of the processor clock cycle. VIN = VCC or GND, VCC = 5.5V, outputs unloaded.
CCSB
measured at 10MHz for the 80C286-10/883 and 12.5MHz for the 80C286-12/883. VIN = 2.4V or 0.4V, VCC = 5.5V, outputsunloaded.
CCOP
6. ISH should be measured after raising VIN to VCC and then lowering to 0V on pins 53 and 54.
VCC = 4.5V 1, 2, 3 -55oC ≤ TA≤ +125oC -0.5 0.8 V
IL
VCC = 5.5V 1, 2, 3 -55oC ≤ TA≤ +125oC 2.0 VCC +0.5 V
IH
VCC = 4.5V 1, 2, 3 -55oC ≤ TA≤ +125oC -0.5 1.0 V
ILC
VCC = 5.5V 1, 2, 3 -55oC ≤ TA≤ +125oC 3.6 VCC +0.5 V
IHC
IOL = 2.0mA, VCC = 4.5V 1, 2, 3 -55oC ≤ TA≤ +125oC - 0.4 V
OL
OHIOH
I
= -2.0mA, VCC = 4.5V 1, 2, 3 -55oC ≤ TA≤ +125oC 3.0 - V
= -100µA, VCC = 4.5V VCC -0.4 - V
I
OH
VIN = GND or VCC,
VCC = 5.5V,
Pins 29, 31, 57, 59, 61,
63-64
VCC = 4.5V and 5.5V,
VIN = 1.0V, Note 1
VCC = 4.5V and 5.5V,
VIN = 3.0V, Note 2
VCC = 4.5V and 5.5V
SH
VIN = GND, Note 5
VO = GND or V
O
CC
VCC = 5.5V,
Pins 1, 7-8, 10-28, 32-34
80C286-10/883, Note 4 1, 2, 3 -55oC ≤ TA≤ +125oC - 185 mA
80C286-12/883, Note 4 - 220 mA
VCC = 5.5V, Note 3 1, 2, 3 -55oC ≤ TA≤ +125oC- 5 mA
Thermal Resistance (Typical) θ
JA
θ
PGA Package . . . . . . . . . . . . . . . . . . . . . 35oC/W 6oC/W
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22,500 Gates
Input RISE and FALL Time (From 0.8V to 2.0V
80C286-10/883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)
80C286-12/883 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8ns (Max)
GROUP A
LIMITS
SUB-
GROUPS TEMPERATURE
UNITS MIN MAX
1, 2, 3 -55oC ≤ TA≤ +125oC -10 10 µA
1, 2, 3 -55oC ≤ TA≤ +125oC 38 200 µA
1, 2, 3 -55oC ≤ TA≤ +125oC -50 -400 µA
1, 2, 3 -55oC ≤ TA≤ +125oC -30 -500 µA
1, 2, 3 -55oC ≤ TA≤ +125oC -10 10 µA
JC
3-130
Page 4
80C286/883
TABLE 2. 80C286/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Datasheet Waveforms, Unless Otherwise Noted. Device
Guaranteed and 100% Tested.
80C286/883
10MHz 12.5MHz
GROUP A
PARAMETER SYMBOL CONDITIONS
SUBGROUPS TEMPERATURE
MIN MAX MIN MAX
UNITS
System Clock
(CLK) Period
System Clock
(CLK) Low Time
System Clock (CLK)
High Time
Asynchronous Inputs
SETUP Time
(Note 1)
Asynchronous Inputs
HOLD Time
(Note 1)
RESET SETUP Time 6 VCC = 4.5V
RESET HOLD Time 7 VCC = 4.5V
Read Data
SETUP Time
Read Data
HOLD Time
READY SETUP Time 10 VCC = 4.5V
1VCC = 4.5V and 5.5V 9, 10, 11 -55oC ≤TA≤ +125oC 50 - 40 - ns
2VCC = 4.5V and 5.5V
at 1.0V
3VCC = 4.5V and 5.5V
at 3.6V
4VCC = 4.5V
and 5.5V
5VCC = 4.5V
and 5.5V
and 5.5V
and 5.5V
8VCC = 4.5V
and 5.5V
9VCC = 4.5V
and 5.5V
and 5.5V
9, 10, 11 -55oC ≤TA≤ +125oC 12 - 11 - ns
9, 10, 11 -55oC ≤TA≤ +125oC 16 - 13 - ns
9, 10, 11 -55oC ≤TA≤ +125oC 20 - 15 - ns
9, 10, 11 -55oC ≤ TA≤ +125oC 20 - 15 - ns
9, 10, 11 -55oC ≤ TA≤ +125oC 19 - 10 - ns
9, 10, 11 -55oC ≤ TA≤ +125oC0 - 0 - ns
9, 10, 11 -55oC ≤ TA≤ +125oC8 - 5 - ns
9, 10, 11 -55oC ≤ TA≤ +125oC4 - 4 - ns
9, 10, 11 -55oC ≤ TA≤ +125oC 26 - 20 - ns
READY HOLD Time 11 VCC = 4.5V
and 5.5V
Status/PEACK Active
Delay, (Note 4)
Status/PEACK
Inactive Delay
(Note 3)
Address Valid
Delay (Note 2)
Write Data
Valid Delay, (Note 2)
12A VCC = 4.5V and
5.5V, CL = 100pF
IL = |2mA|
12B VCC = 4.5V and
5.5V, CL = 100pF
IL = |2mA|
13 VCC = 4.5V and
5.5V, CL = 100pF
IL = |2mA|
14 VCC = 4.5V and
5.5V, CL = 100pF
IL = |2mA|
9, 10, 11 -55oC ≤TA≤ +125oC 25 - 20 - ns
9, 10, 11 -55oC ≤ TA≤ +125oC 1 22 1 21 ns
9, 10, 11 -55oC ≤ TA≤ +125oC 1 30 1 24 ns
9, 10, 11 -55oC ≤ TA≤ +125oC 1 35 1 32 ns
9, 10, 11 -55oC ≤ TA≤ +125oC 0 40 0 31 ns
3-131
Page 5
80C286/883
TABLE 2. 80C286/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS (Continued)
AC Timings are Referenced to 0.8V and 2.0V Points of the Signals as Illustrated in Datasheet Waveforms, Unless Otherwise Noted. Device
Guaranteed and 100% Tested.
80C286/883
10MHz 12.5MHz
GROUP A
PARAMETER SYMBOL CONDITIONS
SUBGROUPS TEMPERATURE
MIN MAX MIN MAX
UNITS
HLDA Valid Delay
(Note 5)
NOTES:
1. Asynchronous inputs are INTR, NMI, HOLD , PEREQ, ERROR, and BUSY. This specification is given only for testing purposes, to assure
recognition at a specific CLK edge.
2. Delay from 1.0V on the CLK to 0.8V or 2.0V.
3. Delay from 1.0V on the CLK to 0.8V for Min (HOLD time) and to 2.0V for Max (inactive delay).
4. Delay from 1.0V on the CLK to 2.0V for Min (HOLD time) and to 0.8V for Max (active delay).
5. Delay from 1.0V on the CLK to 2.0V.
PARAMETER SYMBOL CONDITIONS NOTES TEMPERATURE
CLK Input Capacitance C
Other Input Capacitance C
I/O Capacitance C
Address/Status/Data
Float Delay
Address Valid to Status
SETUP Time
NOTES:
1. Output Load: CL = 100pF.
2. Delay measured from address either reaching 0.8V or 2.0V (valid) to status going active reaching 0.8V or status going inactive reaching
2.0V.
3. Delay from 1.0V on the CLK to Float (no current drive) condition.
4. IL = -6mA (VOH to Float), IL = 8mA (VOL to Float).
5. The parameters listed in Table 3 are controlled via design or process parameters and are not directly tested. These parameters are characterized upon initial design and after major process and/or design changes.
15 VCC = 4.5V and
5.5V, CL = 100pF
IL = |2mA|
TABLE 3. 80C286/883 ELECTRICAL PERFORMANCE SPECIFICATIONS
CLK
15 1, 3, 4, 5 -55oC ≤ TA≤ +125oC 0 47 0 32 ns
19 IL = |2.0mA| 1, 2, 5 -55oC ≤ TA≤ +125oC 27 - 20 - ns
FREQ = 1MHz 5 TA = +25oC - 10 - 10 pF
FREQ = 1MH 5 TA = +25oC - 10 - 10 pF
IN
FREQ = 1MH 5 TA = +25oC - 10 - 10 pF
I/O
9, 10, 11 -55oC ≤ TA≤ +125oC 0 47 0 25 ns
80C286/883
10MHz 12.5MHz
MIN MAX MIN MAX
UNITS
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS METHOD SUBGROUPS
Initial Test 100%/5004 Interim Test 100%/5004 1, 7, 9
PDA 100% 1
Final Test 100% 2, 3, 8A, 8B, 10, 11
Group A - 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Group C & D Samples/5005 1, 7, 9
3-132
Page 6
80C286/883
AC Electrical Specifications 82C284 and 82C288 Timing Specifications Are Given For Reference Only, And No Guarantee is
Implied.
82C284 Timing
10MHz 12.5MHz
SYMBOL PARAMETER
TIMING REQUIREMENTS
11 SRDY/SRDYEN Setup Time 15 - 15 - ns
12 SRDY/SRDYEN Hold Time 2 - 2 - ns
13 ARDY/ARDYEN Setup Time 5 - 5 - ns (Note 1)
14 ARDY/ARDYEN Hold Time 30 - 25 - ns (Note 1)
TIMING RESPONSES
19 PCLK Delay 0 20 0 16 ns CL = 75pF, IOL = 5mA,
NOTE:
1. These times are given for testing purposes to ensure a predetermined action.
UNIT TEST CONDITIONMIN MAX MIN MAX
IOH = -1mA
82C288 Timing
10MHz 12.5MHz
SYMBOL PARAMETER
TIMING REQUIREMENTS
UNIT TEST CONDITIONMIN MAX MIN MAX
12 CMDLY Setup Time 15 - 15 - ns
13 CMDLY Hold Time 1 - 1 - ns
TIMING RESPONSES
16 ALE Active Delay 1 16 1 16 ns
17 ALE Inactive Delay - 19 - 19 ns
19 DT/R Read Active Delay - 23 - 23 ns CL = 150pF
20 DEN Read Active Delay 0 21 0 21 ns IOL = 16mA Max
21 DEN Read Inactive Delay 3 23 3 21 ns IOH = -1mA Max
22 DT/R Read Inactive Delay 5 24 5 18 ns
23 DEN Write Active Delay - 23 - 23 ns
24 DEN Write Inactive Delay 3 23 3 23 ns
29 Command Active Delay from CLK 3 21 3 21 ns CL = 300pF
30 Command Inactive Delay from CLK 3 20 3 20 ns IOL = 32mA Max
3-133
Page 7
AC Specifications
80C286/883
4.0V
CLK INPUT
0.45V
4.0V
CLK INPUT
0.45V
2.4V
OTHER
DEVICE
INPUT
0.4V
3.6V 3.6V
1.0V1.0V
1.0V 1.0V
t
SETUP
2.0V
0.8V 0.8V
t
HOLD
t
t
DELAY
DELAY
3.6V3.6V
2.0V
(MAX)
(MIN)
DEVICE
OUTPUT
NOTE:
1. For AC testing, input rise and fall times are driven at 1ns per volt.
FIGURE 1. AC DRIVE AND MEASURE POINTS - CLK INPUT
2.0V
0.8V
3-134
Page 8
Waveforms
80C286/883
BUS CYCLE TYPE
CLK
S1 • S0
A
- A
23
M/IO,
COD
INTA
BHE, LOCK
80C286/88382C284 (SEE NOTE 2)82C288 (SEE NOTE 2)
D
- D
15
READY
SRDY +
SRDYEN
ARDY +
ARDYEN
PCLK
ALF
CMDLY
MWTC
T
I
V
OH
V
OL
3 1
φ2 φ2 φ1 φ2 φ1 φ2 φ1 φ2 φ1 φ2 φ1
2 12A 12B
13
0
0
READ CYCLE
ILLUSTRATED WITH ZERO
WAIT STATES
T
S
19
WRITE CYCLE
ILLUSTRATED WITH ONE
WAIT STATE
T
C
T
S
T
C
T
C
19
READ
(TI OR TS)
13
VALID ADDRESS VALID ADDRESS VALID IF T
13
13
VALID CONTROL VALID CONTROL
9
8
14
VALID WRITE DATA
VALID READ DATA
11
10
11
10
12
11
19 14
13
1919 20
16 17
12
13
13
12
13
12
29 30
S
15
29 30
(SEE NOTE 1)
MRDC
DT/
R
19
22
20 21
23
DEN
NOTES:
1. The modified timing is due to the CMDLY signal being active.
2. 82C254 and 82C288 Timing Waveforms are shown for reference only, and no guarantee is inplied.
FIGURE 2. MAJOR CYCLE TIMING
3-135
24
Page 9
80C286/883
Waveforms
BUS CYCLE TYPE
(SEE NOTE 1)
HOLD, PEREQ
(SEE NOTE 2)
ERROR, BUSY
(SEE NOTE 2)
CLK
PCLK
INTR, NMI
(Continued)
V
CH
V
CL
4
T
X
φ1
19 19
4
5
φ2
5
NOTES:
1. PCLK indicates which processor cycle phase will occur on the
next CLK. PCLK may not indicate the correct phase until the first
cycle is performed.
2. These inputs are asynchronous. The setup and hold times shown
assure recognition for testing purposes.
FIGURE 3. 80C286/883 ASYNCHRONOUS INPUT SIGNAL
TIMING
V
CLK
RESET
CLK
RESET
CH
φ2
V
CL
7
V
CH
V
CL
T
X
φ1 φ1
6
T
7
(SEE NOTE 1)
X
6
φ2
φ2φ2φ1
(SEE NOTE 1)
NOTE:
1. When RESET meets the setup time shown, the next CLK will
start or repeat φ1 of a processor cycle.
FIGURE 4. 80C286/883 RESET INPUT TIMING AND SUBSE-
QUENT PROCESSOR CYCLE PHASE
BUS CYCLE TYPE
CLK
HILDA
S1 • S0
PEACK
80C286/88380C284
BHE, LOCK
- A0,
A
23
M/
COD/
INTA
- D
D
15
PCLK
IO,
T
H
V
CH
V
CL
0
16
12B
(SEE NOTE 5)
φ2φ1 φ2φ1 φ2φ1 φ2φ1
13
(SEE NOTE 6)
THOR T
I
(SEE NOTE 4)
(NOTE 3)
12A
IF T
S
IF NPX TRANSFER
VALID
14
T
I
15
(SEE NOTE 1)
15
(SEE NOTE 2)
15
VALID IF WRITE
16
15
T
H
(SEE NOTE 3)
NOTES:
1. These signals may not be driven by the 80C286/883 during the time shown. The worst case in terms of latest float time is shown.
2. The data bus will be driven as shown if the last cycle before T
in the diagram was a write TC.
I
3. The 80C286/883 puts its status pins in a high impedance logic one state during TH.
4. For HOLD request set up to HLDA, refer to Figure 8.
5. BHE and LOCK are driven at this time but will not become valid until TS.
6. The data bus will remain in a high impedance state if a read cycle is performed.
FIGURE 5. EXITING AND ENTERING HOLD
3-136
Page 10
80C286/883
Waveforms
BUS CYCLE TYPE
COD INTA
CLK
S1 • S0
CLK
A23 -A
M/
IO,
PEACK
PEREQ
(Continued)
T
I
V
CH
V
CL
0
12A
T
φ2
S
φ1 φ2 φ2 φ1 φ2 φ1 φ1φ2
I/0 READ IF PROC. EXT. TO MEMORY
MEMORY READ IF MEMORY TO PROC. EXT
12B
(SEE NOTE 1)
(SEE NOTE 2)
T
C
1
I/O PORT ADDRESS 00FA(H) IF PROC. EXT. TO MEMORY TRANSFER
MEMORY ADDRESS IF MEMORY TO PROC. EXT. TRANSFER
4
5
T
S
MEMORY WRITE IF PROC. EXT. TO MEMORY
I/O WRITE IF MEMORY TO PROC. EXT.
MEMORY ADDRESS IF PROC. EXT. TO MEMORY TRANSFER I/O
PORT ADDRESS 00FA(H) IF MEMORY TO PROC. EXT. TRANSFER
T
C
T
I
NOTES:
1. PEACK alwa ys goes active during the first bus operation of a processor e xtension data operand transfer sequence . The first bus operation
will be either a memory read at operand address or I/O read at port address 00FA(H).
2. To prevent a second processor extension data operand transfer, the worst case maximum time (shown above) is 3 x - 12A
The actual, configuration dependent, maximum time is: 3 x - 12A
1
MAX
(4)
-
+N x 2 x
MIN
(1)
. N is the number of extra TC states added
1
MAX
-(4)
to either the first or second bus operation of the processor extension data operand transfer sequence.
FIGURE 6. 80C286/883 PEREQ/PEACK TIMING FOR ONE TRANSFER ONLY
MIN
BUS CYCLE TYPE
V
CH
CLK
V
CL
RESET
S1 • S0
PEACK
- A
A
23
0
BHE
M/
IO
COD/
INTA
LOCK
DAT A
HILDA
φ2 φ2 φ2 φ2 φ2φ1φ1φ1φ1
6
UNKNOWN
UNKNOWN
UNKNOWN
UNKNOWN
UNKNOWN
T
X
(SEE NOTE 1)
16
T
X
AT LEAST
16 CLK PERIODS
13
(SEE NOTE 2)
12B
T
X
15
T
I
7
13
13
(SEE NOTE 3)
6
NOTES:
1. Setup time for RESET ↑may be violated with the consideration that φ1 of the processor clock may begin one system CLK period later.
2. Setup and hold times for RESET ↓ must be met for proper operation, but RESET ↓ may occur during φ1 or φ2.
3. The data bus is only guaranteed to be in a high impedance state at the time shown.
FIGURE 7. INITIAL 80C286/883 PIN STATE DURING RESET
3-137
Page 11
80C286/883
Waveforms
BUS CYCLE TYPE
HOLD
S1 •S0
80C28680C28480C288
A
23
COD/
BHE, LOCK
D
15
SRDY +
SRDYEN
ARDY +
ARDYEN
CMDLY
MWTC
(Continued)
CLK
HLDA
- A
0
M/IO,
INTA
- D
0
BUS HOLD ACKNOWLEDGE
T
H
φ2φ1
(SEE NOTE 1)
T
H
φ2φ1
(SEE NOTE 4)
WRITE CYCLE
T
H
φ2φ1
T
S
φ2φ1
VALID
VALID
NOT READY NOT READY
T
C
φ2φ1
NOT READY NOT READY
T
C
φ2φ1
(SEE NOTE 5)
(SEE NOTE 2)
(SEE NOTE 3)
VALID
T
C
φ2φ1
(SEE NOTE 6)
(SEE NOTE 7)
READY
T
BUS HOLD
ACKNOWLEDGE
I
φ2φ1
(SEE NOTE 1)
(SEE NOTE 7)DELAY ENABLE
T
H
φ2φ1
V
OH
DT/R
DEN
ALE
TS - STATUS CYCLE
CT - COMMAND CYCLE
NOTES:
1. Status lines are held at a high impedance logic one by the 80C286 during a HOLD state.
2. Address, M/IO and COD/lNTA may start floating during any TC depending on when internal 80C286 bus arbiter decides to release bus to
external HOLD. The float starts in φ2 of TC.
3. BHE and LOCK may start floating after the end of any TC depending on when internal 80C286 bus arbiter decides to release bus to external HOLD. The float starts in φ1 of TC.
4. The minimum HOLD to HLDA time is shown. Maximum is one TH longer.
5. The earliest HOLD time is shown. It will always allow a subsequent memory cycle if pending is shown.
6. The minimum HOLD to HLDA time is shown. Maximum is a function of the instruction, type of bus cycle and other machine state (i.e.,
Interrupts, Waits, Lock, etc.).
7. Asynchronous ready allows termination of the cycle. Synchronous ready does not signal ready in this example. Synchronous ready state
is ignored after ready is signaled via the asynchronous input.
FIGURE 8. MULTIBUS WRITE TERMINATED BY ASYNCHRONOUS READY WITH BUS HOLD
3-138
Page 12
Burn-In Circuit
RO
RO
RO
RORORORORO
0F7
F
RC
RI
80C286/883
RORORORORO
RO
F5F4F
SS
V
33
32
RI
3130292827
56
RI
RO
RO
34
RI RI RI RIRI RI RI RI RI RI RI RI RIRI RI RI
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 3536
52
SS
V
3
DD
V
535455
RI
26
25
80C286/883 PGA
57
58596061626364
RI
RI
24
23
22
21
20
19
18
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
65
66
67
68
C1
RIRIRI
GND
5.5V
RO
RO
RO
RO
DD
V
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
RO
NOTES:
8. Supply V oltage: VDD = 5.5V, VSS = 0.0V.
9. Input V oltage Limits: V
(Maximum) = 0.8V, VIH (Minimum) = 2.0V
IL
10. Component Values: RC = 1kΩ±5%, RI = 10kΩ±5%, RO = Two Series 2.7kΩ±5%
11. Capacitor Values: C1 = 0.1 Microf arads
12. Oven Type and Frequency Requirements: Wakefield Oven Board f
f
= 6.25kHz, f5 = 3.125kHz, f7 = 781.25Hz.
4
= 100kHz, f3 = 12.5kHz,
0
13. Special Requirements: (a) ELECTROST ATIC DISCHARGE SENSITIVE. Proper Precautions Must be Used When Handling Units. (b) All Power Supplies
Must be at Zero Volts When the Boards are Inserted into the Ovens. (c) When Powering Up, the Inputs Must be Held Below the V
Voltage. (d) If an
DD
Excessive Current is Indicated at Final Inspection, Check to See if a Part is Inserted Backwards or is Latched Up.
3-139
Page 13
Die Characteristics
80C286/883
DIE DIMENSIONS:
286 x 283 x 19 ±1mils
METALLIZATION:
Type: Si-Al
Thickness: 8k
Å
Metallization Mask Layout
GLASSIVATION:
Type: Nitrox
Thickness: 10k
WORST CASE CURRENT DENSITY: 2 X 105A/cm
LEAD TEMPERATURE: (10s Soldering): ≤ 300oC
80C286/883
Å
2
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under an y patent or patent rights of Intersil or its subsidiaries.
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Spec Number
3-140
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