Maxwell Technologies’ 7872 high-speed 14-bit ADC microcircuit features a greater than 100 krad (Si) total dose tolerance;
depending upon orbit. The 7872 consists of a track/hold amplifier, successive-approximation ADC, 3V buried Zener reference and versatile interface logic. It features a self-contained,
laser- trimmed internal clock, so no external clock timing components are required. For minimum noise possible, the onchip clock may be overridden to synchronize the device operation to the digital system. The 7872 is a serial output device.
It is capable of interfacing to all modern microprocessors and
digital signal processors. The 7872 operates from ±5V power
supplies, accepts bipolar input signals of ±3V and is able to
convert full power signals up to 41.5 kHz. It is also fully specified for dynamic performance parameters including distortion
and signal-to-noise ratio.
Maxwell Technologies' patented R
ogy incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing
the required radiation shielding for a lifetime in orbit or space
mission. In a GEO orbit, R
krad (Si) radiation dose tolerance. This product is available
with screening up to Class S.
5% for Specified Performance5V
5% for Specified Performance-5V
Typically 6mA13mA max
Typically 4mA6mA max
Typically 50mW95mW max
D
1,2
(VDD = 5V ±5%, VSS = -5 V ± 5%, TA = -55 TO 125 °C UNLESSOTHERWISESPECIFIED)
ARAMETER/CONDITIONSYMBOLMINMAXUNITS
P
CONVST Pulse Widtht
SSTRB
to SCLK Falling Edge Setup Time t
SCLK Cycle Time
SCLK to Valid Data Delay: C
3
= 35 pF
L
4
SCLD Rising Edge to SSTRB
Bus Relinquish Time After SCLKt
1
10
t
11
t
12
t
13
14
50--ns
100--ns
440--ns
--155ns
20150ns
4100ns
1. All input signals are specified with tr = tr = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2. Serial timing is measured with a 4.7 k
Ω pull-up resistor on SDATA and SSTRB and a 2 kΩ pull-up resistor on SCLK. The
capacitance on all three outputs is 35 pF.
3. SCLK mark/space ration (measured from a voltage level of 1.6 V) is 40/60 to 60/40.
4. SDATA will drive higher capacitive loads, but this will add to t12 since it increases the external RC time constant (4.7kΩ/CL)
and hence, the time to reach 2.4 V.
Memory
12.19.01 Rev 4
All data sheets are subject to change without notice
Important Notice:
These data sheets are created using the chip manufacturer’s published specifications. Maxwell Technologies verifies
functionality by testing key parameters either by 100% testing, sample testing or characterization.
The specifications presented within these data sheets represent the latest and most accurate information available to
date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no
responsibility for the use of this information.
Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems
without express written approval from Maxwell Technologies.
Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.
7872
Memory
12.19.01 Rev 4
All data sheets are subject to change without notice