The 74VHCT574A is an advanced high-speed
CMOS OCT AL D- TYP E FL I P FL O P wi th 3 S TAT E
OUTPUTS NON INVERTING fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
These 8 bit D-Type flip-flop is controlled by a clock
input (CK) and an output enable input (OE
).
On the positive transition of the clock, the Q
outputs will be set to the logic states that were
setup at the D inputs.
Figure 1: Pi n C onnect ion And I E C Logic Sym bols
TSSOPSOP
Table 1: Order Codes
PACKAGET & R
SOP74VHCT574AMTR
TSSOP74VHCT574ATTR
When the (OE
) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
when (OE
) is high, the out puts will be in a hi gh
impedance state.
The Output control does not affect the internal
operation of flip flop; that is, the old data can be
retained or the new data can be entered even
while the outputs are off.
Power down protection is provided on all inputs
and outputs and 0 to 7V can be accepted on
inputs with no regard to the supply voltage. This
device can be used t o interf ace 5V to 3V s ince al l
inputs are equipped with TTL threshold.
All inputs and outputs are equipped with
protection circuits against static disc harge, giving
them 2KV ESD immunity and transient excess
voltage.
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (R ef er to Test Circ ui t). Averag e operating current can be obtained by t he following equation. I
Flip-Flop)
Table 9: Dynamic Switching Characteristics
Test ConditionValue
= 25°C
SymbolParameter
V
V
Dynamic Low
OLP
Voltage Quiet
OLV
Output (note 1, 2)
Dynamic High
V
IHD
Voltage Input
(note 1, 3)
Dynamic Low
V
ILD
Voltage Input
(note 1, 3)
V
CC
(V)
5.0
= 50 pF
5.03.5
C
L
5.01.5
T
A
Min.Typ. Max.Min.Max. Min. Max.
1.21.6
-1.6-1.2
-40 to 85°C -55 to 125°C
= CPD x VCC x fIN + ICC/8 (per
CC(opr)
-40 to 85°C -55 to 125°C
Unit
Unit
V
1) Worst case package.
2) Max number of outp ut s defined as (n). Data inpu t s are driven 0V to 3.0V, (n-1) outputs switc hi ng and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.0V. Inputs under test switching: 3.0V to threshold (V
), f=1MHz.
(V
IHD
ILD
), 0V to thresho l d
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Page 6
74VHCT574A
Figure 4: Te st Circuit
t
, t
PLH
PHL
, t
t
PZL
PLZ
t
, t
PZH
PHZ
TESTSWITCH
Open
V
CC
GND
CL =15/50pF or equivalent (i ncludes jig an d probe capac i tance)
= R1 = 1KΩ or equivalent
R
L
= Z
R
of pulse generator (typically 50Ω)
T
OUT
Figure 5: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle)
6/13
Page 7
Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle)
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