Datasheet 74VHCT574A Datasheet (ST)

Page 1
74VHCT574A
OCTAL D-TYP E FLIP FLOP
WITH 3 STATE OUTPUTS NON INVERTING
■ HIGH SPEED:
f
= 180 MHz (TYP.) at VCC = 5V
MAX
■ LOW POWER DISSIPATION:
I
= 4 µA (MAX.) at TA=25°C
■ COMPATIBLE WITH TTL OUTPUTS:
V
= 2V (MIN.), V
IH
■ POWER DOWN PROTECTION ON INPUTS
= 0.8V (MAX)
IL
& OUTPUTS
■ SYMMETRICAL OUTPUT IMPEDANCE:
|I
| = IOL = 8 mA (MIN)
OH
■ BALANCED PROPAGATION DELAYS:
t
≅ t
PLH
PHL
■ OPERATING VOLTAGE RANGE :
V
(OPR) = 4.5V to 5.5V
■ PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 574
■ IMPROVED LATCH-UP IMMUNITY
■ LOW NOISE: V
= 0.9V (MAX.)
OLP
DESCRIPTION
The 74VHCT574A is an advanced high-speed CMOS OCT AL D- TYP E FL I P FL O P wi th 3 S TAT E OUTPUTS NON INVERTING fabricated with sub-micron silicon gate and double-layer metal wiring C
2
MOS technology. These 8 bit D-Type flip-flop is controlled by a clock input (CK) and an output enable input (OE
). On the positive transition of the clock, the Q outputs will be set to the logic states that were setup at the D inputs.

Figure 1: Pi n C onnect ion And I E C Logic Sym bols

TSSOPSOP

Table 1: Order Codes

PACKAGE T & R
SOP 74VHCT574AMTR
TSSOP 74VHCT574ATTR
When the (OE
) input is low, the 8 outputs will be in a normal logic state (high or low logic level) and when (OE
) is high, the out puts will be in a hi gh impedance state. The Output control does not affect the internal operation of flip flop; that is, the old data can be retained or the new data can be entered even while the outputs are off. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used t o interf ace 5V to 3V s ince al l inputs are equipped with TTL threshold. All inputs and outputs are equipped with protection circuits against static disc harge, giving them 2KV ESD immunity and transient excess voltage.
Rev. 4
1/13December 2004
Page 2
74VHCT574A

Figure 2: Input Equivalent Circuit Table 2: Pin Description

PIN N° SYMBOL NAME AND FUNCTION
1OE
2, 3, 4, 5, 6,
7, 8, 9
12, 13, 14, 15, 16, 17,
18, 19
1 1 CK Clock Input (LOW-to-HIGH
10 GND Ground (0V) 20 V

Table 3: Truth Ta ble

INPUTS OUTPUT
D0 to D7 Data Inputs
Q0 to Q7 3-State Outputs
CC
3-State Output Enable Input (Active LOW)
Edge Triggered)
Positive Supply Voltage
OE
HXXZ
L X NO CHANGE LLL LHH
X : Don’t Care Z : High Impedance

Figure 3: Logic Diagram

CK D Q
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74VHCT574A

Table 4: Absolute Maximum Ratings

Symbol Parameter Value Unit
V
V V V
I
I
OK
I
or I
I
CC
T
T
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied
1) Output in OFF State
2) High or Low State

Table 5: Recommended Operating Conditions

Symbol Parameter Value Unit
V
V
V V T
dt/dv
Supply Voltage
CC
DC Input Voltage
I
DC Output Voltage (see note 1)
O
DC Output Voltage (see note 2) -0.5 to VCC + 0.5
O
DC Input Diode Current
IK
DC Output Diode Current DC Output Current
O
DC VCC or Ground Current
GND
Storage Temperature
stg
Lead Temperature (10 sec)
L
Supply Voltage
CC
Input Voltage
I
Output Voltage (see note 1)
O
Output Voltage (see note 2) 0 to V
O
Operating Temperature
op
Input Rise and Fall Time (see note 3) (V
= 5.0 ± 0.5V)
CC
-0.5 to +7.0 V
-0.5 to +7.0 V
-0.5 to +7.0 V
- 20 mA
± 20 mA ± 25 mA ± 50 mA
-65 to +150 °C 300 °C
4.5 to 5.5 V 0 to 5.5 V 0 to 5.5 V
CC
-55 to 125 °C 0 to 20 ns/V
V
V
1) Output in OFF State
2) High or Low State
3) V
from 0.8V to 2V
IN
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74VHCT574A

Table 6: DC Specifications

Symbol Parameter
V
V
V
+I
I
High Level Input
IH
Voltage Low Level Input
V
IL
Voltage High Level Output
OH
Voltage Low Level Output
OL
Voltage
I
High Impedance
OZ
Output Leakage Current
Input Leakage
I
I
Current Quiescent Supply
I
CC
Current Additional Worst
CC
Case Supply Current
Output Leakage
OPD
Current
Test Condition Value
= 25°C
T
V
CC
(V)
4.5 to
5.5
A
Min. Typ. Max. Min. Max. Min. Max.
222V
4.5 to
5.5
4.5
4.5
4.5
4.5
4.5 to
5.5
0 to
5.5
5.5
I
O
=-8 mA
I
O
=50 µA
I
O
=8 mA
I
O
= VIH or V
V
I
VO = 0V to 5.5V
= 5.5V or GND
V
I
= VCC or GND
V
I
4.4 4.5 4.4 4.4
3.94 3.8 3.7
0.0 0.1 0.1 0.1
IL
±0.25 ± 2.5 ± 2.5 µA
=-50 µA
One Input at 3.4V, other input at V
5.5
CC
or GND
= 5.5V
0
V
OUT
-40 to 85°C -55 to 125°C
Unit
0.8 0.8 0.8 V
V
0.36 0.44 0.55
V
± 0.1 ± 1.0 ± 1.0 µA
44040µA
1.35 1.5 1.5 mA
0.5 5.0 5.0 µA
Table 7: AC Electrical Characteristics (Input t
Test Condition Value
Symbol Parameter
t
Propagation Delay
PLH
t t
t t
t f
t
OSLH
t
OSHL
(*) Voltage range is 5.0V ± 0.5V Note 1: Parameter guaranteed by design. t
Time CK to Q
PHL
Output Enable
PZL
Time
PZH
Output Disable
PLZ
Time
PHZ
Maximum Clock
MAX
Frequency Output to Output
Skew time (note 1)
V
(V)
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
C
CC
L
(pF)
(*)
15 5.5 8.6 1.0 10.0 1.0 10.0
(*)
50 7.0 10.6 1.0 12.0 1.0 12.0
(*)
15
(*)
(*)
(*) (*)
(*)
soLH
= |t
RL = 1K
50 6.0 11.0 1.0 12.5 1.0 12.5 50 RL = 1KΩ 7.0 10.1 1.0 11.5 1.0 11.5 ns 15 90 140 80 80
50 85 130 50 1.5 1.5 1.5 ns
- t
pLHm
pLHn
= tf = 3ns)
r
Min. Typ. Max. Min. Max. Min. Max.
Ω
|, t
= |t
soHL
pHLm
= 25°C
T
A
-40 to 85°C -55 to 125°C
5.0 9.0 1.0 10.5 1.0 10.5
- t
|
pHLn
Unit
ns
ns
MHz
4/13
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74VHCT574A

Table 8: Capacitive Characteristics

Test Condition Value
= 25°C
Symbol Parameter
T
A
Min. Typ. Max. Min. Max. Min. Max.
C
C
C
Input Capacitance
IN
Output
OUT
Capacitance Power Dissipation
PD
Capacitance
410 10 10pF 9pF
25 pF
(note 1)
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (R ef er to Test Circ ui t). Averag e operating current can be obtained by t he following equation. I Flip-Flop)

Table 9: Dynamic Switching Characteristics

Test Condition Value
= 25°C
Symbol Parameter
V V
Dynamic Low
OLP
Voltage Quiet
OLV
Output (note 1, 2) Dynamic High
V
IHD
Voltage Input (note 1, 3)
Dynamic Low
V
ILD
Voltage Input (note 1, 3)
V
CC
(V)
5.0
= 50 pF
5.0 3.5
C
L
5.0 1.5
T
A
Min. Typ. Max. Min. Max. Min. Max.
1.2 1.6
-1.6 -1.2
-40 to 85°C -55 to 125°C
= CPD x VCC x fIN + ICC/8 (per
CC(opr)
-40 to 85°C -55 to 125°C
Unit
Unit
V
1) Worst case package.
2) Max number of outp ut s defined as (n). Data inpu t s are driven 0V to 3.0V, (n-1) outputs switc hi ng and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.0V. Inputs under test switching: 3.0V to threshold (V ), f=1MHz.
(V
IHD
ILD
), 0V to thresho l d
5/13
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74VHCT574A

Figure 4: Te st Circuit

t
, t
PLH
PHL
, t
t
PZL
PLZ
t
, t
PZH
PHZ
TEST SWITCH
Open
V
CC
GND
CL =15/50pF or equivalent (i ncludes jig an d probe capac i tance)
= R1 = 1KΩ or equivalent
R
L
= Z
R
of pulse generator (typically 50Ω)
T
OUT

Figure 5: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle)

6/13
Page 7

Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle)

74VHCT574A

Figure 7: Waveform - Pulse Width (f=1MHz ; 50% duty cycle)

7/13
Page 8
74VHCT574A
SO-20 MECHANICAL DATA
DIM.
A 2.35 2.65 0.093 0.104
A1 0.1 0.30 0.004 0.012
B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 12.60 13.00 0.496 0.512 E 7.4 7.6 0.291 0.299 e 1.27 0.050 H 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.4 1.27 0.016 0.050 k0° 8° 0° 8°
ddd 0.100 0.004
MIN. TYP MAX. MIN. TYP. MAX.
mm. inch
8/13
0016022D
Page 9
74VHCT574A
TSSOP20 MECHANICAL DATA
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 1.2 0.047
A1 0.05 0.15 0.002 0.004 0.006
A2 0.8 1 1.05 0.031 0.039 0.041
b 0.19 0.30 0.007 0.012
c 0.09 0.20 0.004 0.0079
D 6.4 6.5 6.6 0.252 0.256 0.260
E 6.2 6.4 6.6 0.244 0.252 0.260
E1 4.3 4.4 4.48 0.169 0.173 0.176
e 0.65 BSC 0.0256 BSC
K0˚ 8˚0˚ 8˚
L 0.45 0.60 0.75 0.018 0.024 0.030
A2
A
A1
b
e
K
c
L
E
D
E1
PIN 1 IDENTIFICATION
1
0087225C
9/13
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74VHCT574A
Tape & Reel SO-20 MECHANICAL
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 330 12.992 C 12.8 13.2 0.504 0.519 D 20.2 0.795 N 60 2.362
T 30.4 1.197 Ao 10.8 11 0.425 0.433 Bo 13.2 13.4 0.520 0.528 Ko 3.1 3.3 0.122 0.130 Po 3.9 4.1 0.153 0.161
P 11.9 12.1 0.468 0.476
DATA
10/13
Page 11
74VHCT574A
Tape & Reel TSSOP20 MECHANICAL DATA
mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 60 2.362
T 22.4 0.882 Ao 6.8 7 0.268 0.276 Bo 6.9 7.1 0.272 0.280 Ko 1.7 1.9 0.067 0.075 Po 3.9 4.1 0.153 0.161
P 11.9 12.1 0.468 0.476
11/13
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74VHCT574A

Table 10: Revision History

Date Revision Description of Change s
16-Dec-2004 4 Order Codes Revision - pag. 1.
12/13
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74VHCT574A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of s uch inf ormati on nor for a ny infr ing eme nt o f p atent s or o ther ri ghts of third parti es wh ic h m ay r esul t from i ts use. No license is gr an ted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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