Datasheet 74VHCT273A Datasheet (ST)

74VHCT273A

OCTAL D-TYPE FL IP FLO P W ITH CLEAR

■ HIGH SPEED:

f

= 170 MHz (TYP.) at VCC = 5V

MAX

■ LOW POWER DISSIPATION:

I

= 4 µA (MAX.) at TA=25°C

CC

■ COMPATIBLE WITH TTL OU TP U TS:

V

= 2V (MIN.), V

IH

■ POWER DOWN PROTECTION ON INPUTS

= 0.8V (MAX)

IL

& OUTPUTS

■ SYMMETRICAL OUTPUT IMPEDANCE:

|I

| = IOL = 8 mA (MIN)

OH

■ BALANCED PROPAGATION DELAYS :

t

≅ t

PLH

PHL

■ OPERATING VOLTAGE RANGE:

V

(OPR) = 4.5V to 5.5V

CC

■ PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 273

■ IMPROVED LATCH-UP IMMUNIT Y

■ LOW NOISE: V

= 0.9V (MAX.)

OLP

DESCRIPTION

The 74VHCT273A is an advanced high-speed CMOS OCTA L D-TY PE FL IP FL OP WIT H CLEA R fabricated with sub-micron silicon gate and double-layer metal wiring C

2

MOS technology. Information signals applied to D inputs are transferred to the Q o utputs on the positive going

TSSOPSOP

Table 1: Order Codes

PACKAGE T & R

SOP 74VHCT273AMTR

TSSOP 74VHCT273ATTR

edge of the clock pulse. When the CLE AR

input is held low, the Q outputs are held low independently of the other inputs. Power down protection is provided on all inputs and outputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used t o interf ace 5V to 3V s ince al l inputs are equipped with TTL threshold. All inputs and outputs are equipped with protection circuits against static disc harge, giving them 2KV ESD immunity and transient excess voltage.

Figure 1: Pin Conne ction And IEC Logic Symbol s

Rev. 3

1/13December 2004

74VHCT273A

Figure 2: Input Equivalent Circuit Table 2: Pin Description

PIN N° SYMBOL NAME AND FUNCTION

Table 3: Truth Table

1CLEAR

2, 5, 6, 9, 12,

15, 16,19

3, 4, 7, 8, 13,

14, 17, 18

1 1 CLOCK Clock Input (LOW-to-HIGH

10 GND Ground (0V) 20 V

Q0 to Q7 Flip-Flop Outputs

D0 to D7 Data Inputs

CC

Asynchronous Master Reset (Active LOW)

Edge Triggered)

Positive Supply Voltage

CLEAR

L X X L CLEAR

HL L HH H HX

X: Don’t care

Table 4: Logic Diagram

INPUTS OUTPUT

DCLOCKQ

Q

n

FUNCTION

NO CHANGE

This logi c di agram has not be used to est i m ate propaga tion delays

2/13

74VHCT273A

Table 5: Absolute Maximum Ratings

Symbol Parameter Value Unit

V

V V V

I

OK

I

or I

I

CC

T

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied

1) V

CC

2) High or Low State

Table 6: Recommended Operating Conditions

Symbol Parameter Value Unit

V

V V T

dt/dv

Supply Voltage

CC

DC Input Voltage

I

DC Output Voltage (see note 1)

O

DC Output Voltage (see note 2) -0.5 to VCC + 0.5

O

DC Input Diode Current

IK

DC Output Diode Current DC Output Current

O

DC VCC or Ground Current

GND

Storage Temperature

stg

Lead Temperature (10 sec)

L

= 0V

Supply Voltage

CC

Input Voltage

I

Output Voltage (see note 1)

O

Output Voltage (see note 2) 0 to V

O

Operating Temperature

op

Input Rise and Fall Time (see note 3) (V

= 5.0 ± 0.5V)

CC

-0.5 to +7.0 V

- 20 mA

± 20 mA ± 25 mA ± 50 mA

-65 to +150 °C 300 °C

4.5 to 5.5 V 0 to 5.5 V 0 to 5.5 V

CC

-55 to 125 °C 0 to 20 ns/V

V

1) V

= 0V

CC

2) High or Low State

3) V

from 0.8V to 2V

IN

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74VHCT273A

Table 7: DC Specifications

Symbol Parameter

V

+I

I

High Level Input

IH

Voltage Low Level Input

V

IL

Voltage High Level Output

OH

Voltage Low Level Output

OL

Voltage

I

Input Leakage

I

Current

I

Quiescent Supply

CC

Current Additional Worst

CC

Case Supply Current

Output Leakage

OPD

Current

Test Condition Value

= 25°C

T

V

CC

(V)

4.5 to

5.5

A

Min. Typ. Max. Min. Max. Min. Max.

222V

4.5 to

5.5

4.5

0 to

VI = 5.5V or GND

5.5 V

5.5

I

O

=-8 mA

I

O

=50 µA

I

O

=8 mA

I

O

= VCC or GND

I

4.4 4.5 4.4 4.4

3.94 3.8 3.7

0.0 0.1 0.1 0.1

=-50 µA

One Input at 3.4V, other input at V

5.5

CC

or GND

= 5.5V

0

V

OUT

-40 to 85°C -55 to 125°C

Unit

0.8 0.8 0.8 V

V

0.36 0.44 0.55

V

± 0.1 ± 1.0 ± 1.0 µA

44040µA

1.35 1.5 1.5 mA

0.5 5.0 5.0 µA

Table 8: AC Electrical Characteristics (Input t

Test Condition Value

Symbol Parameter

t

Propagation Delay

PLH

t t

Time CLOCK to Q

PHL

Propagation Delay

PHL

Time CLEAR

t

CLR Pulse Width

W

LOW

t

CK Pulse Width

W

HIGH or LOW Setup Time D to

t

s

CLOCK, HIGH or

to Q

LOW

t

Hold Time D to CK,

h

HIGH or LOW

t

REM

f

t

OSLH

t

OSHL

Removal Time CLR to CLOCK

Maximum Clock

MAX

Frequency Output to Output

Skew time (note 1)

V

5.0

C

CC

(V)

L

(pF)

(**)

15 5.8 8.2 1.0 10.0 1.0 10.0

(**)

50 6.8 9.2 1.0 11.0 1.0 11.0

(**)

15 7.5 10.0 1.0 11.6 1.0 11.6

(**)

50 8.5 11.0 1.0 12.6 1.0 12.6

(**)

15 75 170 65 65

(**)

50 50 160 45 45

(**)

50 1.0 1.0 1.0 ns

= tf = 3ns)

r

= 25°C

T

A

-40 to 85°C -55 to 125°C

Min. Typ. Max. Min. Max. Min. Max.

5.0 5.0 5.0 ns

2.0 2.0 2.0 ns

1.0 1.0 1.0 ns

Unit

ns

MHz

(*) Voltage range is 5.0V ± 0.5V Note 1: Parameter guaranteed by design. t

4/13

soLH

= |t

pLHm

- t

pLHn

|, t

soHL

= |t

pHLm

- t

pHLn

|

Table 9: Capacitive Characteristics

Test Condition Value

Symbol Parameter

C

Input Capacitance

IN

Power Dissipation

PD

Capacitance (note 1)

74VHCT273A

= 25°C

T

A

Min. Typ. Max. Min. Max. Min. Max.

610 10 10pF

16 pF

-40 to 85°C -55 to 125°C

Unit

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (R ef er to Test Circ ui t). Averag e operating current can be obtained by t he following equation. I Flip-Flop)

= CPD x VCC x fIN + ICC/8 (per

CC(opr)

Table 10: Dynamic Switching Characteristics

Test Condition Value

Symbol Parameter

V V

Dynamic Low

OLP

Voltage Quiet

OLV

Output (note 1, 2)

V

CC

(V)

5.0

T

A

Min. Typ. Max. Min. Max. Min. Max.

0.6 0.9

-0.9 -0.6

-40 to 85°C -55 to 125°C

Unit

= 25°C

Dynamic High

V

IHD

Voltage Input

5.0 2.0

= 50 pF

C

L

V

(note 1, 3) Dynamic Low

V

ILD

Voltage Input

5.0 0.8

(note 1, 3)

1) Worst case package.

2) Max number of outp ut s defined as (n). Data inpu t s are driven 0V to 3.0V, (n-1) outputs switc hi ng and one output at GND.

3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.0V. Inputs under test switching: 3.0V to threshold (V (V

), f=1MHz.

IHD

), 0V to thresho l d

ILD

Figure 3: Test Cir cuit

CL =15/50pF or equivalent (i ncludes jig an d probe capac i tance)

= Z

R

of pulse generator (typically 50Ω)

T

OUT

5/13

74VHCT273A

Figure 4: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle)

Figure 5: Waveform - Propagation Delays (f=1MHz; 50% duty cycle)

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Figure 6: Waveform - Recovery Time (f=1MHz; 50% duty cycle)

74VHCT273A

7/13

74VHCT273A

SO-20 MECHANICAL DATA

DIM.

A 2.35 2.65 0.093 0.104

A1 0.1 0.30 0.004 0.012

B 0.33 0.51 0.013 0.020 C 0.23 0.32 0.009 0.013 D 12.60 13.00 0.496 0.512 E 7.4 7.6 0.291 0.299 e 1.27 0.050 H 10.00 10.65 0.394 0.419 h 0.25 0.75 0.010 0.030 L 0.4 1.27 0.016 0.050 k0° 8° 0° 8°

ddd 0.100 0.004

MIN. TYP MAX. MIN. TYP. MAX.

mm. inch

8/13

0016022D

74VHCT273A

TSSOP20 MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 1.2 0.047

A1 0.05 0.15 0.002 0.004 0.006

A2 0.8 1 1.05 0.031 0.039 0.041

b 0.19 0.30 0.007 0.012

c 0.09 0.20 0.004 0.0079

D 6.4 6.5 6.6 0.252 0.256 0.260

E 6.2 6.4 6.6 0.244 0.252 0.260

E1 4.3 4.4 4.48 0.169 0.173 0.176

e 0.65 BSC 0.0256 BSC

K0˚ 8˚0˚ 8˚

L 0.45 0.60 0.75 0.018 0.024 0.030

A2

A

A1

b

e

K

c

L

E

D

E1

PIN 1 IDENTIFICATION

1

0087225C

9/13

74VHCT273A

Tape & Reel SO-20 MECHANICAL

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 330 12.992 C 12.8 13.2 0.504 0.519 D 20.2 0.795 N 60 2.362

T 30.4 1.197 Ao 10.8 11 0.425 0.433 Bo 13.2 13.4 0.520 0.528 Ko 3.1 3.3 0.122 0.130 Po 3.9 4.1 0.153 0.161

P 11.9 12.1 0.468 0.476

DATA

10/13

74VHCT273A

Tape & Reel TSSOP20 MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 330 12.992

C 12.8 13.2 0.504 0.519

D 20.2 0.795

N 60 2.362

T 22.4 0.882 Ao 6.8 7 0.268 0.276 Bo 6.9 7.1 0.272 0.280 Ko 1.7 1.9 0.067 0.075 Po 3.9 4.1 0.153 0.161

P 11.9 12.1 0.468 0.476

11/13

74VHCT273A

Table 11: Revision History

Date Revision Description of Change s

16-Dec-2004 3 Order Codes Revision - pag. 1.

12/13

74VHCT273A

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