The 74VHC245 is an advanced high-speed
CMOS OCTAL BUS TRANSCEIVER (3-STATE)
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
This IC is intended for two-way asynchronous
communication between data busses; the
TSSOPSOP
Table 1: Order Codes
PACKAGET & R
SOP74VHC245MTR
TSSOP74VHC245TTR
direction of data transmission is determined by
DIR input. The enable input G
can be used to
disable the device so that the busses are
effectivel y isolated.
All inputs and outputs are equipped with
protection circuits against static disc harge, giving
them 2KV ESD immunity and transient excess
voltage.
All floating bus terminals during High Z State must
be held HIGH or LOW.
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ±
Note 1: Parameter guaranteed by design. t
0.5V
soLH
= |t
pLHm
- t
pLHn
|, t
soHL
= |t
pHLm
- t
pHLn
|
Table 8: Capacitive Characteristics
Test ConditionValue
= 25°C
SymbolParameter
T
A
Min.Typ. Max.Min.Max. Min. Max.
C
C
C
Input Capacitance
IN
Output
I/O
Capacitance
Power Dissipation
PD
Capacitance
4101010pF
8pF
21pF
(note 1)
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
-40 to 85°C -55 to 125°C
= CPD x VCC x fIN + ICC/8 (per c ircuit )
CC(opr)
Unit
4/12
Page 5
Table 9: Dynamic Switching Characteristics
Test ConditionValue
SymbolParameter
V
V
Dynamic Low
OLP
Voltage Quiet
OLV
Output (note 1, 2)
V
(V)
5.0
CC
T
A
Min.Typ. Max.Min.Max. Min. Max.
0.60.9
-0.9-0.6
-40 to 85°C -55 to 125°C
= 25°C
Dynamic High
V
IHD
Voltage Input
5.03.5V
= 50 pF
C
L
(note 1, 3)
Dynamic Low
V
ILD
Voltage Input
5.01.5V
(note 1, 3)
1) Worst case package.
2) Max number of outp ut s defined as (n). Data inpu t s are driven 0V to 5.0V, (n-1) outputs switc hi ng and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (V
(V
), f=1MHz.
IHD
ILD
Figure 3: Test Circuit
74VHC245
Unit
V
), 0V to thresho l d
TESTSWITCH
t
, t
PLH
PHL
, t
t
PZL
PLZ
t
, t
PZH
PHZ
CL =15/ 50pF or e qui valent (includes jig an d probe capacit ance)
Information fur nished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of s uch inf ormati on nor for a ny infr ing eme nt o f p atent s or o ther ri ghts of third parties wh ich m ay res ult fr om it s us e. No li cens e i s gr an ted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Speci fications mentioned in this publication are subject
to change wi thout notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics produc ts are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
All other names are the property of their respective owners