Datasheet 74VHC240SJX, 74VHC240SJ, 74VHC240N, 74VHC240MX, 74VHC240MTCX Datasheet (Fairchild Semiconductor)

October 1992
Revised March 1999

74VHC240 Octal Buffer/Line Driver with 3-STATE Outputs

© 1999 Fairchild Semiconductor Corporation DS011506.prf www.fairchildsemi.com

74VHC240
Octal Buffer/Line Driver with 3-STATE Outputs

General Description

The VHC240 is an advanced high sp eed CMOS octal b us
buffer fabricated with silicon gate CMOS technology. It
achieves high speed operation similar to equivalent Bipolar
Schottky TTL while maintaining the CMOS low power dissi­pation. The VHC240 is an inverti ng 3-S TATE buffer having
two active-LOW output en able s. Th i s devic e i s desig ne d to
drive buslines or buffer memory address registers.

An input protection circuit en sures that 0V to 7V can be
applied to the input pins without re gard to the supply volt­age. This device can be used to interface 5V to 3V systems
and two supply systems such as b attery backup. This cir-

cuit prevents device destruction due to m i sma tche d s upp l y
and input voltages.

Features

■ High Speed: tPD = 3.6ns (typ) at TA = 25°C

■ Low power dissipation: I

CC

= 4 µA (max) @ TA = 25°C

■ High noise immunity: V

NIH

= V

NIL

= 28% VCC (min)

■ Power down protection is provided on all inputs

■ Low noise: V

OLP

= 0.9V (max)

■ Pin and function compatible with 74HC240

Ordering Code:

Surface mount pack ages are also available on Tape and Reel. Specify by appending the s uffix let te r “X” to the ordering code.

Logic Symbol

IEEE/IEC

Connection Diagram

Pin Descriptions

Order Number Package Number Package Description

74VHC240M M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide
74VHC240SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74VHC240MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74VHC240N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Names Description

OE

1

, OE

2

3-STATE Output Enable Inputs

I

0–I7

Inputs

O

0–O7

Outputs 3-STATE Outputs

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74VHC240

Truth Tables

H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance

Inputs Outputs

OE

1

I

n

(Pins 12, 14, 16, 18)

LL H
LH L
HX Z

Inputs Outputs

OE

1

I

n

(Pins 3, 5, 7, 9)

LL H
LH L
HX Z

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74VHC240

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

(Note 2)

Note 1: Absolute Maximum Ratings are valu es beyond whic h the device
may be damaged or ha ve its useful life impaire d. The datab ook specifica­tions should be met, without exception, to ensure that the system design is
reliable over its p ower supp ly, temperature, and o utput/input loading vari­ables.Fairchild does not reco m m end operation outside databook specifica­tions.

Note 2: Unused inputs must be held HIGH or LOW. They may not float.

DC Electrical Characteristics

Noise Characteristics

Note 3: Parameter gu aranteed by design.

Supply Voltage (VCC) −0.5V to +7.0V
DC Input Voltage (V

IN

) −0.5V to +7.0V

DC Output Voltage (V

OUT

) −0.5V to VCC + 0.5V

Input Diode Current (I

IK

) −20 mA

Output Diode Current (I

OK

) ±20 mA

DC Output Current (I

OUT

) ±25 mA

DC V

CC

/GND Current (ICC) ±75 mA

Storage Temperature (T

STG

) −65°C to +150°C

Lead Temperature (T

L

)

(Soldering, 10 seconds) 260°C

Supply Voltage (V

CC

) 2.0V to 5.5V

Input Voltage (V

IN

)0V to +5.5V

Output Voltage (V

OUT

)0V to V

CC

Operating Temperature (T

OPR

) −40°C to +85°C

Input Rise and Fall Time (t

r

, tf)

V

CC

= 3.3V ± 0.3V 0 ns/V ∼ 100 ns/V

V

CC

= 5.0V ± 0.5V 0 ns/V ∼ 20 ns/V

Symbol Parameter

V

CC

(V)

TA = 25°CT

A

= −40°C to +85°C

Units Conditions

Min Typ Max Min Max

V

IH

HIGH Level 2.0 1.50 1.50

V

Input Voltage 3.0 − 5.5 0.7 V

CC

0.7 V

CC

V

IL

LOW Level 2.0 0.50 0.50

V

Input Voltage 3.0 − 5.5 0.3 V

CC

0.3 V

CC

V

OH

HIGH Level 2.0 1.9 2.0 1.9

V

VIN = VIHIOH = −50 µA

Output Voltage 3.0 2.9 3.0 2.9 or V

IL

4.5 4.4 4.5 4.4

3.0 2.58 2.48
V

IOH = −4 mA

4.5 3.94 3.80 IOH = −8 mA

V

OL

LOW Level Output 2.0 0.0 0.1 0.1 VIN = VIHIOL = 50 µA
Voltage 3.0 0.0 0.1 0.1 V or V

IL

4.5 0.0 0.1 0.1

3.0 0.36 0.44
V

IOL = 4 mA

4.5 0.36 0.44 IOL = 8 mA

I

OZ

3-STATE Output 5.5 ±0.25 ±2.5 µAVIN = VIH or V

IL

Off-State Current V

OUT

= VCC or GND

I

IN

Input Leakage Current 0 − 5.5 ±0.1 ±1.0 µAVIN = 5.5V or GND

I

CC

Quiescent Supply Current 5.5 4.0 40.0 µAVIN = VCC or GND

Symbol Parameter

V

CC

(V)

TA = 25°C

Units Conditions

Typ Limits

V

OLP

(Note 3)

Quiet Output Maximum Dynamic V

OL

5.0 0.6 0.9

VCL = 50 pF

V

OLV

(Note 3)

Quiet Output Minimum Dynamic V

OL

5.0 −0.6 −0.9

VCL = 50 pF

V

IHD

(Note 3)

Minimum HIGH Level Dynamic Input Voltage

5.0 3.5

VCL = 50 pF

V

ILD

(Note 3)

Maximum LOW Level Dynamic Input Voltage 5.0 1.5 V CL = 50 pF

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74VHC240

AC Electrical Characteristics

Note 4: Paramete r guaranteed by desig n. t

OSLH

= |t

PLHmax

− t

PLHmin

|; t

OSHL

= |t

PHLmax

− t

PHLmin

|

Note 5: C

PD

is defined as the value of the internal equivalent capacitance w hic h is calculated from t he operating curren t co ns umption without loa d. Av erage

operating curren t can be obtained by the e quation: I

CC

(opr.) = CPD * VCC * fIN + ICC/8 (per bit).

Symbol Parameter

V

CC

(V)

TA = 25°CT

A

= −40°C to +85°C

Units Conditions

Min Typ Max Min Max

t

PLH

Propagation 3.3 ± 0.3 5.3 7.5 1.0 9.0

ns

CL = 15 pF

t

PHL

Delay Time 7.8 11.0 1.0 12.5 CL = 50 pF

5.0 ± 0.5 3.6 5.5 1.0 6.5
ns

CL = 15 pF

5.1 7.5 1.0 8.5 CL = 50 pF

t

PZL

3-STATE 3.3 ± 0.3 6.6 10.6 1.0 12.5

ns

RL = 1 kΩ CL = 15 pF

t

PZH

Output 9.1 14.1 1.0 16.0 CL = 50 pF
Enable Time 5.0 ± 0.5 4.7 7.3 1.0 8.5

ns

CL = 15 pF

6.2 9.3 1.0 10.5 CL = 50 pF

t

PLZ

3-STATE 3.3 ± 0.3 10.3 14.0 1.0 16.0

ns

RL = 1 kΩ CL = 50 pF

t

PHZ

Output Disable Time 5.0 ± 0.5 6.7 9.2 1.0 10.5 CL = 50 pF

t

OSLH

Output to 3.3 ± 0.3 1.5 1.5

ns

(Note 4) CL = 50 pF

t

OSHL

Output Skew 5.0 ± 0.5 1.0 1.0 CL = 50 pF

C

IN

Input Capacitance 4 10 10 pF VCC = Open

C

OUT

Output Capacitance 6 pF VCC = 5.0V

C

PD

Power Dissipation 17 pF (Note 5)
Capacitance

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74VHC240

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide

Package Number M20B

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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74VHC240

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC20

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.

74VHC240 Octal Buffer/Line Driver with 3-STATE Outputs

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are dev ic es or syste ms
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided i n the labe li ng, can be re a­sonably expected to result in a significant injury to the
user.

2. A critical componen t in any com ponent o f a l ife supp ort
device or system whose failu re to perform can b e rea­sonably expected to c ause th e fa i lure of the li fe s upp or t
device or system, or to affect its safety or effectiveness.

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N20A