Datasheet 74VHC174 Datasheet (ST)

74VHC174

HEX D-TYPE FLIP FLOP WITH CLEAR

■ HIGH SPEED:

f

= 175MHz (TYP.) at VCC = 5V

MAX

■ LOW POWER DISSIPATION:

I

= 4 µA (MAX.) at TA=25°C

CC

■ HIGH NOISE IMMUNITY:

V

= V

NIH

■ POWER DOWN PROTECTION ON INPUTS

■ SYMMETRICAL OUTPUT IMPEDANCE:

|I

| = IOL = 8 mA (MIN)

OH

■ BALANCED PROPAGATION DELAYS:

t

≅ t

PLH

■ OPERATING VOLTAGE RANGE:

V

(OPR) = 2V to 5.5V

CC

■ PIN AND FUNCTION COMPATIBLE WITH

= 28% VCC (MIN.)

NIL

PHL

74 SERIES 174

■ IMPROVED LATCH-UP IMMUNITY

■ LOW NOISE: V

= 0.8V (MAX.)

OLP

DESCRIPTION

The 74VHC174 is an advanced high-speed CMOS HEX D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C

2

MOS technology. Information signals applied to D inputs are transferred to the Q o utputs on the positive going edge of the clock pulse.

TSSOPSOP

Table 1: Order Codes

PACKAGE T & R

SOP 74VHC174MTR

TSSOP 74VHC174TTR

When the CLE AR

input is held low, the Q outputs are held low independently of the other inputs. Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static disc harge, giving them 2KV ESD immunity and transient excess voltage.

Figure 1: Pi n C onnect ion And I E C Logic Sym bols

Rev. 4

1/14November 2004

74VHC174

Figure 2: Input Equivalent Circuit Table 2: Pin Description

PIN N° SYMBOL NAME AND FUNCTION

Table 3: Truth Ta ble

1CLEAR

2, 5, 7, 10,

12, 15

3, 4, 6, 11,

13, 14

9 CLOCK Clock Input (LOW-to-HIGH,

8 GND Ground (0V)

16 V

Q0 to Q5 Flip-Flop Outputs

D0 to D5 Data Inputs

CC

Asynchronous Maste r Reset (Active LOW)

Edge Triggered)

Positive Supply Voltage

CLEAR

L X X L CLEAR

HL L HH H HX

X : Don’t Care

Figure 3: Logic Diagram

INPUTS OUTPUTS

DCLOCKQ

Q

n

FUNCTION

NO CHANGE

This log i c diagram has not to be used to es timate pro pagation del ays

2/14

74VHC174

Table 4: Absolute Maximum Ratings

Symbol Parameter Value Unit

V

I

OK

I

or I

I

CC

T

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied

Table 5: Recommended Operating Conditions

Symbol Parameter Value Unit

V

V V T

dt/dv

Supply Voltage

CC

DC Input Voltage

I

DC Output Voltage -0.5 to VCC + 0.5

O

DC Input Diode Current

IK

DC Output Diode Current DC Output Current

O

DC VCC or Ground Current

GND

Storage Temperature

stg

Lead Temperature (10 sec)

L

Supply Voltage

CC

Input Voltage

I

Output Voltage 0 to V

O

Operating Temperature

op

Input Rise and Fall Time (note 1) (V (V

= 3.3 ± 0.3V)

CC

= 5.0 ± 0.5V)

CC

-0.5 to +7.0 V

- 20 mA

± 20 mA ± 25 mA ± 50 mA

-65 to +150 °C 300 °C

2 to 5.5 V 0 to 5.5 V

CC

-55 to 125 °C 0 to 100

0 to 20

ns/V

V

1) VIN from 30 % t o 70% of V

CC

3/14

74VHC174

Table 6: DC Specifications

Symbol Parameter

V

High Level Input

IH

Voltage

V

Low Level Input

IL

Voltage

High Level Output

OH

Voltage

Low Level Output

OL

Voltage

I

Input Leakage

I

Current

I

Quiescent Supply

CC

Current

3.0 to

Test Condition Value

V

(V)

CC

T

A

Min. Typ. Max. Min. Max. Min. Max.

-40 to 85°C -55 to 125°C

= 25°C

2.0 1.5 1.5 1.5

5.5

0.7V

CC

0.7V

CC

0.7V

CC

2.0 0.5 0.5 0.5

5.5

2.0

3.0

4.5

3.0

4.5

2.0

3.0

4.5

3.0

4.5

0 to

VI = 5.5V or GND

5.5 V

5.5

IO=-50 µA I

=-50 µA

O

=-50 µA

I

O

=-4 mA

I

O

=-8 mA

I

O

IO=50 µA

=50 µA

I

O

=50 µA

I

O

=4 mA

I

O

=8 mA

I

O

= VCC or GND

I

0.3V

CC

1.9 2.0 1.9 1.9

2.9 3.0 2.9 2.9

4.4 4.5 4.4 4.4

2.58 2.48 2.4

3.94 3.8 3.7

0.0 0.1 0.1 0.1

0.36 0.44 0.55

± 0.1 ± 1 ± 1 µA

44040µA

0.3V

CC

0.3V

CC

Unit

V

4/14

Table 7: AC Electrical Characteristics (Input tr = tf = 3ns)

Test Condition Value

Symbol Parameter

t

Propagation Delay

PLH

t

Time

PHL

CLOCK to Q

Propagation Delay

PHL

Time CLEAR

t

CLEAR Pulse

W

Width LOW

t

CLEAR Pulse

W

Width HIGH or

to Q

LOW

t

Setup Time D to

s

CLOCK, HIGH or LOW

t

Hold Time D to

h

CLOCK, HIGH or LOW

t

REM

f

MAX

Recovery Time

to CLOCK

CLEAR Maximum Clock

Frequency

V

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

3.3

5.0

C

CC

(V)

L

(pF)

(*)

15 5.8 11.0 1.0 13.0 1.0 13.0

(*)

50 7.5 14.5 1.0 16.5 1.0 16.5

(**)

15 4.1 7.2 1.0 8.5 1.0 8.5

(**)

50 5.5 9.2 1.0 10.5 1.0 10.5

(*)

15 7.4 11.4 1.0 13.5 1.0 13.5

(*)

50 9.9 14.9 1.0 17.0 1.0 17.0

(**)

15 5.1 7.6 1.0 9.0 1.0 9.0

(**)

50 6.6 9.6 1.0 11.0 1.0 11.0

(*)

(**)

(*)

(**)

(*)

(**)

(*)

(**)

(*)

(**)

(*)

15 95 150 80 80

(*)

50 55 85 50 50

(**)

15 130 175 110 110

(**)

50 90 120 80 80

T

A

Min. Typ. Max. Min. Max. Min. Max.

= 25°C

74VHC174

-40 to 85°C -55 to 125°C

5.0 5.0 5.0

5.0 6.0 6.0

4.5 4.5 4.5

0.0 0.0 0.0

0.5 0.5 0.5

3.0 3.0 3.0

2.5 2.5 2.5

Unit

ns

MHz

(*) Voltage range is 3.3V ± 0.3V (**) Voltage range is 5.0V ±

0.5V

Table 8: Capacitive Characteristics

Test Condition Value

= 25°C

Symbol Parameter

T

A

Min. Typ. Max. Min. Max. Min. Max.

C

Input Capacitance

IN

Power Dissipation

PD

Capacitance

610 10 10pF

15 pF

(note 1)

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without load. (R ef er to Test Circ ui t). Averag e operating current can be obtained by t he following equation. I Flip-Flop)

-40 to 85°C -55 to 125°C

= CPD x VCC x fIN + ICC/6 (per

CC(opr)

Unit

5/14

74VHC174

Table 9: Dynamic Switching Characteristics

Test Condition Value

= 25°C

Symbol Parameter

V V

Dynamic Low

OLP

Voltage Quiet

OLV

Output (note 1, 2)

V

CC

(V)

5.0

T

A

Min. Typ. Max. Min. Max. Min. Max.

0.3 0.8

-0.8 -0.3

Dynamic High

V

IHD

Voltage Input

5.0 3.5 V

= 50 pF

C

L

(note 1, 3) Dynamic Low

V

ILD

Voltage Input

5.0 1.5 V

(note 1, 3)

1) Worst case package.

2) Max number of outp ut s defined as (n). Data inpu t s are driven 0V to 5.0V, (n-1) outputs switc hi ng and one output at GND.

3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (V (V

), f=1MHz.

IHD

Figure 4: Te st Circuit

-40 to 85°C -55 to 125°C

ILD

Unit

V

), 0V to thresho l d

CL =15/50pF or equivalent (i ncludes jig an d probe capac i tance)

= Z

R

of pulse generator (typically 50Ω)

T

OUT

6/14

74VHC174

Figure 5: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle)

Figure 6: Waveform - Propagation Delays (f=1MHz; 50% duty cycle)

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74VHC174

Figure 7: Waveform - Recovery Time (f=1MHz; 50% duty cycle)

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SO-16 MECHANICAL DATA

74VHC174

DIM.

A 1.75 0.068 a1 0.1 0.25 0.004 0.010 a2 1.64 0.063

b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010

C 0.5 0.019 c1 45° (typ.)

D 9.8 10 0.385 0.393

E 5.8 6.2 0.228 0.244

e 1.27 0.050 e3 8.89 0.350

F 3.8 4.0 0.149 0.157

G 4.6 5.3 0.181 0.208

L 0.5 1.27 0.019 0.050

M 0.62 0.024

S8° (max.)

MIN. TYP MAX. MIN. TYP. MAX.

mm. inch

0016020D

9/14

74VHC174

TSSOP16 MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 1.2 0.047

A1 0.05 0.15 0.002 0.004 0.006

A2 0.8 1 1.05 0.031 0.039 0.041

b 0.19 0.30 0.007 0.012

c 0.09 0.20 0.004 0.0079

D 4.9 5 5.1 0.193 0.197 0.201

E 6.2 6.4 6.6 0.244 0.252 0.260

E1 4.3 4.4 4.48 0.169 0.173 0.176

e 0.65 BSC 0.0256 BSC

K0˚ 8˚0˚ 8˚

L 0.45 0.60 0.75 0.018 0.024 0.030

A2

A

A1

b

e

c

K

L

E

D

E1

PIN 1 IDENTIFICATION

10/14

1

0080338D

74VHC174

Tape & Reel SO-16 MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 330 12.992

C 12.8 13.2 0.504 0.519 D 20.2 0.795 N 60 2.362

T 22.4 0.882 Ao 6.45 6.65 0.254 0.262 Bo 10.3 10.5 0.406 0.414 Ko 2.1 2.3 0.082 0.090 Po 3.9 4.1 0.153 0.161

P 7.9 8.1 0.311 0.319

11/14

74VHC174

Tape & Reel TSSOP16 MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 330 12.992

C 12.8 13.2 0.504 0.519 D 20.2 0.795 N 60 2.362

T 22.4 0.882 Ao 6.7 6.9 0.264 0.272 Bo 5.3 5.5 0.209 0.217 Ko 1.6 1.8 0.063 0.071 Po 3.9 4.1 0.153 0.161

P 7.9 8.1 0.311 0.319

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Table 10: Revision History

Date Revision Description of Change s

12-Nov-2004 4 Order Codes Revision - pag. 1.

74VHC174

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74VHC174

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