The 74VHC157 is an advanced high-speed
CMOS QUAD 2-CHANNEL MULTIPLEXER
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS technology.
It consists of fo ur 2-input digital multiplexer with
common select and strobe inputs. It is a
non-inverting multiplexer. When the STROBE
TSSOPSOP
Table 1: Order Codes
PACKAGET & R
SOP74VHC157MTR
TSSOP74VHC157TTR
input is held high selection of data is inhibited and
all the outputs become low. The SELECT
decoding determines whether the A or B inputs
get routed to their corresponding Y outputs.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V t o 3V. All inputs and outputs
are equipped with protection circuits against static
discharge, giving them 2KV ESD immunity and
transient excess voltage.
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
Table 5: Recommended Operating Conditions
SymbolParameterValueUnit
V
V
V
T
dt/dv
Supply Voltage
CC
DC Input Voltage
I
DC Output Voltage-0.5 to VCC + 0.5
O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCC or Ground Current
GND
Storage Temperature
stg
Lead Temperature (10 sec)
L
Supply Voltage
CC
Input Voltage
I
Output Voltage0 to V
O
Operating Temperature
op
Input Rise and Fall Time (note 1) (V
(V
= 3.3 ± 0.3V)
CC
= 5.0 ± 0.5V)
CC
-0.5 to +7.0V
-0.5 to +7.0V
- 20mA
± 20mA
± 25mA
± 50mA
-65 to +150°C
300°C
2 to 5.5V
0 to 5.5V
CC
-55 to 125°C
0 to 100
0 to 20
ns/V
V
V
1) VIN from 30 % t o 70% of V
CC
3/12
Page 4
74VHC157
Table 6: DC Specifications
SymbolParameter
V
V
V
High Level Input
IH
Voltage
V
Low Level Input
IL
Voltage
High Level Output
OH
Voltage
Low Level Output
OL
Voltage
Input Leakage
I
I
Current
Quiescent Supply
I
CC
Current
V
3.0 to
3.0 to
0 to
Test ConditionValue
= 25°C
(V)
CC
T
A
Min.Typ. Max.Min.Max. Min. Max.
-40 to 85°C -55 to 125°C
2.01.51.51.5
5.5
0.7V
CC
0.7V
CC
0.7V
CC
2.00.50.50.5
5.5
2.0
3.0
4.5
3.0
4.5
2.0
3.0
4.5
3.0
4.5
5.5
5.5
=-50 µA
I
O
=-50 µA
I
O
=-50 µA
I
O
I
=-4 mA
O
=-8 mA
I
O
=50 µA
I
O
=50 µA
I
O
I
=50 µA
O
=4 mA
I
O
=8 mA
I
O
V
= 5.5V or GND
I
= VCC or GND
V
I
0.3V
CC
1.92.01.91.9
2.93.02.92.9
4.44.54.44.4
2.582.482.4
3.943.83.7
0.00.10.10.1
0.00.10.10.1
0.00.10.10.1
0.360.440.55
0.360.440.55
± 0.1± 1± 1µA
44040µA
0.3V
CC
0.3V
CC
Unit
V
V
V
V
Table 7: AC Electrical Characteristics (Input t
Test ConditionValue
SymbolParameter
t
Propagation Delay
PLH
t
t
t
t
t
(*) Voltage range is 3.3V ± 0.3V
(**) Voltage range is 5.0V ±
Time
PHL
A, B to Y
Propagation Delay
PLH
Time
PHL
SELECT to Y
Propagation Delay
PLH
Time STROBE
PHL
0.5V
to Y
V
3.3
3.3
5.0
5.0
3.3
3.3
5.0
5.0
3.3
3.3
5.0
5.0
C
CC
(V)
L
(pF)
(*)
156.29.71.011.51.011.5
(*)
508.713.21.015.01.015.0
(**)
154.16.41.07.51.07.5
(**)
505.68.41.09.51.09.5
(*)
158.413.21.015.51.015.5
(*)
5010.916.71.019.01.019.0
(**)
155.38.11.09.51.09.5
(**)
506.810.11.011.51.011.5
(*)
158.713.61.016.01.016.0
(*)
5011.217.11.019.51.019.5
(**)
155.68.61.010.01.010.0
(**)
507.110.61.012.01.012.0
= tf = 3ns)
r
= 25°C
T
A
-40 to 85°C -55 to 125°C
Min.Typ. Max.Min.Max. Min. Max.
Unit
ns
ns
ns
4/12
Page 5
Table 8: Capacitive Characteristics
Test ConditionValue
SymbolParameter
C
C
Input Capacitance
IN
Power Dissipation
PD
Capacitance
(note 1)
74VHC157
= 25°C
T
A
Min.Typ. Max.Min.Max. Min. Max.
6101010pF
18pF
-40 to 85°C -55 to 125°C
Unit
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (R ef er to Test Circ ui t). Averag e operating current can be obtained by t he following equation. I
channel)
= CPD x VCC x fIN + ICC/4 (per
CC(opr)
Table 9: Dynamic Switching Characteristics
Test ConditionValue
SymbolParameter
V
V
Dynamic Low
OLP
Voltage Quiet
OLV
Output (note 1, 2)
V
CC
(V)
5.0
T
A
Min.Typ. Max.Min.Max. Min. Max.
0.30.8
-0.8-0.3
-40 to 85°C -55 to 125°C
Unit
V
= 25°C
Dynamic High
V
IHD
Voltage Input
5.03.5V
= 50 pF
C
L
(note 1, 3)
Dynamic Low
V
ILD
Voltage Input
5.01.5V
(note 1, 3)
1) Worst case package.
2) Max number of outp ut s defined as (n). Data inpu t s are driven 0V to 5.0V, (n-1) outputs switc hi ng and one output at GND.
3) Max number of data inputs (n) switching. (n-1) switching 0V to 5.0V. Inputs under test switching: 5.0V to threshold (V
(V
), f=1MHz.
IHD
), 0V to thresho l d
ILD
Figure 4: Test Circuit
CL =15/50pF or equivalent (i ncludes jig an d probe capac i tance)
= Z
R
of pulse generator (typically 50Ω)
T
OUT
5/12
Page 6
74VHC157
Figure 5: Waveform - Propagation Delays For Inverting Conditions
Figure 6: Waveform - Propagation Delays For Non-inverting Conditions
Information fur nished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of s uch inf ormati on nor for a ny infr ing eme nt o f p atent s or o ther ri ghts of third parties wh ich m ay res ult fr om it s us e. No li cens e i s gr an ted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Speci fications mentioned in this publication are subject
to change wi thout notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
The ST logo is a registered trademark of STMicroelectronics
All other names are the property of their respective owners