The 74V2T07 is an advanced high-speed CMOS
TRIPLE BUFFE R (OPEN DRAIN) fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology.
The internal circuit i s composed of 2 stages
including buffer output, which provide high noise
immunity and stable output.
SOT23-8L
ORDER CODES
PACKAGET & R
SOT23-8L74V2T07STR
Power down protection is prov ided on input and 0
to 7V c an be accepted on input with no regard t o
the supply voltage. This device can be us ed to
interface5Vto3V.
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
Supply Voltage
CC
DC Input Voltage
I
DC Output Voltage-0.5 to VCC+ 0.5
O
DC Input Diode Current
IK
DC Output Diode Current
DC Output Current
O
DC VCCor Ground Current
GND
Storage Temperature
stg
Lead Temperature (10 sec)
L
V
CC
Positive Supply Voltage
AY
LL
HZ
-0.5 to +7.0V
-0.5 to +7.0V
V
-20mA
± 20mA
± 25mA
± 50mA
-65 to +150°C
260°C
RECOMMENDED OPERATING CONDITIONS
SymbolParameterValueUnit
V
V
V
T
dt/dv
1) VINfrom0.8V to 2V
2/7
Supply Voltage
CC
Input Voltage
I
Output Voltage0 to V
O
Operating Temperature
op
Input Rise and Fall Time (note 1) (V
=5.0±0.5V)
CC
4.5 to 5.5V
0 to 5.5V
CC
-55 to 125°C
0 to 20ns/V
V
Page 3
DC SPECIFICATIONS
SymbolParameter
V
V
∆I
High Level Input
IH
Voltage
V
Low Level Input
IL
Voltage
Low Level Output
OL
Voltage
High Impedance
I
OZ
Output Leakage
Current
Input Leakage
I
I
Current
Quiescent Supply
I
CC
Current
Additional Worst
CC
Case Supply
Current
Test ConditionValue
= 25°C
T
V
CC
(V)
4.5to
A
Min.Typ. Max.Min.Max.Min.Max.
222V
5.5
4.5to
5.5
4.5
4.5
5.5
0to
5.5
5.5
IO=50 µA0.00.10.10.1V
=8 mA0.360.440.55
I
O
VI=VIHor V
IL
±0.25± 2.5± 5.0µA
VO=VCCor GND
VI= 5.5V or GND
V
I=VCC
or GND
One Input at 3.4V,
other input at V
5.5
CC
or GND
74V2T07
-40 to 85°C -55 to 125°C
0.80.80.8V
± 0.1± 1.0± 1.0µA
11020µA
1.351.51.5mA
Unit
AC ELECTRICAL CHARACTERISTICS (Input t
r=tf
=3ns)
Test ConditionValue
SymbolParameter
t
t
(*) Voltage range is5.0V ± 0.5V
Enable Delay Time
PZL
Disable Delay Time
PLZ
T
V
CC
(V)
C
(pF)
L
A
Min.Typ. Max.Min.Max.Min.Max.
5.0 (*)153.77.01.08.01.09.0
5.0 (*)504.18.01.09.01.010.0
5.0 (*)154.37.01.08.01.09.0
5.0 (*)504.78.01.09.01.010.0
-40 to 85°C -55 to 125°C
Unit
ns
ns
= 25°C
CAPACITIVE CHARACTERISTICS
Test ConditionValue
= 25°C
SymbolParameter
T
A
Min.Typ. Max.Min.Max.Min.Max.
C
C
C
Input Capacitance4101010pF
IN
Output
OUT
Capacitance
Power Dissipation
PD
Capacitance
5pF
9pF
(note 1)
1) CPDis defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
-40 to 85°C -55 to 125°C
CC(opr)=CPDxVCCxfIN+ICC
Unit
/3
3/7
Page 4
74V2T07
TEST CIRCUIT
CL= 15/50pF or equivalent (includes jig and probe capacitance)
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mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
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