(OPR) = 4.5V to 5.5V (1.2V Data Retention)
(OPR) = 2.7V to 5.5V (1.2V Data Retention)
= 5.0V
CCB
=0.3V (TYP.) at
OLP
=3.3V
CCB
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES C4245
■ IMPROVED LATCH-UP I MMUN ITY
DESCRIPTION
The 74LVXC4245 is a dual supply 8 bit
configurable low voltage CMOS OCTAL BUS
TRANSCEIVER fabricated with sub-micron silicon
gate and double-layer metal wiring C
2
MOS
technology. Designed for use as an interface
between a 5V bus and a 3.3V to 5V bus in a mixed
5V/3.3V supply systems, it achieves high speed
operation while maintaining the CMOS low power
dissipation.
TSSOPSOP
Table 1: Order Codes
PACKAGET & R
SOP74LVXC4245MTR
TSSOP74LVXC4245TTR
This IC is intended for two-way asynchronous
communication between data buses and the
direction of data transmission is determined by
DIR input. The enable input G
can be used to
disable the device so that the buses are effectively
isolated.
The A-port interfaces with the 5V bus, the B-port
with the 3.3V to 5V bus.
All inputs are equipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the sa me direction, either HIGH or LOW (t
2) Param eter guaran teed by design
3) Typical values referred at V
(*) Volt age Range is 5.0V
± 0.5
= 5.0V, V
CCA
CCB
= | t
OSLH
= 5.0V or V
PLHm
CCA
- t
PLHn
= 5.0V, V
|, t
OSHL
CCB
= | t
PHLm
= 3.3V
- t
PHLn
|
6/14
Page 7
Table 10: Capacitive Characteristics
Test ConditionValue
SymbolParameter
C
Input
INA
Capacitance
C
Input/Output
I/O
Capacitance
C
Dynamic Low
PD
Level Quiet
Output (note 1)
A to B
Dynamic Low
C
PD
Level Quiet
Output (note 1)
B to A
V
V
CCA
CCB
(V)
(V)
open open4.5101010V
5.03.310V
5.03.355V
5.03.340V
74LVXC4245
= 25 °C
T
A
Min.Typ. Max.Min.Max. Min. Max.
-40 to 85 °C -55 to 125°C
Unit
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (R efer to Test Circuit). Average curre nt can be obta i ned by the following equa t i on. I
= CPD x VCC x fIN + ICC/8 (per circuit)
CC(opr)
Figure 3: Test Circuit
TESTSWITCH
, t
t
PLH
PHL
, t
t
PZLH
PLZ
t
, t
PZH
PHZ
CL = 50pF or equivalent (includes jig and p robe capacit ance)
R
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