The 74LVX86 is a low voltage CMOS QUAD
EXCLUSIVE OR GATE fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology. It is ideal for low
TSSOPSOP
Table 1: Order Codes
PACKAGET & R
SOP74LVX86MTR
TSSOP74LVX86TTR
power, battery operated and low noise 3.3V
applications.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V
system. It combines high speed performance with
the true CMOS low power consumption. All inputs
and outputs are eq uipped with protection circuits
against static discharge, giving them 2KV ESD
immunity and transient excess voltage.
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the sa m e di rection, ei ther HIGH or LOW
2) Param eter guaran teed by design
(*) Voltage range is 3.3V ±
Propagation Delay
Time
Output To Output
Skew Time (note1,
2)
0.3V
V
C
CC
(V)
L
(pF)
2.7157.514.51.017.51.017.5
2.75010.018.01.021.01.021.0
(*)
3.3
3.3
155.89.31.011.01.011.0
(*)
508.312.81.014.51.014.5
2.7500.51.01.51.5
(*)
3.3
50
T
A
Min.Typ. Max.Min.Max. Min. Max.
0.51.01.51.5
Table 9: Capacitive Characteristics
Test ConditionValue
= 25°C
SymbolParameter
C
C
Input Capacitance
IN
Power Dissipation
PD
Capacitance
(note 1)
V
CC
(V)
3.34101010pF
3.318pF
T
A
Min.Typ. Max.Min.Max. Min. Max.
-40 to 85°C -55 to 125°C
-40 to 85°C -55 to 125°C
Unit
ns
ns
Unit
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
= CPD x VCC x fIN + ICC/4 (per gate)
CC(opr)
Figure 3: Test Circuit
CL =15/50pF or equivalent (i ncludes jig an d probe capac i tance)
R
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