Datasheet 74LVX594 Datasheet (ST)

74LVX594

LOW VOLTAGE CMOS 8 BIT SHIFT REGISTER

WITH OUTPUT REGISTER (5V TOLERANT INPUTS)

■ HIGH SPEED:

t

= 5.5ns (TYP.) at V

PD

■ 5V TOLERANT INPUTS

■ INPUT VOLTAGE LEVEL:

V

=0.8V , VIH=2V at VCC=3V

IL

■ LOW POWER DISSIPATION:

I

= 4 µA (MAX.) at TA=25°C

CC

■ LOW NOISE:

V

= 0.3V (TYP.) at VCC = 3.3V

OLP

■ SYMMETRICAL OUTPUT IMPEDANCE:

|I

| = IOL = 4mA (MIN)

OH

■ BALANCED PROPAGATION DELAYS:

t

≅ t

PLH

■ OPERATING VOLTAGE RANGE:

V

CC

■ PIN AND FUNCTION COMPATIBLE WITH

PHL

(OPR) = 2V to 3.6V (1.2V Data Retention)

CC

= 3.3V

74 SERIES 594

■ IMPROVED LATCH-UP IMMUN ITY

■ POWER DOWN PROTECTION ON INPUTS

DESCRIPTION

The 74LVX594 is a low voltage CMOS 8 BIT
SHIFT REGISTER WITH OUTPUT REGISTER
fabricated with sub-micron silicon gate and
double-layer metal wiring C

2

MOS technology. It is
ideal for low power, battery operated and low
noise 3.3V applications.
This device contains an 8-bit serial-in, parallel-out
shift register that feeds an 8-bit D-type storage
register. Separate clocks and direct overriding
clear (SCLR,

RCLR) are provided for both the shift

Figure 1: Pin Connection An d I E C Logic Symbols

TSSOPSOP

Table 1: Order Codes

PACKAGE T & R

SOP 74LVX594MTR

TSSOP 74LVX594TTR

register and the storage register. A serial (QH’)
output is provided for cascading purposes.

Both

the shift register and storage register use
positive-edge triggered clocks. If the clocks are
connected together, the shift register state will
always be one clock pulse ahead of the storage
register.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage. This device can be
used to interface 5V to 3V system. It combines
high speed performance w ith the true CMOS low
powe r consumption.
All inputs and outputs are equipped with
protection circuits against static disc harge, giving
them 2KV ESD immunity and transient excess
voltage.

Rev. 5

1/14August 2004

74LVX594

Figure 2: Input Equivalent Circuit Table 2: Pin Description

PIN N° SYMBOL NAME AND FUNCTION

1, 2, 3, 4, 5,

6, 7, 15

9 QH’ Serial Data Output
10 SCLR
11 SCK Shift Register Clock Input
13 RCLR

14 SI Serial Data Input
12 RCK Storage Register Clock

8 GND Ground (0V)
16 V

Table 3: Truth Table

QA to QH Data Outputs

Shift Register Clear Input

Storage Register Clear
Input

Input

CC

Positive Supply Voltage

INPUTS

SI SCK SCLR RCK RCLR

X X L X X SHIFT REGISTER IS CLEAR

FIRST STAGE OF SHIFT REGISTER GOES LOW

LHXX

HHXX

L H X X SHIFT REGISTER STATE IS NOT CHANGED
X X X X L STORAGE REGISTER IS CLEARED

XXX H
X X X H STORAGE REGISTER STATE IS NOT CHANGED

X : Don’t Care

OTHER STAGES STORE THE DATA OF PREVI-

OUS STAGE, RESPECTIVELY

FIRST STAGE OF SHIFT REGISTER GOES HIGH

OTHER STAGES STORE THE DATA OF PREVI-

OUS STAGE, RESPECTIVELY

SHIFT REGISTER DATA IS STORED IN THE

OUTPUTS

STORAGE REGISTER

2/14

Figure 3: Logic Diagram

74LVX594

This logic diagram has not be used to estimate propagation delays

3/14

74LVX594

Figure 4: Timing Chart

Table 4: Absolute Maximum Ratings

Symbol Parameter Value Unit

V

V

V

I

I

OK

I

or I

I

CC

T

T

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.

4/14

Supply Voltage

CC

DC Input Voltage

I

DC Output Voltage -0.5 to VCC + 0.5

O

DC Input Diode Current

IK

DC Output Diode Current
DC Output Current

O

DC VCC or Ground Current

GND

Storage Temperature

stg

Lead Temperature (10 sec)

L

-0.5 to +7.0 V

-0.5 to +7.0 V
V

- 20 mA

± 20 mA
± 25 mA
± 50 mA

-65 to +150 °C

300 °C

74LVX594

Table 5: Recommended Operating Conditions

Symbol Parameter Value Unit

V

V
V
T

dt/dv

1) Truth T abl e guarante ed: 1.2V to 3.6V

2) V

from 0.8V to 2.0V

IN

Table 6: DC Specifications

Symbol Parameter

V

IH

V

IL

V

OH

V

OL

I

I

I

off

I

CC

Supply Voltage (note 1)

CC

Input Voltage

I

Output Voltage 0 to V

O

Operating Temperature

op

Input Rise and Fall Time (note 2) (V

= 3.3V)

CC

Test Condition Value

= 25°C

T

A

Min. Typ. Max. Min. Max. Min. Max.

High Level Input

V

CC

(V)

2.0 1.5 1.5 1.5

Voltage

3.6 2.4 2.4 2.4

Low Level Input

2.0 0.5 0.5 0.5

Voltage

3.6 0.8 0.8 0.8

High Level Output
Voltage

Low Level Output
Voltage

Input Leakage
Current

Power Off Leakage
Current

Quiescent Supply
Current

2.0

3.0

2.0

3.0

3.6

0

3.6

IO=-50 µA
I

=-50 µA

O

=-4 mA

I

O

=50 µA

I

O

=50 µA

I

O

=4 mA

I

O

= 5V or GND

V

I

= 0 to 5V

V

I

= VCC or GND

V

I

1.9 2.0 1.9 1.9

2.9 3.0 2.9 2.9

2.58 2.48 2.4

0.0 0.1 0.1 0.1

0.0 0.1 0.1 0.1

0.36 0.44 0.55

± 0.1 ± 1 ± 1 µA

± 0.1 ± 5 ± 5 µA

44040µA

2 to 3.6 V
0 to 5.5 V

CC

-55 to 125 °C
0 to 100 ns/V

-40 to 85°C -55 to 125°C

V

Unit

V3.0 2.0 2.0 2.0

V3.0 0.8 0.8 0.8

V3.0

V3.0

Table 7: Dynamic Switching Characteristics

Test Condition Value

= 25°C

Symbol Parameter

V

CC

(V)

V
V

V

V

1) Worst case package.

2) Max number of outp ut s defined as (n). Data inp ut s are driven 0V to 3.3V, (n-1) outputs switc hi ng and one out put at GND.

3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
(V

IHD

Dynamic Low Voltage

OLP

Quiet Output (note 1, 2)

OLV

Dynamic High Voltage

IHD

Input (note 1, 3)
Dynamic Low Voltage

ILD

Input (note 1, 3)

), f=1MHz.

3.3

3.3 2

= 50 pF

C

L

3.3 0.8

T

A

Min. Typ. Max. Min. Max. Min. Max.

0.3 0.5

-0.5 -0.3

-40 to 85°C -55 to 125°C

ILD

Unit

V

), 0V to thresho l d

5/14

74LVX594

Table 8: AC Electrical Characteristics (Input tr = tf = 3ns)

Test Condition Value

Symbol Parameter

t

PLH tPHL

Propagation Delay
Time
(RCK - Qn)

t

PLH tPHL

Propagation Delay
Time
(SCK - QH’)

t

t

PLH tPHL

f

t

W(H)

Propagation Delay

PHL

Time
(RCLR

Propagation Delay
Time
(SCLR

Maximum Clock

MAX

Frequency

Minimum Pulse
Width (SCK, RCK)

- Qn)

- QH’)

Minimum Pulse

t

t

REM

t

OSLH

t

OSHL

Width

W(L)

(SCLR
Minimum Set-Up

t

s

Time (SI - CCK)
Minimum Set - Up

t

s

Time (SCK, RCK)
Minimum Set - Up

t

s

Time (SCRL - RCK)
Minimum Hold

t

h

Time
Minimum Clear

Removal Time
Output To Output

Skew Time (note1,

2)

,RCLR)

V

C

CC

(V)

L

(pF)

2.7 15 5.5 9.5 1.0 10.0 1.0 10.0

2.7 50 9.0 13.0 1.0 14.5 1.0 14.5

(*)

3.3

3.3

15 4.9 8.2 1.0 8.8 1.0 8.8

(*)

50 8.1 11.9 1.0 13.1 1.0 13.1

2.7 15 6.5 11.0 1.0 12.5 1.0 12.5

2.7 50 9.2 14.0 1.0 16.0 1.0 16.0

(*)

3.3

3.3

15 5.5 9.2 1.0 9.9 1.0 9.9

(*)

50 8.4 12.5 1.0 13.9 1.0 13.9

2.7 15 7.3 11.0 1.0 13.0 1.0 13.0

2.7 50 10.5 14.5 1.0 16.0 1.0 16.0

(*)

3.3

3.3

15 6.0 9.8 1.0 10.6 1.0 10.6

(*)

50 9.0 13.1 1.0 14.4 1.0 14.4

2.7 15 6.3 10.5 1.0 12.0 1.0 12.0

2.7 50 9.0 13.5 1.0 15.5 1.0 15.5

(*)

3.3

3.3

15 5.6 9.2 1.0 10.0 1.0 10.0

(*)

50 8.5 12.4 1.0 14.0 1.0 14.0

2.7 15 70 110 60 60

2.750 40903535

(*)

3.3

3.3

15 80 120 70 70

(*)

50 55 105 50 50

2.7 50 6.5 6.5 6.5

(*)

3.3

50 5.5 5.5 5.5

2.7 50 5.0 5.0 5.0

(*)

3.3

50 5.0 5.0 5.0

2.7 50 3.5 3.5 3.5

(*)

3.3

50 3.0 3.0 3.0

2.7 50 9.0 9.0 9.0

(*)

3.3

50 85. 8.5 8.5

2.7 50 8.0 8.0 8.0

(*)

3.3

50 7.5 7.5 7.5

2.7 50 1.5 1.5 1.5

(*)

3.3

50 1.5 1.5 1.5

2.7 50 3.0 3.0 3.0

(*)

3.3

50 3.0 3.0 3.0

2.7 50 0.5 1.0 1.5 1.5

(*)

3.3

50

T

Min. Typ. Max. Min. Max. Min. Max.

= 25°C

A

-40 to 85°C -55 to 125°C

0.5 1.0 1.5 1.5

Unit

ns

ns

ns

ns

MHz

ns

ns

ns

ns

ns

ns

ns

ns

1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch­ing in the sa m e di rection, ei ther HIGH or LOW

2) Param eter guaran teed by design
(*) Voltage range is 3.3V ±

0.3V

6/14

Table 9: Capacitive Characteristics

Test Condition Value

Symbol Parameter

C

C

C

Input Capacitance

IN

Output

OUT

Capacitance
Power Dissipation

PD

Capacitance
(note 1)

V

CC

(V)

3.3 7 10 10 10 pF

3.3 9 pF

3.3

= 10MHz

f

IN

74LVX594

= 25°C

T

A

Min. Typ. Max. Min. Max. Min. Max.

55 pF

-40 to 85°C -55 to 125°C

Unit

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (R ef er to Test Circ ui t). Averag e operatin g current can be obtained by t he following equation. I

= CPD x VCC x f

CC(opr)

+ I

IN

CC

Figure 5: Test Circuit

CL =15/50pF or equivalent (i ncludes jig an d probe capac i tance)

= Z

R

of pulse generator (typically 50Ω)

T

OUT

Figure 6: Wavefo rm - Minimum Pulse Width (f=1MHz; 50% duty cycle)

7/14

74LVX594

Figure 7: Waveform - Propagation Delays, Setup And Hold Times (f=1MHz; 50% duty cycle)

8/14

SO-16 MECHANICAL DATA

74LVX594

DIM.

A 1.75 0.068
a1 0.1 0.25 0.004 0.010
a2 1.64 0.063

b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010

C 0.5 0.019
c1 45° (typ.)

D 9.8 10 0.385 0.393

E 5.8 6.2 0.228 0.244

e 1.27 0.050
e3 8.89 0.350

F 3.8 4.0 0.149 0.157

G 4.6 5.3 0.181 0.208

L 0.5 1.27 0.019 0.050

M 0.62 0.024

S8° (max.)

MIN. TYP MAX. MIN. TYP. MAX.

mm. inch

0016020D

9/14

74LVX594

TSSOP16 MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 1.2 0.047

A1 0.05 0.15 0.002 0.004 0.006

A2 0.8 1 1.05 0.031 0.039 0.041

b 0.19 0.30 0.007 0.012

c 0.09 0.20 0.004 0.0079

D 4.9 5 5.1 0.193 0.197 0.201

E 6.2 6.4 6.6 0.244 0.252 0.260

E1 4.3 4.4 4.48 0.169 0.173 0.176

e 0.65 BSC 0.0256 BSC

K0˚ 8˚0˚ 8˚

L 0.45 0.60 0.75 0.018 0.024 0.030

A2

A

A1

b

e

c

K

L

E

D

E1

PIN 1 IDENTIFICATION

10/14

1

0080338D

74LVX594

Tape & Reel SO-16 MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 330 12.992

C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 60 2.362

T 22.4 0.882

Ao 6.45 6.65 0.254 0.262
Bo 10.3 10.5 0.406 0.414
Ko 2.1 2.3 0.082 0.090
Po 3.9 4.1 0.153 0.161

P 7.9 8.1 0.311 0.319

11/14

74LVX594

Tape & Reel TSSOP16 MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 330 12.992

C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 60 2.362

T 22.4 0.882

Ao 6.7 6.9 0.264 0.272
Bo 5.3 5.5 0.209 0.217
Ko 1.6 1.8 0.063 0.071
Po 3.9 4.1 0.153 0.161

P 7.9 8.1 0.311 0.319

12/14

Table 10: Revision History

Date Revision Description of Change s

27-Aug-2004 5 Ordering Codes Revision - pag. 1.

74LVX594

13/14

74LVX594

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