Datasheet 74LVX573 Datasheet (ST)

74LVX573

LOW VOLTAGE CMOS OCTAL D-TYPE LATCH

(3-STATE NON INV.) WITH 5V TOLERANT INPUTS

■ HIGH SPEED:

t

=6.4ns (TY P.) at VCC = 3.3V

PD

■ 5V TOLERANT INPUTS

■ POWER-DOWN PROTECTION ON INPUTS

■ INPUT VOLTAGE LEVEL:

V

= 0.8V, VIH = 2V at VCC =3V

IL

■ LOW POWER DISSIPATION:

I

= 4 µA (MAX.) at TA=25°C

CC

■ LOW NOISE:

V

= 0.3V (TYP.) at VCC =3.3V

OLP

■ SYMMETRICAL OUTPUT IMPEDANCE:

|I

| = IOL = 4 mA (MIN) at VCC = 3V

OH

■ BALANCED PROPAGATION DELAYS:

t

≅ t

PLH

PHL

■ OPERATING VOLTAGE RANGE:

V

(OPR) = 2V to 3.6V (1.2V Data Retention)

CC

■ PIN AND FUNCTION COMPATIBLE WITH

74 SERIES 573

■ IMPROVED LATCH-UP IMMUNITY

DESCRIPTION

The 74LVX573 is a low voltage CMOS OCTAL
D-TYPE LATCH with 3 STATE OUTPUT NON
INVERTING fabricated with sub-micron silicon
gate and double-layer metal wiring C

2

MOS
technology. It is ideal for low power, battery
operated and low noise 3.3V applications.
This 8 bit D-Type latch is controlled by a latch
enable input (LE) and an output enable input (OE

).
While the LE in put is held at a high level, the Q
outpu ts w ill f o llow t h e d ata in put precis ely .

Figure 1: Pin C onnection And IEC Logic Symbol s

TSSOPSOP

Table 1: Order Codes

PACKAGE T & R

SOP 74LVX573MTR

TSSOP 74LVX573TTR

When the LE i s taken low, the Q outputs will be
latched precisely at the logic level of D input data.
While the (OE

) input is low, the 8 outputs will be in
a normal logic state (high or low logic level) and
while high level the outputs will be in a high
impedance state.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static disc harge, giving
them 2KV ESD immunity and transient excess
voltage.

Rev. 4

1/13August 2004

74LVX573

Figure 2: Input Equivalent Circuit Table 2: Pin Description

PIN N° SYMBOL NAME AND FUNCTION

Table 3: Truth Table

1OE

2, 3, 4, 5, 6,

D0 to D7 Data Inputs

7, 8, 9

12, 13, 14,

Q0 to Q7 3-State Latch Outputs

15, 16, 17,

18, 19

11 LE Latch Enable Input
10 GND Ground (0V)
20 V

CC

INPUTS OUTPUT

3 State Output Enable
Input (Active LOW)

Positive Supply Voltage

OE

LE D Q

HXXZ

LLXNO CHANGE*
LHLL
LHHH

X : Don’t Care
Z : High Impedance
* : Q Outputs are Latched at the time when the LE INPUT is taken low logic level

Figure 3: Logic Diagram

This logi c di agram has not be used to est i m ate propagation delays

2/13

74LVX573

Table 4: Absolute Maximum Ratings

Symbol Parameter Value Unit

V

V

V

I

I

OK

I

or I

I

CC

T

T

Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied

Table 5: Recommended Operating Conditions

Symbol Parameter Value Unit

V

V
V
T

dt/dv

1) Truth T abl e guarante ed: 1.2V to 3.6V
from 0.8V to 2.0V

2) V

IN

Table 6: DC Specifications

Supply Voltage

CC

DC Input Voltage

I

DC Output Voltage -0.5 to VCC + 0.5

O

DC Input Diode Current

IK

DC Output Diode Current
DC Output Current

O

DC VCC or Ground Current

GND

Storage Temperature

stg

Lead Temperature (10 sec)

L

Supply Voltage (note 1)

CC

Input Voltage

I

Output Voltage 0 to V

O

Operating Temperature

op

Input Rise and Fall Time (note 2) (V

CC

= 3V)

-0.5 to +7.0 V

-0.5 to +7.0 V

- 20 mA

± 20 mA
± 25 mA
± 50 mA

-65 to +150 °C
300 °C

2 to 3.6 V
0 to 5.5 V

CC

-55 to 125 °C
0 to 100 ns/V

V

V

Symbol Parameter

V

High Level Input

IH

Voltage

V

Low Level Input

IL

Voltage

V

High Level Output

OH

Voltage

V

Low Level Output

OL

Voltage

High Impedance

I

OZ

Output Leakage
Current

Input Leakage Curren t

I

I

Quiescent Supply

I

CC

Current

Test Condition Value

V

CC

(V)

T

A

Min. Typ. Max. Min. Max. Min. Max.

-40 to 85°C -55 to 125°C

= 25°C

2.0 1.5 1.5 1.5

2.0 2.0 2.0

3.6

2.4 2.4 2.4

2.0 0.5 0.5 0.5

3.6 0.8 0.8 0.8
=-50 µA

2.0

3.0

2.0

3.0

3.6

3.6

3.6

V

VO = VCC or GND

VI = 5V or GND

= VCC or GND

V

I

I

O

=-50 µA

I

O

=-4 mA

I

O

IO=50 µA

=50 µA

I

O

=4 mA

I

O

= VIH or V

I

1.9 2.0 1.9 1.9

2.9 3.0 2.9 2.9

2.58 2.48 2.4

0.0 0.1 0.1 0.1

0.0 0.1 0.1 0.1

0.36 0.44 0.55

IL

±0.25 ± 2.5 ± 2.5 µA

± 0.1 ± 1 ± 1 µA

44040µA

Unit

V3.0

V3.0 0.8 0.8 0.8

V3.0

V3.0

3/13

74LVX573

Table 7: Dynamic Switching Characteristics

Test Condition Value

= 25°C

Symbol Parameter

V
V

Dynamic Low

OLP

Voltage Quiet

OLV

Output (note 1, 2)

V

CC

(V)

3.3

T

A

Min. Typ. Max. Min. Max. Min. Max.

0.3 0.8

-0.8 -0.3

Dynamic High

V

IHD

Voltage Input

3.3 2.0

= 50 pF

C

L

(note 1, 3)
Dynamic Low

V

ILD

Voltage Input

3.3 0.8

(note 1, 3)

1) Worst case package.

2) Max number of outp ut s defined as (n). Data inp ut s are driven 0V to 3.3V, (n-1) outputs switc hi ng and one out put at GND.

3) Max number of data inputs (n) switching. (n-1) switching 0V to 3.3V. Inputs under test switching: 3.3V to threshold (V
(V

), f=1MHz.

IHD

Table 8: AC Electrical Characteristics (Input tr = tf = 3ns)

Test Condition Value

-40 to 85°C -55 to 125°C

ILD

Unit

V

), 0V to thresho l d

Symbol Parameter

t

Propagation Delay

PLH
PHL

PLH
PHL

PZL

PZH

PLZ

PHZ

t

W

t

S

t

h

Time
LE to Q

Propagation Delay
Time
D to Q

Output Enable
Time

Output Disable
Time

LE pulse Width,
HIGH

Setup Time D to LE
HIGH or LOW

Hold Time D to LE
HIGH or LOW

Output to Output
Skew Time (note
1,2)

t

t
t

t
t

t
t

t

OSLH

t

OSHL

V

(V)

CC

C

(pF)

T

L

A

Min. Typ. Max. Min. Max. Min. Max.

-40 to 85°C -55 to 125°C

= 25°C

2.7 15 8.2 15.6 1.0 18.5 1.0 18.5

2.7 50 10.7 19.1 1.0 22.0 1.0 22.0

(*)

3.3

3.3

15 6.4 10.1 1.0 12.0 1.0 12.0

(*)

50 8.9 13.6 1.0 15.5 1.0 15.5

2.7 15 7.6 14.5 1.0 17.5 1.0 17.5

2.7 50 10.1 18.0 1.0 21.0 1.0 21.0

(*)

3.3

3.3

15 5.9 9.3 1.0 11.0 1.0 11.0

(*)

50 8.4 12.8 1.0 14.5 1.0 14.5

2.7 15 7.8 15.0 1.0 18.5 1.0 18.5

2.7 50 10.3 18.5 1.0 22.0 1.0 22.0

(*)

3.3

3.3

15 6.1 9.7 1.0 12.0 1.0 12.0

(*)

50 8.6 13.2 1.0 15.5 1.0 15.5

2.7 50 12.1 19.1 1.0 22.0 1.0 22.0

(*)

3.3

50 10.1 13.6 1.0 15.5 1.0 15.5

2.7 50 6.5 7.5 7.5

(*)

3.3

50 5.0 5.0 5.0

2.7 50 5.0 5.0 5.0

(*)

3.3

50 3.5 3.5 3.5

2.7 50 1.5 1.5 1.5

(*)

3.3

50 1.5 1.5 1.5

2.7 50 0.5 1.0 1.5 1.5

(*)

3.3

50 0.5 1.0 1.5 1.5

Unit

ns

ns

ns

ns

ns

ns

ns

ns

1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch­ing in the sa m e di rection, ei ther HIGH or LOW

2) Param eter guaran teed by design
(*) Voltage range is 3.3V ±

0.3V

4/13

74LVX573

Table 9: Capacitive Characteristics

Test Condition Value

= 25°C

Symbol Parameter

C

C

C

Input Capacitance

IN

Output

OUT

Capacitance
Power Dissipation

PD

Capacitance

V

CC

(V)

3.3 4 10 10 10 pF

3.3 6 pF

= 10MHz

3.3

f

IN

T

A

Min. Typ. Max. Min. Max. Min. Max.

29 pF

(note 1)

1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I

Figure 4: Test Circuit

-40 to 85°C -55 to 125°C

= CPD x VCC x fIN + ICC/8 (per c ircuit )

CC(opr)

Unit

TEST SWITCH

t

, t

PLH

PHL

, t

t

PZL

PLZ

t

, t

PZH

PHZ

CL =15/50pF or equivalent (i ncludes jig an d probe capac i tance)

= R1 = 1KΩ or equivalen t

R

L

= Z

R

of pulse generator (typically 50Ω)

T

OUT

Open

V

CC

GND

5/13

74LVX573

Figure 5: Waveform - LE To Qn Propagation Delays, Le Minimun Pulse Width, Dn To LE Setup
And Hold Times (f=1MHz; 50% duty cycle)

Figure 6: Waveform - Output Enable And Disable Times (f=1MHz; 50% duty cycle)

6/13

Figure 7: Waveform - Propagation Delay Time (f=1MHz; 50% duty cycle)

74LVX573

7/13

74LVX573

SO-20 MECHANICAL DATA

DIM.

A 2.35 2.65 0.093 0.104

A1 0.1 0.30 0.004 0.012

B 0.33 0.51 0.013 0.020
C 0.23 0.32 0.009 0.013
D 12.60 13.00 0.496 0.512
E 7.4 7.6 0.291 0.299
e 1.27 0.050
H 10.00 10.65 0.394 0.419
h 0.25 0.75 0.010 0.030
L 0.4 1.27 0.016 0.050
k0° 8° 0° 8°

ddd 0.100 0.004

MIN. TYP MAX. MIN. TYP. M AX.

mm. inch

8/13

0016022D

74LVX573

TSSOP20 MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 1.2 0.047

A1 0.05 0.15 0.002 0.004 0.006

A2 0.8 1 1.05 0.031 0.039 0.041

b 0.19 0.30 0.007 0.012

c 0.09 0.20 0.004 0.0079

D 6.4 6.5 6.6 0.252 0.256 0.260

E 6.2 6.4 6.6 0.244 0.252 0.260

E1 4.3 4.4 4.48 0.169 0.173 0.176

e 0.65 BSC 0.0256 BSC

K0˚ 8˚0˚ 8˚

L 0.45 0.60 0.75 0.018 0.024 0.030

A2

A

A1

b

e

K

c

L

E

D

E1

PIN 1 IDENTIFICATION

1

0087225C

9/13

74LVX573

Tape & Reel SO-20 MECHANICAL

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 330 12.992
C 12.8 13.2 0.504 0.519
D 20.2 0.795
N 60 2.362

T 30.4 1.197
Ao 10.8 11 0.425 0.433
Bo 13.2 13.4 0.520 0.528
Ko 3.1 3.3 0.122 0.130
Po 3.9 4.1 0.153 0.161

P 11.9 12.1 0.468 0.476

DATA

10/13

74LVX573

Tape & Reel TSSOP20 MECHANICAL DATA

mm. inch

DIM.

MIN. TYP MAX. MIN. TYP. MAX.

A 330 12.992

C 12.8 13.2 0.504 0.519

D 20.2 0.795

N 60 2.362

T 22.4 0.882
Ao 6.8 7 0.268 0.276
Bo 6.9 7.1 0.272 0.280
Ko 1.7 1.9 0.067 0.075
Po 3.9 4.1 0.153 0.161

P 11.9 12.1 0.468 0.476

11/13

74LVX573

Table 10: Revision History

Date Revisio n Description of Changes

27-Aug-2004 4 Ordering Codes Revision - pag. 1.

12/13

74LVX573

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