The 74LVX257 i s a low voltage CMOS QUAD 2
CHANNEL MULTIPLEXER (3-STATE) fabricated
with sub-micron silicon gate and double-layer
metal wiring C
2
MOS technology. It is ideal for low
power, battery operated and low noise 3.3V
applications.
It is composed of four independent 2-channel
multiplexers with common SELECT and ENA BLE
(OE
) INPUT. The 74LVX257 is a non-inverting
TSSOPSOP
Table 1: Order Codes
PACKAGET & R
SOP74LVX257MTR
TSSOP74LVX257TTR
multiplexer. When the ENABLE INPUT is held
"High", all outputs become in high impedance
state. If SELECT INPUT is held "Low", "A" dat a is
selected, when SELECT INPUT is "High", "B" data
is chosen.
Power down protection is provided on all inputs
and 0 to 7V can be accepted on inputs with no
regard to the supply voltage.
This device can be used to interface 5V to 3V. It
combines high speed performance with the true
CMOS low power consumption.
All inputs and outputs are equipped with
protection circuits against static disc harge, giving
them 2KV ESD immunity and transient excess
voltage.
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switching in the sa m e di rection, ei ther HIGH or LOW
2) Param eter guaran teed by design
(*) Voltage range is 3.3V ±
Time
PHL
A, B, to Y
Propagation Delay
PLH
Time
PHL
SELECT to Y
Output Enable
PZL
Time
PZH
Output Disable
PLZ
Time
PHZ
Output to Output
Skew Time (note
1,2)
0.3V
V
C
CC
(V)
L
(pF)
2.7157.013.01.015.41.016.4
2.7509.518.01.020.31.021.3
(*)
3.3
3.3
155.89.31.011.01.012.0
(*)
508.312.81.014.51.015.5
2.7158.515.41.018.21.020.0
2.75010.520.31.023.11.024.5
(*)
3.3
3.3
157.011.01.013.01.014.0
(*)
509.514.51.016.51.018.0
2.7158.014.71.017.51.018.5
2.75010.519.61.022.41.024.0
(*)
3.3
3.3
156.710.51.012.51.013.5
(*)
509.214.01.016.01.017.0
2.7509.516.81.018.91.020.0
(*)
3.3
508.612.01.013.51.015.0
2.7500.51.01.51.5
(*)
3.3
500.51.01.51.5
T
A
-40 to 85°C -55 to 125°C
Min.Typ. Max.Min.Max. Min. Max.
Unit
ns
ns
ns
ns
ns
4/13
Page 5
Table 9: Capacitive Characteristics
Test ConditionValue
SymbolParameter
C
C
C
Input Capacitance
IN
Output
OUT
Capacitance
Power Dissipation
PD
Capacitance
(note 1)
V
CC
(V)
3.34101010pF
3.36pF
3.323pF
74LVX257
= 25°C
T
A
Min.Typ. Max.Min.Max. Min. Max.
-40 to 85°C -55 to 125°C
Unit
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (R ef er to Test Circ ui t). Averag e operatin g current can be obtained by t he following equation. I
channel)
= CPD x VCC x fIN + ICC/4 (per
CC(opr)
Figure 4: Test Circuit
TESTSWITCH
, t
t
PLH
t
PZL
t
PZH
PHL
, t
PLZ
, t
PHZ
Open
V
CC
GND
CL =15/50pF or equivalent (i ncludes jig an d probe capac i tance)
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