Datasheet 74LVT543PW, 74LVT543DB, 74LVT543D Datasheet (Philips)

INTEGRATED CIRCUITS

74LVT543

3.3V Octal latched transceiver with
dual enable (3-State)

Product specification
Supersedes data of 1994 May 20
IC23 Data Handbook

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1998 Feb 19

Philips Semiconductors Product specification

3.3V Octal latched transceiver with dual enable
(3-State)

FEA TURES

•Combines 74L VT245 and 74LVT373 type functions in one device

•8-bit octal transceiver with D-type latch

•Back-to-back registers for storage

•Separate controls for data flow in each direction

•Output capability: +64mA/–32mA

•TTL input and output switching levels

•Input and output interface capability to systems at 5V supply

•Bus-hold data inputs eliminate the need for external pull-up

resistors to hold unused inputs

•Live insertion/extraction permitted

•No bus current loading when output is tied to 5V bus

•Power-up 3-State

•Power-up reset

•Latch-up protection exceeds 500mA per JEDEC Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015

and 200V per Machine Model

DESCRIPTION

The 74LVT543 is a high-performance BiCMOS product designed for
V

operation at 3.3V .

CC

This device contains two sets of D-type latches for temporary
storage of data flowing in either direction. Separate Latch Enable
(LEAB

, LEBA) and Output Enable (OEAB, OEBA) inputs are
provided for each register to permit independent control of data
transfer in either direction. The outputs are guaranteed to sink
64mA.

FUNCTIONAL DESCRIPTION

The 74LVT543 contains two sets of eight D–type latches, with
separate control pins for each set. Using data flow from A to B as an
example, when the A-to-B Enable (EAB
Enable (LEAB
subsequent Low-to-High transition of the LEAB
data into the latches where it is stored and the B outputs no longer
change with the A inputs. With EAB
3-State B output buffers are active and display the data present at
the outputs of the A latches.

Control of data flow from B to A is similar, but using the EBA
and OEBA

74L VT543

) input and the A-to-B Latch

) input are Low the A-to-B path is transparent. A

signal puts the A

and OEAB both Low, the

, LEBA,

inputs.

QUICK REFERENCE DATA

SYMBOL PARAMETER

t

PLH

t

PHL

C
C
I

CCZ

IN

I/O

Propagation delay
An to Bn or Bn to An

Input capacitance VI = 0V or 3.0V 4 pF
I/O capacitance Outputs disabled; V
Total supply current Outputs disabled; VCC = 3.6V 0.13 mA

CL = 50pF;
VCC = 3.3V

CONDITIONS

T

= 25°C; GND = 0V

amb

I/O

TYPICAL UNIT

2.3

3.0

= 0V or 3.0V 10 pF

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

24-Pin Plastic SOL –40°C to +85°C 74LVT543 D 74LVT543 D SOT137-1
24-Pin Plastic SSOP Type II –40°C to +85°C 74LVT543 DB 74LVT543 DB SOT340-1
24-Pin Plastic TSSOP Type I –40°C to +85°C 74LVT543 PW 74LVT543PW DH SOT355-1

PIN CONFIGURATION

1

LEBA

2

OEBA

3

A0

4

A1

5

A2

6

A3

7

A4

8

A5

9

A6

10 15

A7

11

EAB

12 13

GND

24

V

23

EBA

22

B0

21

B1

20

B2

19

B3

18

B4

17

B5

16

B6
B7

14

LEAB
OEAB

SV00026

CC

LOGIC SYMBOL

11
23
14 LEAB

1 LEBA

3456

A0 A1 A2 A3
EAB

EBA

B0 B1 B2

B3

2122

1920

78910

A4 A5 A6 A7

B4 B5 B6

B7

1718

1516

13OEAB
2OEBA

SV00027

ns

1998 Feb 19 853-1749 18988

2

Philips Semiconductors Product specification

STATUS

3.3V Octal latched transceiver with dual enable
(3-State)

LOGIC SYMBOL (IEEE/IEC)

2

1EN3

23

G1

1

IC5

13

ZEN4 (AB)

11

GZ.

14

ZC6

3 22

V3 5D

6D

421

520

619

718

817

916

10 15

2V

SV00028

LOGIC DIAGRAM

OEBA

EBA

LEBA

74LVT543

DETAIL A

DLEQ

3

A0

4

A1

5

A2

6

A3

7

A4

8

A5

9

A6

10

A7

2

23

1

DETAIL A X 7

D

Q

LE

22

B0

21

B1

20

B2

19

B3

18

B4

17

B5

16

B6

15

B7

13

OEAB

11

EAB

14

LEAB

SV00029

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

14, 1 LEAB / LEBA A to B / B to A Latch Enable input (active-Low)

11, 23 EAB / EBA A to B / B to A Enable input (active-Low)

13, 2 OEAB / OEBA A to B / B to A Output Enable input (active-Low)

3, 4, 5, 6, 7, 8, 9, 10 A0 – A7 Port A, 3-State outputs

22, 21, 20, 19, 18, 17, 16, 15 B0 – B7 Port B, 3-State outputs

12 GND Ground (0V)
24 V

CC

Positive supply voltage

FUNCTION TABLE

INPUTS OUTPUTS

OEXX EXX LEXX An or Bn Bn or An

H X X X Z Disabled
X H X X Z Disabled

L
L

L
L

L
L

L L H X NC Hold

H = High voltage level
h = High voltage level one set-up time prior to the Low-to-High

transition of LEXX
L = Low voltage level
l = Low voltage level one set-up time prior to the Low-to-High

transition of LEXX or EXX (XX = AB or BA)

↑
↑

L
L

L
L

L
L

↑
↑

L
L

or EXX (XX = AB or BA)

h

l

h

l

H

L

Z
Z

H

L

H

L

X = Don’t care
↑ = Low-to-High transition of LEXX
NC= No change
Z = High impedance or “off” state

Disabled + Latch

Latch + Display

Transparent

or EXX (XX = AB or BA)

1998 Feb 19

3

Philips Semiconductors Product specification

I

DC output current

mA

SYMBOL

PARAMETER

UNIT

I

mA

3.3V Octal latched transceiver with dual enable
(3-State)

ABSOLUTE MAXIMUM RATINGS

SYMBOL

V

V

I
V

I

OK

OUT

OUT

T

CC

IK

stg

DC supply voltage –0.5 to +4.6 V
DC input diode current VI < 0 –50 mA
DC input voltage

I

DC output diode current VO < 0 –50 mA
DC output voltage

p

Storage temperature range –65 to 150 °C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create ju nction

temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

PARAMETER CONDITIONS RATING UNIT

3

3

1, 2

–0.5 to +7.0 V

Output in Off or High state –0.5 to +7.0 V

Output in Low state 128

Output in High state –64

74LVT543

RECOMMENDED OPERATING CONDITIONS

LIMITS

MIN MAX

V

CC

V
V
V
I

OH

OL

∆t/∆v Input transition rise or fall rate; outputs enabled 10 ns/V

T

amb

DC supply voltage 2.7 3.6 V
Input voltage 0 5.5 V

I

High-level input voltage 2.0 V

IH

Low-level input voltage 0.8 V

IL

High-level output current –32 mA
Low-level output current 32
Low-level output current; current duty cycle ≤ 50%; f ≥ 1kHz 64

Operating free-air temperature range –40 +85 °C

1998 Feb 19

4

Philips Semiconductors Product specification

Control pi

6

3.3V Octal latched transceiver with dual enable
(3-State)

DC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT

MIN TYP1MAX

V

V

V

V

I

OFF

I

HOLD

I

I

PU/PD

I

CCH

I

CCL

I

CCZ

∆I

NOTES:

1. All typical values are at V

2. This is the increase in supply current for each input at the specified voltage level other than V

3. This parameter is valid for any V
transition time of 100µsec is permitted. This parameter is valid for T

4. Unused pins at V

5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

6. This is the bus hold overdrive current required to force the input to the opposite logic state.

Input clamp voltage VCC = 2.7V; IIK = –18mA –0.9 –1.2 V

IK

VCC = 2.7 to 3.6V; IOH = –100µA VCC-0.2 VCC-0.1

High-level output voltage VCC = 2.7V; IOH = –8mA 2.4 2.5 V

OH

VCC = 3.0V; IOH = –32mA 2.0 2.2
VCC = 2.7V; IOL = 100µA 0.1 0.2
VCC = 2.7V; IOL = 24mA 0.3 0.5

Low-level output voltage VCC = 3.0V; IOL = 16mA 0.25 0.4 V

OL

VCC = 3.0V; IOL = 32mA 0.3 0.5
VCC = 3.0V; IOL = 64mA 0.4 0.55

Power-up output low voltage5VCC = 3.6V; IO = 1mA; VI = GND or V

RST

VCC = 3.6V; VI = VCC or GND
VCC = 0 or 3.6V; VI = 5.5V

I

Input leakage current VCC = 3.6V; VI = 5.5V 1 20 µA

I

VCC = 3.6V; VI = V

CC

CC

I/O Data pins

ns

4

VCC = 3.6V; VI = 0 –1 -5

Output off current VCC = 0V; VI or VO = 0 to 4.5V 1 ±100 µA

VCC = 3V; VI = 0.8V 75 150

Bus Hold current A inputs

VCC = 3V; VI = 2.0V –75 –150
VCC = 0V to 3.6V; VCC = 3.6V ±500

Current into an output in the

EX

High state when VO > V
Power up/down 3-State output

3

current

CC

Quiescent supply current VCC = 3.6V; Outputs Low, VI = GND or V

Additional supply current per

CC

input pin

2

or GND.

CC

= 3.3V and T

CC

CC

VO = 5.5V; VCC = 3.0V 60 125 µA

VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC;
OE/OE = Don’t care

VCC = 3.6V; Outputs High, VI = GND or V

VCC = 3.6V; Outputs Disabled; VI = GND or V
VCC = 3V to 3.6V; One input at V

Other inputs at VCC or GND

= 25°C.

amb

CC

-0.6V,

between 0V and 1.2V with a transition time of up to 10msec. From V

= 25°C only.

amb

I

0 0.13 0.19

CC,

O =

I

0 3 12 mA

CC,

O =

I

0 0.13 0.19

CC,

O =

or GND

CC

= 1.2V to VCC = 3.3V ± 0.3V a

CC

74LVT543

LIMITS

0.13 0.55 V
±0.1 ±1

1 10

0.1 1

15 ±100 µA

0.1 0.2 mA

µA

1998 Feb 19

5

Philips Semiconductors Product specification

3.3V Octal latched transceiver with dual enable
(3-State)

AC CHARACTERISTICS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω; T

SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V UNIT

t

PLH

t

PHL

t

PLH

t

PHL

t

PZH

t

t

PHZ

t

t

PZH

t

t

PHZ

t

PZL

PLZ

PZL

PLZ

Propagation delay
An to Bn, Bn to An

Propagation delay
LEBA to An, LEAB to Bn

Output enable time
OEBA to An, OEAB to Bn

Output disable time
OEBA

to An, OEAB to Bn

Output enable time
EBA to An, EAB to Bn

Output disable time
EBA to An, EAB to Bn

NOTE:

1. All typical values are at V

= 3.3V and T

CC

amb

= –40°C to +85°C.

amb

= 25°C.

LIMITS

2.3

3.0

3.6

4.2

3.8

3.8

3.7

3.5

4.0

4.1

3.7

3.5

1

MAX MAX

4.7

4.6

5.9

5.7

5.8

6.4

6.5

5.8

6.0

6.7

6.4

5.4

MIN TYP

2
1

2
4

5
4

5
4

5
4

5

1.0

1.0

1.0

1.0

1.0

1.1

2.4

2.0

1.0

1.4

2.3

2.0

74LVT543

5.5

5.8

7.3

7.3

7.6

8.2

7.1

5.9

7.6

8.3

7.1

5.6

ns

ns

ns

ns

ns

ns

AC SETUP REQUIREMENTS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω; T

SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V UNIT

ts(H)
ts(L)

th(H)
th(L)

ts(H)
ts(L)

th(H)
t

(L)

h

Setup time
An to LEAB, Bn to LEBA

Hold time
An to LEAB, Bn to LEBA

Setup time
An to EAB, Bn to EBA

Hold time
An to EAB

, Bn to EBA

tw(L) Latch enable pulse width, Low 3 3.3 3.3 ns

= –40°C to +85°C.

amb

LIMITS

MIN MAX MIN

3

3

3

3

0

0.8

1.7

1.7
0

0.9

1.8

1.8

0

1.1

1.7

1.7
0

1.2

1.8

1.8

AC WAVEFORMS

VM = 1.5V, VIN = GND to 2.7V

V

V

OUT

2.7V

IN

1.5V

t

PHL

1.5V

t

PLH

1.5V 1.5V

0V

V

OH

V

OL

V

V

OUT

IN

t

PLH

1.5V1.5V

t

PHL

1.5V1.5V

2.7V

0V

V

V

ns

ns

ns

ns

OH

OL

Waveform 1. Propagation Delay For Inverting Output

1998 Feb 19

SV00030

SV00113

Waveform 2. Propagation Delay For Non-Inverting Output

6

Philips Semiconductors Product specification

3.3V Octal latched transceiver with dual enable
(3-State)

An,
Bn

LEAB, LEBA,
EAB, EBA

1.5V 1.5V 1.5V 1.5V

ts(H)

t

(H)

h

(L)

t

s

tw(L)

1.5V1.5V

NOTE: The shaded areas indicate when the input is permitted

to change for predictable output performance.

Waveform 3. Data Setup and Hold Times And Latch Enable

Pulse Width

OEAB, OEBA,
EAB, EBA

An, Bn

t

PZH

1.5V

1.5V1.5V

t

PHZ

2.7V

OEAB, OEBA,

0V

t

(L)

h

2.7V

EAB, EBA

An, Bn

0V

Waveform 5. 3-State Output Enable Time to Low Level

SV00114

2.7V

0V

V

OH

–0.3V

V

OH

0V

74LVT543

1.5V 1.5V

t

PZL

1.5V

and Output Disable Time from Low Level

t

PLZ

2.7V

0V

3.0V

VOL+0.3V

V

SV00116

OL

Waveform 4. 3-State Output Enable Time to High Level

and Output Disable Time from High Level

TEST CIRCUIT AND WAVEFORM

V

CC

PULSE

GENERATOR

V

IN

D.U.T.

R

T

V

OUT

C

L

Test Circuit for 3-State Outputs

SWITCH POSITION

TEST SWITCH

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

DEFINITIONS

RL = Load resistor; see AC CHARACTERISTICS for value.

= Load capacitance includes jig and probe capacitance;

C

L

see AC CHARACTERISTICS for value.

R

= Termination resistance should be equal to Z

T

pulse generators.

Open

6V

GND

SV00115

R

R

OUT

6.0V

t

Open

GND

L

L

90%

NEGATIVE
PULSE

POSITIVE
PULSE

10%

V

M

10% 10%

t

THL

t

TLH

90% 90%

V

M

W

V

M

(tF)

(tR)t

V

M

t

W

90%

10%

t

TLH

THL

AMP (V)

0V

(tR)

(tF)

AMP (V)

0V

VM = 1.5V

Input Pulse Definition

INPUT PULSE REQUIREMENTS

FAMILY

74LVT

Amplitude Rep. Rate t

2.7V 10MHz 500ns 2.5ns 2.5ns

t

W

t

R

F

of

SV00092

1998 Feb 19

7

Philips Semiconductors Product specification

3.3V Octal latched transceiver with dual enable
(3-State)

SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

74LVT543

1998 Feb 19

8

Philips Semiconductors Product specification

3.3V Octal latched transceiver with dual enable
(3-State)

SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm SOT340-1

74LVT543

1998 Feb 19

9

Philips Semiconductors Product specification

3.3V Octal latched transceiver with dual enable
(3-State)

TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm SOT355-1

74LVT543

1998 Feb 19

10

Philips Semiconductors Product specification

3.3V Octal latched transceiver with dual enable
(3-State)

NOTES

74LVT543

1998 Feb 19

11

Philips Semiconductors Product specification

3.3V Octal latched transceiver with dual enable
(3-State)

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

74LVT543

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1998

All rights reserved. Printed in U.S.A.

print code Date of release: 05-96
Document order number: 9397-750-03537

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