Datasheet 74LVT373 Datasheet (Philips)

Philips Semiconductors Low Voltage Products Objective specification

74LVT3733.3 Volt ABT octal transparent latch (3–State)

2

July 1993

FEATURES

•Designed for use in the 3.3V

high–performance market

•Supports mixed–mode signal operation; 5V

input and output voltages with 3.3V V

CC

•Bus–hold inputs eliminate the need for

external pull-up resistors to hold unused pins

•Live insertion/extraction permitted

•No bus current loading when output is tied

to 5V bus

•8–bit transparent latch

•3-State output buffers

•Zero-static power dissipation

•Pin and function compatibility with ABT

•AC and DC performance compatibility with

ABT

•Latch–up protection exceeds 500mA per

JEDEC JC40.2 Std 17

•ESD protection exceeds 2000 V per MIL

STD 883 Method 3015 and 200 V per Machine Model

DESCRIPTION

The 74LVT373 device is designed specifically for low–voltage (3.3V) V

CC

operation, but can provide a TTL interface to a 5V system environment.

The 74LVT373 high-performance BiCMOS device combines zero static and low dynamic power dissipation with high speed and high output drive.

The 74LVT373 device is an octal transparent latch coupled to eight 3-State output buffers. The two sections of the device are controlled

independently by Enable (E) and Output Enable (OE

) control gates.

The data on the D inputs are transferred to the latch outputs when the Latch Enable (E) input is High. The latch remains transparent to the data inputs while E is High, and stores the data that is present one setup time before the High-to-Low enable transition.

The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE

) controls all eight 3-State buffers independent of the latch operation.

When OE

is Low, the latched or transparent

data appears at the outputs. When OE

is High, the outputs are in the High-impedance ”OFF” state, which means they will neither drive nor load the bus.

QUICK REFERENCE DATA

SYMBOL PARAMETER

CONDITIONS

T

amb

= 25°C; GND = 0V

TYPICAL UNIT

t

PLH

t

PHL

Propagation delay Dn to Qn

CL = 50pF; VCC = 5V 4.2 ns

C

IN

Input capacitance VI = 0V or V

CC

4 pF

C

OUT

Output capacitance VI = 0V or V

CC

7 pF

I

CCZ

Total supply current Outputs disabled; VCC =5.5V 50 µA

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE ORDER CODE DRAWING NUMBER

20–Pin Plastic SOL -40°C to +85°C 74LVT373D 0172D 20–Pin Plastic SSOP -40°C to +85°C 74LVT373DB 1640B 20–Pin Plastic TSSOP -40°C to +85°C 74LVT373PW TBD

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

1 OE Output enable input (active-Low) 3, 4, 7, 8, 13, 14, 17, 18 D0-D7 Data inputs 2, 5, 6, 9, 12, 15, 16, 19 Q0-Q7 Data outputs

11 E Enable input (active-High) 10 GND Ground (0V) 20 V

CC

Positive supply voltage

Philips Semiconductors Low Voltage Products Objective specification

74LVT3733.3 Volt ABT octal transparent latch (3–State)

July 1993

3

FUNCTION TABLE

INPUTS INTERNAL OUTPUTS OPERATING MODE

OE E Dn

REGISTER Q0 – Q7

L L

H H

L

H

L

H

L

H

Enable and read register

L L

↓ ↓

i

h

L

H

L

H

Latch and read register

L L X NC NC Hold

H H

L

H

X

Dn

NC

Dn

Z Z

Disable outputs

H = High voltage level h = High voltage level one set-up time prior to the High-to-Low E transition L = Low voltage level l = Low voltage level one set-up time prior to the High-to-Low E transition NC= No change X = Don’t care Z = High impedance “off” state ↓ = High-to-Low E transition

LOGIC DIAGRAM

E Q

D

3

D0

Q0

E Q

D

4

D1

E Q

D

7

D2

E Q

D

8

D3

E Q

D

13

D4

E Q

D

14

D5

E Q

D

17

D6

E Q

D

18

D7

2

Q1

5

Q2

6

Q3

9

Q4

12

Q5

15

Q6

16

Q7

19

11

E

1

OE

Philips Semiconductors Low Voltage Products Objective specification

74LVT3733.3 Volt ABT octal transparent latch (3–State)

July 1993

4

ABSOLUTE MAXIMUM RATINGS

1, 2

SYMBOL

PARAMETER CONDITIONS RATING UNIT

V

CC

DC supply voltage –0.5 to +4.6 V

I

IK

DC input diode current VI < 0 –18 mA

V

I

DC input voltage

3

–1.2 to +5.5 V

I

OK

DC output diode current VO < 0 –50 mA

V

OUT

DC output voltage

3

output in Off or High state –0.5 to +5.5 V

I

OUT

DC output current output in Low state 64 mA

T

stg

Storage temperature range –65 to 150 °C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

2. The performance capability of a high–performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER LIMITS UNIT

Min Max

V

CC

DC supply voltage 2.7 3.6 V

V

I

Input voltage 0 V

CC

V

IH

High-level input voltage 2.0 V

V

IL

Input voltage 0.8 V

I

OH

High-level output current –32 mA

I

OL

Low-level output current 64 mA

∆t/∆v Input transition rise or fall rate 0 10 ns/V

T

amb

Operating free-air temperature range 0 +70 °C

Philips Semiconductors Low Voltage Products Objective specification

74LVT3733.3 Volt ABT octal transparent latch (3–State)

July 1993

5

DC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT

MIN TYP1MAX

V

IK

Input clamp voltage VCC = 2.7V; IIK = –18mA –1.2 V

VCC = 2.7 to 3.6V; IOH = –100µA VCC-0.2

V

OH

High-level output voltage VCC = 2.7V; IOH = –8mA 2.4 V

VCC = 3.0V; IOH = –32mA 2.0 VCC = 2.7V; IOL = 100µA 0.2 VCC = 2.7V; IOL = 24mA 0.5

V

OL

Low-level output voltage VCC = 3.0V; IOL = 16mA 0.4 V

VCC = 3.0V; IOL = 32mA 0.5 VCC = 3.0V; IOL = 64mA 0.55 VCC = 3.6V; VI = VCC or GND Control pins ±1

VCC = 0 or 3.6V; VI = 5.5V 10

I

Input leakage current VCC = 3.6V; VI = 5.5V 20 µA

VCC = 3.6V; VI = V

CC

Data pins

4

1

VCC = 3.6V; VI = 0 -5

I

OFF

Output off current VCC = 0V; VI or VO = 0 to 4.5V ±100 µA

I

HOLD

Bus Hold current A VCC = 3V; VI = 0.8V 75 µA or B ports VCC = 3V; VI = 2.0V –75 µA

I

EX

Current into an ouptut in the High state when V

O

> V

CC

VO = 5.5V; VCC = 3.0V 100 µA

I

CCH

VCC = 3.6V; Outputs High, VI = GND or V

CC,

I

O =

0 0.13 0.19

I

CCL

Quiescent supply current VCC = 3.6V; Outputs Low, VI = GND or V

CC,

I

O =

0 3 12 mA

I

CCZ

VCC = 3.6V; Outputs Disabled; VI = GND or V

CC,

I

O =

0 0.13 0.19

∆I

CC

Additional supply current per input pin

2

VCC = 3V to 3.6V; One input at VCC-0.6V, Other inputs at VCC or GND

0.2 mA

I

PU/PD

Power up/down 3-State output current

3

VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC; OE/OE = X

±100 µA

C

I

Input capacitance VI = 3V or 0 4 pF

C

O

Output capacitance VO = 3V or 0 11 pF

NOTES:

1. All typical values are at V

CC

= 3.3V and T

amb

= 25°C.

2. This is the increase in supply current for each input at the specificed voltage level other than VCC or GND

3. This parameter is valid for any V

CC

between 0V and 1.3V with a transition time of up to 10msec. From V

CC

= 1.3V to VCC = 3.3V ± 0.3V a

transition time of 100µsec is permitted. X = Don’t care.

4. Unused pins at V

CC

or GND.

Philips Semiconductors Low Voltage Products Objective specification

74LVT3733.3 Volt ABT octal transparent latch (3–State)

July 1993

6

AC CHARACTERISTICS

GND = 0V; tR = tF = 6ns; CL = 50pF; RL = 500Ω, T

amb

= –40°C to +85°C.

LIMITS

SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V UNIT

MIN TYP

1

MAX MAX

t

PLH

t

PHL

Propagation delay An to Yn

NO TAG

2.7

2.9

ns

t

PZH

t

PZL

Output enable time OE

n to Yn

NO TAG

3.4

ns

t

PHZ

t

PLZ

Output disable time OE

n to Yn

NO TAG

3.7

2.6

ns

NOTE:

1. All typical values are at V

CC

= 3.3V and T

amb

= 25°C.

AC WAVEFORMS

VM = 1.5V, VIN = GND to 3.0V

NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.

V

M

V

M

Waveform 1. Propagation Delay, Enable to

Output, and Enable Pulse Width

V

M

V

M

V

M

tw(H)

t

PHL

t

PLH

E

Qn

V

M

Dn

V

M

V

M

V

M

V

MVM

E

Waveform 3. Data Setup and Hold Times

ts(H)

t

h

(H)

t

s

(L)

t

h

(L)

OE

V

M

t

PZH

t

PHZ

0V

V

OH

–0.3V

Qn

Waveform 4. 3-State Output Enable Time to High Level

and Output Disable Time from High Level

OE

t

PZL

t

PLZ

0V

V

OL

+0.3V

Qn

Waveform 5. 3-State Output Enable Time to Low Level

and Output Disable Time from Low Level

V

M

V

M

V

M

V

M

V

M

Dn

V

M

t

PLH

t

PHL

Qn

Waveform 2. Propagation Delay for Data

to Outputs

V

M

V

M

V

M

Philips Semiconductors Low Voltage Products Objective specification

74LVT3733.3 Volt ABT octal transparent latch (3–State)

July 1993

7

TEST CIRCUIT AND WAVEFORM

PULSE

GENERATOR

R

T

V

IN

D.U.T

V

OUT

C

L

R

L

V

CC

R

L

OPEN

Test Circuit for 3-State Outputs

V

M

V

M

t

W

AMP (V)

NEGATIVE PULSE

10% 10%

90%

0V

V

M

V

M

t

W

AMP (V)

POSITIVE PULSE

90% 90%

10%

0V

t

THL

(tF)

t

TLH

(tR) t

THL

(tF)

t

TLH

(tR)

VM = 1.5V

Input Pulse Definition

DEFINITIONS

RL = Load resistor; see AC CHARACTERISTICS for value. C

L

= Load capacitance includes jig and probe capacitance;

see AC CHARACTERISTICS for value.

RT = Termination resistance should be equal to Z

OUT

of

pulse generators.

INPUT PULSE REQUIREMENTS

FAMILY

Amplitude Rep. Rate t

W

t

R

t

F

74LVT VCC(Min) ≤1MHz 500ns ≤2.5ns ≤2.5ns

SWITCH POSITION

TEST SWITCH

t

PHZ/tPZH

GND

t

PLZ/tPZL

6V

t

PLH/tPHL

open

GND

6V