Datasheet 74LVT534PW, 74LVT534DB, 74LVT534D Datasheet (Philips)

Page 1
INTEGRATED CIRCUITS
74LVT534
3.3V Octal D-type flip-flop; inverting (3-State)
Product specification Supersedes data of 1996 Aug 13 IC23 Data Handbook
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Page 2
Philips Semiconductors Product specification
74L VT5343.3V Octal D-type flip-flop, inverting (3-State)
FEA TURES
3-State outputs for bus interfacing
Common output enable
TTL input and output switching levels
Input and output interface capability to systems at 5V supply
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
Live insertion/extraction permitted
No bus current loading when output is tied to 5V bus
Power-up 3-State
Power-up reset
Latch-up protection exceeds 500mA per JEDEC Std 17
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL PARAMETER
C
t
PLH
t
PHL
C
OUT
I
CCZ
IN
Propagation delay CP to Qn
Input capacitance VI = 0V or 3.0V 4 pF Output capacitance
Total supply current
DESCRIPTION
The LVT534 is a high-performance BiCMOS product designed for V
operation at 3.3V .
CC
This device is an 8-bit, edge triggered register coupled to eight 3-State output buffers. The two sections of the device are controlled independently by the clock (CP) and Output Enable (OE gates. The state of each D input (one set-up time before the Low-to-High clock transition) is transferred to the corresponding flip-flop’s Q output.
The 3-State output buffers are designed to drive heavily loaded 3-State buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE independent of the clock operation.
When OE is Low, the stored data appears at the outputs. When OE is High, the outputs are in the High-impedance “off” state, which means they will neither drive nor load the bus.
CONDITIONS
T
= 25°C; GND = 0V
amb
CL = 50pF; VCC = 3.3V
Outputs disabled; V
= 0V or 3.0V
I/O
Outputs disabled; VCC = 3.6V
) control
) controls all eight 3-State buffers
TYPICAL UNIT
3.0
3.5
ns
7 pF
0.13 mA
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER
20-Pin Plastic SOL –40°C to +85°C 74LVT534 D 74LVT534 D SOT163-1 20-Pin Plastic SSOP Type II –40°C to +85°C 74LVT534 DB 74LVT534 DB SOT339-1 20-Pin Plastic TSSOP Type I –40°C to +85°C 74LVT534 PW 74LVT534PW DH SOT360-1
PIN CONFIGURATION
1
OE
2
Q0
3
D0
4
D1
5
1
Q
6
Q2
7
D2
8
D3
9
Q
3
GND
10 11
20 19 18 17 16 15 14 13 12
SA00161
V Q7 D7 D6 Q Q5 D5 D4 Q
CP
CC
6
4
LOGIC SYMBOL
11
1
3478
D0 D1 D2 D3
CP
OE
Q0 Q1 Q296Q3
52
13 14 17 18
D4 D5 D6 D7
Q4 Q5 Q6
1512
SA00162
Q7
1916
1998 Feb 19 853-1855 18988
2
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Philips Semiconductors Product specification
74LVT5343.3V Octal D-type flip-flop, inverting (3-State)
LOGIC SYMBOL (IEEE/IEC)
1
EN
11
13
14
17
18
C1
3
1D
4
7
8
2
5
6
9
12
15
16
19
SA00163
FUNCTION TABLE
INPUTS INTERNAL OUTPUTS
OE CP Dn REGISTER Q0 – Q7
LL↑
L X NC NC Hold
HH↑
↑XDn
l
h
H
NC
Dn
L
H
L
Z Z
OPERATING
MODE
Latch and read register
Disable outputs
PIN DESCRIPTION
PIN NUMBER SYMBOL FUNCTION
1 OE Output enable input (active-Low)
3, 4, 7, 8,
13, 14, 17, 18
2, 5, 6, 9,
12, 15, 16, 19
11 CP 10 GND Ground (0V)
20 V
H = High voltage level h = High voltage level one set-up time prior to the Low-to-High
clock transition L = Low voltage level l = Low voltage level one set-up time prior to the Low-to-High
clock transition NC= No change X = Don’t care Z = High impedance “off” state = Low-to-High clock transition
= not a Low-to-High clock transition
D0-D7 Data inputs
Q0-Q7 Inverting 3-State outputs
Clock pulse input (active rising edge)
Positive supply voltage
CC
LOGIC DIAGRAM
D0
11
CP
1
OE
2
D
CP Q
Q0
D1
3
D
CP Q
19
Q1
D2
4
D
CP Q
18
Q2
D3
5
D
CP Q
17
Q3
D4
6
D
CP Q
16
Q4
D5
7
D
CP Q
15
Q5
D6
8
D
CP Q
14
Q6
D7
9
D
CP Q
13
12
Q7
SV00168
1998 Feb 19
3
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Philips Semiconductors Product specification
I
DC output current
mA
SYMBOL
PARAMETER
UNIT
I
mA
74LVT5343.3V Octal D-type flip-flop, inverting (3-State)
ABSOLUTE MAXIMUM RATINGS
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
DC supply voltage –0.5 to +4.6 V DC input diode current VI < 0 –50 mA DC input voltage DC output diode current VO < 0 –50 mA DC output voltage
PARAMETER CONDITIONS RATING UNIT
3
1, 2
–0.5 to +7.0 V
3
Output in Off or High state –0.5 to +7.0 V
Output in Low state 128
OUT
T
stg
p
Output in High state –64
Storage temperature range –65 to 150 °C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
MIN MAX
V
CC
V
I
V
IH
V
IL
I
OH
OL
t/v Input transition rise or fall rate; outputs enabled 10 ns/V
T
amb
DC supply voltage 2.7 3.6 V Input voltage 0 5.5 V High-level input voltage 2.0 V Input voltage 0.8 V High-level output current –32 mA Low-level output current 32 Low-level output current; current duty cycle 50%, f 1kHz 64
Operating free-air temperature range –40 +85 °C
1998 Feb 19
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Philips Semiconductors Product specification
IIIn ut leakage current
4
µA
Data ins
4
7
74LVT5343.3V Octal D-type flip-flop, inverting (3-State)
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT
MIN TYP1MAX
V
V
V
V
I
OFF
I
HOLD
I
I
PU/PD
I
OZH
I
OZL
I
CCH
I
CCL
I
CCZ
I
NOTES:
1. All typical values are at V
2. This is the increase in supply current for each input at the specified voltage level other than V
3. This parameter is valid for any V transition time of 100µsec is permitted. This parameter is valid for T
4. Unused pins at V
5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
6. I
CCZ
7. This is the bus hold overdrive current required to force the input to the opposite logic state.
Input clamp voltage VCC = 2.7V; IIK = –18mA –0.9 –1.2 V
IK
VCC = 2.7 to 3.6V; IOH = –100µA VCC-0.2 VCC-0.1
High-level output voltage VCC = 2.7V; IOH = –8mA 2.4 2.5 V
OH
VCC = 3.0V; IOH = –32mA 2.0 2.2 VCC = 2.7V; IOL = 100µA 0.1 0.2 VCC = 2.7V; IOL = 24mA 0.3 0.5
Low-level output voltage VCC = 3.0V; IOL = 16mA 0.25 0.4 V
OL
VCC = 3.0V; IOL = 32mA 0.3 0.5 VCC = 3.0V; IOL = 64mA 0.4 0.55
Power-up output low voltage5VCC = 3.6V; IO = 1mA; VI = GND or V
RST
CC
0.13 0.55 V
VCC = 0 or 3.6V; VI = 5.5V 1 10
p
VCC = 3.6V; VI = VCC or GND Control pins ±0.1 ±1 VCC = 3.6V; VI = V VCC = 3.6V; VI = 0
CC
p
0.1 1 –1 -5
Output off current VCC = 0V; VI or VO = 0 to 4.5V 1 ±100 µA
VCC = 3V; VI = 0.8V 75 150
Bus Hold current A inputs
VCC = 3V; VI = 2.0V –75 –150 VCC = 0V to 3.6V; VCC = 3.6V ±500
Current into an output in the
EX
High state when VO > V Power up/down 3-State output
3
current
CC
3-State output High current VCC= 3.6V; V 3-State output Low current VCC= 3.6V; V
Quiescent supply current
Additional supply current per
CC
input pin
2
or GND.
CC
= 3.3V and T
CC
CC
VO = 5.5V; VCC = 3.0V 60 125 µA VCC 1.2V; VO = 0.5V to VCC; VI = GND or VCC;
OE/OE = Don’t care
= 3V; VI = VIL or V
O
= 0.5V; VI = VIL or V
O
VCC = 3.6V; Outputs High, VI = GND or V
3
VCC = 3.6V; Outputs Low, VI = GND or V VCC = 3.6V; Outputs Disabled; VI = GND or V VCC = 3V to 3.6V; One input at V
Other inputs at VCC or GND
= 25°C.
amb
between 0V and 1.2V with a transition time of up to 10msec. From V
amb
IH
IH
-0.6V,
CC
= 25°C only.
I
0 0.13 0.19
CC,
O =
I
0 3 12 mA
CC,
O =
CC,
I
O =
CC
6
0
or GND
= 1.2V to VCC = 3.3V ± 0.3V a
CC
1 ±100 µA 1 5 µA
1 –5 µA
0.13 0.19
0.1 0.2 mA
is measured with outputs pulled to VCC or down to GND.
µA
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500; T
SYMBOL PARAMETER WAVEFORM VCC = 3.3V ± 0.3V VCC = 2.7V UNIT
f
MAX
t
PLH
t
PHL
t
PZH
t
PZL
t
PHZ
t
PLZ
Maximum clock frequency 1 100 150 100 ns Propagation delay
CP to Qn Output enable time
to High and Low level Output disable time
from High and Low level
NOTE:
1. All typical values are at V
= 3.3V and T
CC
amb
1998 Feb 19
= –40°C to +85°C.
amb
= 25°C.
LIMITS
3.0
3.5
3.2
3.3
3.5
3.4
1
MAX MIN MAX
4.6
4.9
5.4
5.5
3.0
4.8
5.4
5.2
7.0
5.6
5.3
4.6
MIN TYP
1 3
4 3
4
1.7
2.2
1.7
1.7
2.1
2.1
5
ns
ns
ns
Page 6
Philips Semiconductors Product specification
74LVT5343.3V Octal D-type flip-flop, inverting (3-State)
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500; T
SYMBOL PARAMETER WAVEFORM VCC = 3.3V ± 0.3V VCC = 2.7V UNIT
tS(H) tS(L)
TH(H) TH(L)
TW(H) TW(L)
Setup time, High or Low, Dn to CP 2
Hold time, High or Low, Dn to CP 2
CP pulse width High or Low 1
AC WAVEFORMS
VM = 1.5V, VIN = GND to 2.7V
= –40°C to +85°C.
amb
LIMITS
MIN TYP MIN
2.0
2.6 0
0
1.5
4.2
1.0
1.3
–1.3 –0.9
0.8
3.0
2.0
3.2 0
0
1.5
5.0
ns
ns
ns
1/f
CP
Qn
MAX
1.5V
tw(H) tw(L)
t
PHL
1.5V
1.5V 1.5V
t
PLH
1.5V
2.7V
0V
V
V
SV00044
OH
OL
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
2.7V
Dn
CP
1.5V 1.5V 1.5V 1.5V
ts(H)
(H)
t
h
t
(L)
s
0V
(L)
t
h
2.7V
1.5V1.5V 0V
NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
SV00108
Waveform 2. Data Setup and Hold Times
2.7V
OE
Qn
1.5V 1.5V
t
PZH
1.5V
t
PHZ
0V
V
OH
V
–0.3V
OH
0V
SV00119
Waveform 3. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
2.7V
OE
Qn
1.5V 1.5V
t
PZL
1.5V
t
PLZ
VOL +0.3V V
OL
SV00120
0V
3V
Waveform 4. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
1998 Feb 19
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Philips Semiconductors Product specification
74LVT5343.3V Octal D-type flip-flop, inverting (3-State)
TEST CIRCUIT AND WAVEFORM
V
CC
PULSE
GENERATOR
V
IN
D.U.T.
R
T
V
OUT
R
L
C
L
R
L
Test Circuit for 3-State Outputs
SWITCH POSITION
TEST SWITCH
t
PLH/tPHL
t
PLZ/tPZL
t
PHZ/tPZH
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value.
= Load capacitance includes jig and probe capacitance;
C
L
see AC CHARACTERISTICS for value.
R
= Termination resistance should be equal to Z
T
pulse generators.
Open
6V
GND
OUT
of
6.0V
GND
Open
NEGATIVE PULSE
POSITIVE PULSE
FAMILY
74LVT
t
90%
10%
V
M
10% 10%
t
THL
t
TLH
90% 90%
V
M
W
(tF)
(tR)t
t
W
90%
V
M
V
M
10%
VM = 1.5V
Input Pulse Definition
INPUT PULSE REQUIREMENTS
Amplitude Rep. Rate t
t
W
2.7V 10MHz 500ns 2.5ns 2.5ns
AMP (V)
0V
(tR)
t
TLH
(tF)
THL
AMP (V)
0V
t
R
F
SV00092
1998 Feb 19
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Philips Semiconductors Product specification
74LVT5343.3V Octal D-type flip-flop; inverting (3-State)
SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
1998 Feb 19
8
Page 9
Philips Semiconductors Product specification
74LVT5343.3V Octal D-type flip-flop; inverting (3-State)
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1
1998 Feb 19
9
Page 10
Philips Semiconductors Product specification
74LVT5343.3V Octal D-type flip-flop; inverting (3-State)
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
1998 Feb 19
10
Page 11
Philips Semiconductors Product specification
74LVT5343.3V Octal D-type flip-flop; inverting (3-State)
NOTES
1998 Feb 19
11
Page 12
Philips Semiconductors Product specification
3.3V Octal D-type flip-flop, inverting (3-State)
Data sheet status
Data sheet status
Objective specification
Preliminary specification
Product specification
Product status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
[1]
74LVT534
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook. Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 05-96 Document order number: 9397-750-03536
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