Datasheet 74LVT374DB, 74LVT374D, 74LVT374PW Datasheet (Philips)

INTEGRATED CIRCUITS

74LVT374

3.3V Octal D-type flip-flop; positive-edge
trigger (3-State)

Product specification
Supersedes data of 1996 Feb 08
IC23 Data Handbook

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1998 Feb 19

Philips Semiconductors Product specification

3.3V Octal D-type flip-flop; positive-edge trigger
(3-State)

FEA TURES

•Inputs and outputs on opposite side of package allow easy

interface to microprocessors

•3-State outputs for bus interfacing

•Common output enable

•TTL input and output switching levels

•Input and output interface capability to systems at 5V supply

•Bus-hold data inputs eliminate the need for external pull-up

resistors to hold unused inputs

•Live insertion/extraction permitted

•No bus current loading when output is tied to 5V bus

•Power-up 3-State

•Power-up reset

•Latch-up protection exceeds 500mA per JEDEC Std 17

•ESD protection exceeds 2000V per MIL STD 883 Method 3015

and 200V per Machine Model

QUICK REFERENCE DATA

SYMBOL PARAMETER

C

t

PLH

t

PHL

C

OUT

I

CCZ

IN

Propagation delay
CP to Qn

Input capacitance VI = 0V or 3.0V 4 pF
Output capacitance

Total supply current

CL = 50pF;
VCC = 3.3V

Outputs disabled;
V

Outputs disabled;
VCC = 3.6V

DESCRIPTION

The 74LVT374 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.

The 74LVT374 is an 8-bit, edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by the clock (CP) and Output Enable (OE
gates.

The register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.

The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE
independent of the clock operation.

When OE
is High, the outputs are in the High-impedance “OFF” state, which
means they will neither drive nor load the bus.

T

amb

= 0V or 3.0V

I/O

is Low, the stored data appears at the outputs. When OE

CONDITIONS
= 25°C; GND = 0V

74L VT374

) control

) controls all eight 3-State buffers

TYPICAL UNIT

3.2

3.5

7 pF

0.13 mA

ns

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA DWG NUMBER

20-Pin Plastic SOL –40°C to +85°C 74LVT374 D 74LVT374 D SOT163-1
20-Pin Plastic SSOP Type II –40°C to +85°C 74LVT374 DB 74LVT374 DB SOT339-1
20-Pin Plastic TSSOP Type I –40°C to +85°C 74LVT374 PW 74LVT374PW DH SOT360-1

PIN CONFIGURATION

1

OE

2

Q0

3

D0

4

D1

5

Q1

6

Q2

7

D2

8

D3

9

Q3 Q4

10 11

GND

20

V
Q7

19

D7

18

D6

17

Q6

16

Q5

15

D5

14

D4

13
12

CP

SA00110

CC

PIN DESCRIPTION

PIN

NUMBER

1 OE Output enable input (active-Low)

3, 4, 7, 8,

13, 14, 17,

18

2, 5, 6, 9,

12, 15, 16,

19
11 CP Clock pulse input (active rising edge)
10 GND Ground (0V)
20 V

SYMBOL FUNCTION

D0-D7 Data inputs

Q0-Q7 Data outputs

Positive supply voltage

CC

1998 Feb 19 853-1826 18985

2

Philips Semiconductors Product specification

INTERNAL

OPERATING MODE

Load and read register

3.3V Octal D-type flip-flop; positive-edge trigger
(3-State)

LOGIC SYMBOL

3 4 7 8 13 14 1817

D0 D1 D2 D3 D4 D5 D6 D7

11

CP
OE

1

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

2 5 6 9 12 15 16 19

SA00111

FUNCTION TABLE

INPUTS

OE CP Dn

L ↑ l L L
L ↑ h H H
L ↑ X NC NC Hold

H X X NC Z Disable outputs

H = High voltage level
h = High voltage level one set-up time prior to the Low-to-High clock transition
L = Low voltage level
l = Low voltage level one set-up time prior to the Low-to-High clock transition
NC= No change
X = Don’t care
Z = High impedance “off” state
↑ = Low-to-High clock transition

= not a Low-to-High clock transition

↑

INTERNAL
REGISTER

LOGIC SYMBOL (IEEE/IEC)

OUTPUTS

Q0 – Q7

74LVT374

1

11

32
4 5
7 6
89
13 12
14 15
17 16
18 19

EN
C1

1D

SA00112

LOGIC DIAGRAM

11

CP

1

OE

1998 Feb 19

D0

3 4 7 8 13 14 17 18

D

CP Q

D1

D

CP Q

2 5 6 9 12 15 16 19

Q0

D2

D

CP Q

Q1 Q2 Q3 Q4 Q5 Q6 Q7

D3

D

CP Q

D4

D

CP Q

D5

D

CP Q

D6

D

CP Q

3

D7

D

CP Q

SA00113

Philips Semiconductors Product specification

I

DC output current

mA

SYMBOL

PARAMETER

UNIT

I

mA

3.3V Octal D-type flip-flop; positive-edge trigger
(3-State)

ABSOLUTE MAXIMUM RATINGS

SYMBOL

V

V

I
V

I

OK

OUT

OUT

T

CC

IK

I

stg

DC supply voltage –0.5 to +4.6 V
DC input diode current VI < 0 –50 mA
DC input voltage
DC output diode current VO < 0 –50 mA
DC output voltage

Storage temperature range –65 to 150 °C

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.

3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.

PARAMETER CONDITIONS RATING UNIT

3

p

1, 2

–0.5 to +7.0 V

3

Output in Off or High state –0.5 to +7.0 V

Output in Low state 128

Output in High state –64

74LVT374

RECOMMENDED OPERATING CONDITIONS

LIMITS

MIN MAX

V

CC

V

I

V

IH

V

IL

I

OH

OL

∆t/∆v Input transition rise or fall rate; outputs enabled 10 ns/V

T

amb

DC supply voltage 2.7 3.6 V
Input voltage 0 5.5 V
High-level input voltage 2.0 V
Input voltage 0.8 V
High-level output current –32 mA
Low-level output current 32
Low-level output current; current duty cycle ≤ 50%, f ≥ 1kHz 64

Operating free-air temperature range –40 +85 °C

1998 Feb 19

4

Philips Semiconductors Product specification

Data pins

4

7

3.3V Octal D-type flip-flop; positive-edge trigger
(3-State)

DC ELECTRICAL CHARACTERISTICS

SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT

MIN TYP1MAX

V

V

V

V

I

OFF

I

HOLD

I

I

PU/PD

I

OZH

I

OZL

I

CCH

I

CCL

I

CCZ

∆I

NOTES:

1. All typical values are at V

2. This is the increase in supply current for each input at the specified voltage level other than V

3. This parameter is valid for any V
transition time of 100µsec is permitted. This parameter is valid for T

4. Unused pins at V

5. For valid test results, data must not be loaded into the flip-flops (or latches) after applying power.

6. I

CCZ

7. This is the bus hold overdrive current required to force the input to the opposite logic state.

Input clamp voltage VCC = 2.7V; IIK = –18mA –0.9 –1.2 V

IK

VCC = 2.7 to 3.6V; IOH = –100µA VCC-0.2 VCC-0.1

High-level output voltage VCC = 2.7V; IOH = –8mA 2.4 2.5 V

OH

VCC = 3.0V; IOH = –32mA 2.0 2.2
VCC = 2.7V; IOL = 100µA 0.1 0.2
VCC = 2.7V; IOL = 24mA 0.3 0.5

Low-level output voltage VCC = 3.0V; IOL = 16mA 0.25 0.4 V

OL

VCC = 3.0V; IOL = 32mA 0.3 0.5
VCC = 3.0V; IOL = 64mA 0.4 0.55

Power-up output low voltage5VCC = 3.6V; IO = 1mA; VI = GND or V

RST

CC

VCC = 0 or 3.6V; VI = 5.5V 1 10
VCC = 3.6V; VI = VCC or GND Control pins ±0.1 ±1

I

Input leakage current

I

VCC = 3.6V; VI = V
VCC = 3.6V; VI = 0

CC

p

Output off current VCC = 0V; VI or VO = 0 to 4.5V 1 ±100 µA

VCC = 3V; VI = 0.8V 75 150

Bus Hold current A inputs

VCC = 3V; VI = 2.0V –75 –150
VCC = 0V to 3.6V; VCC = 3.6V ±500

Current into an output in the

EX

High state when VO > V
Power up/down 3-State output

3

current

CC

3-State output High current VCC= 3.6V; V
3-State output Low current VCC= 3.6V; V

Quiescent supply current

Additional supply current per

CC

input pin

2

or GND.

CC

= 3.3V and T

CC

CC

VO = 5.5V; VCC = 3.0V 60 125 µA

VCC ≤ 1.2V; VO = 0.5V to VCC; VI = GND or VCC;
OE/OE

= Don’t care

= 3V; VI = VIL or V

O

= 0.5V; VI = VIL or V

O

VCC = 3.6V; Outputs High, VI = GND or V

3

VCC = 3.6V; Outputs Low, VI = GND or V
VCC = 3.6V; Outputs Disabled; VI = GND or V
VCC = 3V to 3.6V; One input at V

Other inputs at VCC or GND

= 25°C.

amb

between 0V and 1.2V with a transition time of up to 10msec. From V

amb

IH

IH

-0.6V,

CC

= 25°C only.

I

0 0.13 0.19

CC,

O =

I

0 3 12 mA

CC,

O =

6

I

0

CC,

O =

or GND

CC

= 1.2V to VCC = 3.3V ± 0.3V a

CC

is measured with outputs pulled to VCC or down to GND.

74LVT374

LIMITS

0.13 0.55 V

0.1 1
–1 -5

1 ±100 µA

1 5 µA
1 –5 µA

0.13 0.19

0.1 0.2 mA

µA

µA

1998 Feb 19

5

Philips Semiconductors Product specification

3.3V Octal D-type flip-flop; positive-edge trigger
(3-State)

AC CHARACTERISTICS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω; T

SYMBOL PARAMETER WAVEFORM VCC = 3.3V ± 0.3V VCC = 2.7V UNIT

f

MAX

t

PLH

t

PHL

t

PZH

t

PZL

t

PHZ

t

PLZ

Maximum clock frequency 1 125 200 125 ns
Propagation delay

CP to Qn
Output enable time

to High and Low level
Output disable time

from High and Low level

NOTE:

1. All typical values are at V

= 3.3V and T

CC

amb

AC SETUP REQUIREMENTS

GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500Ω; T

SYMBOL PARAMETER WAVEFORM VCC = 3.3V ± 0.3V VCC = 2.7V UNIT

tS(H)
t

(L)

S

TH(H)
T

(L)

H

TW(H) CP pulse width High or Low 1

Setup time, High or Low, Dn to CP 2

Hold time, High or Low, Dn to CP 2

= –40°C to +85°C.

amb

= 25°C.

= –40°C to +85°C.

amb

LIMITS

3.2

3.5

3.2

3.4

4.3

3.4

1

MAX MIN MAX

5.1

5.2

5.3

5.2

6.7

5.1

MIN TYP

1
3

4
3

4

1.7

2.2

1.5

2.0

1.9

2.0

LIMITS

MIN TYP MIN

2.0

2.0

0.3

0.3

1.5

2.5

0.7

0.7

–0.5
–0.5

0.8

1.7

74LVT374

5.8

5.5

7.3

6.1

7.1

5.1

2.0

2.0
0

0

1.5

3.0

ns

ns

ns

ns

ns

ns

AC WAVEFORMS

VM = 1.5V, VIN = GND to 3.0V

1/f

MAX

CP

Qn

Waveform 1. Propagation Delay, Clock Input to Output, Clock

Pulse Width, and Maximum Clock Frequency

Dn

CP

NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.

VM VM VM

tw(H) tw(L)

t

PHL

VM VM

V

V

M

M

(H) th(H) ts(L) th(L)

t

s

V

M

t

PLH

V

M

SA00056

V

M

V

M

Waveform 2. Data Setup and Hold Times

SA00107

OE

Qn

V

M

t

PZH

V

M

t

PHZ

V

M

VOH–0.3V

0V

SA00066

Waveform 3. 3-State Output Enable Time to High Level and

Output Disable Time from High Level

OE

Qn

V

M

t

PZL

V

M

t

PLZ

V

M

VOL+0.3V

0V

SA00067

Waveform 4. 3-State Output Enable Time to Low Level and

Output Disable Time from Low Level

1998 Feb 19

6

Philips Semiconductors Product specification

3.3V Octal D-type flip-flop; positive-edge trigger
(3-State)

TEST CIRCUIT AND WAVEFORM

6.0V

Open

R

R

GND

L

L

NEGATIVE
PULSE

POSITIVE
PULSE

V

PULSE

GENERATOR

IN

R

T

Test Circuit for 3-State Outputs

SWITCH POSITION

TEST SWITCH

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

6V

GND

V

CC

D.U.T.

V

OUT

C

L

90%

10%

74LVT374

t

W

V

M

10% 10%

t

(tF)

THL

t

(tR)t

TLH

90% 90%

V

M

t

W

V

M

V

M

VM = 1.5V

Input Pulse Definition

90%

10%

t

TLH

THL

AMP (V)

0V

(tR)

(tF)

AMP (V)

0V

DEFINITIONS

RL = Load resistor; see AC CHARACTERISTICS for value.

= Load capacitance includes jig and probe capacitance;

C

L

see AC CHARACTERISTICS for value.

= Termination resistance should be equal to Z

R

T

pulse generators.

OUT

of

FAMILY

74LVT

INPUT PULSE REQUIREMENTS

Amplitude Rep. Rate t

t

W

R

2.7V 10MHz 500ns 2.5ns 2.5ns

t

F

SV00092

1998 Feb 19

7

Philips Semiconductors Product specification

3.3V Octal D-type flip-flop; positive-edge trigger
(3-State)

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

74LVT374

1998 Feb 19

8

Philips Semiconductors Product specification

3.3V Octal D-type flip-flop; positive-edge trigger
(3-State)

SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1

74LVT374

1998 Feb 19

9

Philips Semiconductors Product specification

3.3V Octal D-type flip-flop; positive-edge trigger
(3-State)

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

74LVT374

1998 Feb 19

10

Philips Semiconductors Product specification

3.3V Octal D-type flip-flop; positive-edge trigger
(3-State)

NOTES

74LVT374

1998 Feb 19

11

Philips Semiconductors Product specification

3.3V Octal D-type flip-flop; positive-edge trigger
(3-State)

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

74LVT374

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1998

All rights reserved. Printed in U.S.A.

print code Date of release: 05-96
Document order number: 9397-750-03535

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