Datasheet 74lvch2373a DATASHEETS (Philips)

INTEGRATED CIRCUITS

74LVC2373A 74LVCH2373A

Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State)

Product specification IC24 Data Handbook

1997 Mar 12

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Philips Semiconductors Product specification

Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State)

FEA TURES

•5-volt tolerant inputs/outputs, for interfacing with 5-volt logic

•Supply voltage range of 2.7V to 3.6V

•Complies with JEDEC standard no. 8-1A

•CMOS low power consumption

•Direct interface with TTL levels

•High impedance when V

CC

= 0V

•Bushold on all data inputs (74LVCH2373A only)

•Integrated 30 damping resistor

QUICK REFERENCE DATA

GND = 0V; T

SYMBOL

t

PHL/tPLH

C

I

C

PD

NOTES:

is used to determine the dynamic power dissipation (PD in µW)

1. C

PD

= CPD × V

P

D

= input frequency in MHz; CL = output load capacity in pF;

f

i

= output frequency in MHz; VCC = supply voltage in V;

f

o

Σ (C

L

2. The condition is V

= 25°C; tr = tf 2.5 ns

amb

Propagation delay Dn to Qn LE to Qn

Input capacitance 5.0 pF Power dissipation capacitance per latch Notes 1, 2 20 pF

2

× fi Σ (CL × V

CC

2

× V

× fo) = sum of the outputs.

CC

= GND to V

I

PARAMETER CONDITIONS TYPICAL UNIT

2

× fo) where:

CC

CC.

DESCRIPTION

The 74LVC2373A/74LVCH2373A is a high performance, low-power, low-voltage Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either

3.3V or 5V devices. This feature allows the use of these devices as translators in a mixed 3.3V/5V environment.

The 74LVC2373A/74LVCH2373A is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-State outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE

The ‘2373’ consists of eight D-type transparent latches with 3-State true outputs. When LE is HIGH, data at the Dn inputs enters the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding D-input changes.

When LE is LOW the latches store the information that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE available at the outputs. When OE high impedance OFF-state. Operation of the OE affect the state of the latches.

CL = 50pF

= 3.3V 4.4

V

CC

74L VC2373A

74L VCH2373A

) input are common to all internal latches.

is LOW, the contents of the eight latches are

is HIGH, the outputs go to the

input does not

ns

5.0

ORDERING AND PACKAGE INFORMA TION

PACKAGES TEMPERATURE RANGE

20-Pin Plastic SO –40°C to +85°C 74LVC2373A D 74LVC2373A D SOT163-1 20-Pin Plastic SSOP Type II –40°C to +85°C 74LVC2373A DB 74LVC2373A DB SOT339-1 20-Pin Plastic TSSOP Type I –40°C to +85°C 74LVC2373A PW LVC2373APW DH SOT360-1 20-Pin Plastic SO –40°C to +85°C 74LVCH2373A D 74LVCH2373A D SOT163-1 20-Pin Plastic SSOP Type II –40°C to +85°C 74LVCH2373A DB 7LVCH2373A DB SOT339-1 20-Pin Plastic TSSOP Type I –40°C to +85°C 74LVCH2373A PW VCH2373APW DH SOT360-1

1997 Mar 12 853–1940 17843

OUTSIDE NORTH

AMERICA

2

NORTH AMERICA PKG. DWG. #

Philips Semiconductors Product specification

Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State)

PIN CONFIGURATION

OE

GND

Q0 D0 D1 Q1 Q2

D2 D3 Q3

1 2 3 4 5 6

7 8 9

10

20

V

CC

19

Q7

18

D7

17

D6

16

Q6

15

Q5

14

D5

13

D4 Q4

12

11

LE

PIN DESCRIPTION

PIN NUMBER SYMBOL FUNCTION

1 OE Output enable input (active LOW)

2, 5, 6, 9, 12,

15, 16, 19

3, 4, 7, 8, 13,

14, 17, 18

Q0–Q7 3-State latch outputs

D0–D7 Data inputs

10 GND Ground (0V) 11 LE Latch enable input (active HIGH) 20 V

Positive supply voltage

CC

LOGIC SYMBOL (IEEE/IEC)

11

C1

1

EN1

SV00657

LOGIC SYMBOL

FUNCTIONAL DIAGRAM

74LVC2373A

74LVCH2373A

11

D0 D1 D2 D3 D4 D5 D6 D7

OE

LATCH 1 to 8

LE

1

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

2 5 6 9 12 15 16 19

3–STATE OUTPUTS

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

SV00658

2

5

6

9

12

15

16

19

3 4 7

8 13 14 17 18

3

D0

4

D1

7

D2

8

D3

13

D4

14

D5

17

D6

18

D7

11

LE

1

OE

1997 Mar 12

3

1D

4

7

8

13

14

17

18

2

5

6

9

12

15

16

19

SV00659

FUNCTION TABLE

OPERATING MODES

Enable and read register (transparent mode)

Latch and read register

Latch register and disable outputs

OE LE Dn

L L

H H

INPUTS

H H

L L

L

H

I

h

I

h

INTERNAL

LATCHES

L

H

L

H

L

H

SV00660

OUTPUTS

Q0 to Q7

L

H

L

H Z

Z

H = HIGH voltage level h = HIGH voltage level one set-up time prior to the HIGH-to-LOW

LE transition L = LOW voltage level I = LOW voltage level one set-up time prior to the HIGH-to-LOW

LE transition X = Don’t care Z = High impedance OFF-state

3

Philips Semiconductors Product specification

SYMBOL

PARAMETER

CONDITIONS

UNIT

mW

Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State)

LOGIC DIAGRAM

D0

D LATCH

1 LE

LE

OE

RECOMMENDED OPERATING CONDITIONS

V V

T

V

amb

tr, t

DC supply voltage (for max. speed performance) 2.7 3.6 V

CC

DC supply voltage (for low-voltage applications) 1.2 3.6 V

CC

DC input voltage range 0 5.5 V

I

DC input voltage range for I/Os 0 V

I/O

DC output voltage range 0 V

O

Operating free-air temperature range –40 +85 °C Input rise and fall times

f

D1

Q

LE

Q0

D LATCH

2 LE

D2

Q

LE

Q1

D LATCH

3 LE

D3

Q

LE

Q2

D LATCH

4 LE

D4

Q

LE

Q3

VCC = 1.2 to 2.7V V

CC

Q

D LATCH

5

LE

Q4

= 2.7 to 3.6V

74LVC2373A

74LVCH2373A

D5

D LATCH

6 LE

D6

Q

LE

Q5

D LATCH

7 LE

D7

Q

LE

Q6

D LATCH

8 LE

Q

LE

Q7

SV00661

LIMITS

MIN MAX

CC CC

0 0

20 10

V V

ns/V

ABSOLUTE MAXIMUM RATINGS

1

In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V).

SYMBOL

V

CC

I

IK

V

I

V

I/O

I

OK

V

OUT

V

OUT

I

OUT

I

, I

GND

CC

T

stg

DC supply voltage –0.5 to +6.5 V DC input diode current VI t0 –50 mA DC input voltage Note 2 –0.5 to +5.5 V DC input voltage range for I/Os –0.5 to VCC +0.5 V DC output diode current V DC output voltage; output HIGH or LOW Note 2 –0.5 to VCC +0.5 V DC output voltage; output 3-State Note 2 –0.5 to +6.5 V DC output source or sink current VO = 0 to V DC VCC or GND current ±100 mA Storage temperature range –60 to +150 °C

PARAMETER CONDITIONS RATING UNIT

uVCC or VO t 0 ±50 mA

O

CC

±50 mA

Power dissipation per package

P

TOT

– plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500 – plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 500

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

1997 Mar 12

4

Philips Semiconductors Product specification

VIHHIGH level Input voltage

V

VILLOW level Input voltage

V

VOLLOW level output voltage

V

Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State)

74LVC2373A

74LVCH2373A

DC ELECTRICAL CHARACTERISTICS

Over recommended operating conditions. V oltages are referenced to GND (ground = 0V).

LIMITS

SYMBOL PARAMETER TEST CONDITIONS Temp = -40°C to +85°C UNIT

MIN TYP1MAX

p

VCC = 1.2V V VCC = 2.7 to 3.6V 2.0 VCC = 1.2V GND VCC = 2.7 to 3.6V 0.8 VCC = 3.0V; VI = VIH or VIL; IO = –100µA VCC0.2 V

V

OH

V

OH

V

OL

I

IHZ/IILZ

I

OZ

I

CC

∆I

CC

I

BHL

I

BHH

I

BHLO

I

BHHO

HIGH level output voltage

VCC = 3.0V; VI = VIH or V VCC = 3.0V; VI = VIH or V VCC = 2.7V; VI = VIH or VIL; IO = –6mA

HIGH level output voltage

VCC = 3.0V; VI = VIH or VIL; IO = –100µA VCC = 3.0V; VI = VIH or V

p

VCC = 3.0V; VI = VIH or VIL; IO = 100µA GND 0.20 VCC = 3.0V; VI = VIH or V VCC = 2.7V; VI = VIH or VIL; IO = 6mA

LOW level output voltage

VCC = 3.0V; VI = VIH or VIL; IO = 100µA

VCC = 3.0V; VI = VIH or V Input leakage current VCC = 3.6V; VI = 5.5V or GND Not for I/O pins ±0.1 ±5 µA Input current for common I/O pins VCC = 3.6V; VI = VCC or GND ±0.1 ±15 µA 3-State output OFF-state current VCC = 3.6V; VI = VIH or VIL; VO = VCC or GND 0.1 ±10 µA Quiescent supply current VCC = 3.6V; VI = VCC or GND; IO = 0 0.1 20 µA Additional quiescent supply current per

input pin Bushold LOW sustaining current Bushold HIGH sustaining current Bushold LOW overdrive current Bushold HIGH overdrive current

2, 3, 4

2, 3, 5

VCC = 2.7V to 3.6V; VI = VCC –0.6V; IO = 0 5 500 µA

VCC = 3.0V; V

=0.8V 75 – – µA

I

=2.0V –75 – – µA

I

VCC = 3.6V 500 – – µA

VCC = 3.6V –500 – – µA

IO = –12mA VCC0.6

IL;

IO = –24mA VCC1.0

IL;

IO = –12mA

IL;

IO = 24mA 0.55

IL;

IO = 12mA

IL;

7

NOTES:

1. All typical values are at V

2. Valid for data inputs of bushold parts (LVCH-A) only.

= 3.3V and T

CC

amb

= 25°C.

3. For data inputs only, control inputs do not have a bushold circuit.

4. The specified sustaining current at the data inputs do not have a bushold circuit.

5. The specified overdrive current at the data input forces the data input to the opposite logic input state.

6. For bushold parts, the bushold circuit is switched off when V

7. For data outputs of damping resistor parts only.

exceeds VCC allowing 5.5V on the input terminal.

I

CC

VCC0.5 VCC0.2 V VCC0.8

CC

0.40

GND 0.20

0.55

V

1997 Mar 12

5

Philips Semiconductors Product specification

Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State)

74LVC2373A

74LVCH2373A

AC CHARACTERISTICS

GND = 0 V; tr = tf v 2.5 ns; CL = 50 pF

LIMITS

SYMBOL PARAMETER WAVEFORM VCC = 3.3V ±0.3V VCC = 2.7V VCC = 1.2V UNIT

1

MAX MIN MAX TYP

t

PHL/tPLH

t

PHL/tPLH

t

PZH/tPZL

t

PHZ/tPLZ

t

W

t

su

t

h

Propagation delay Dn to Qn

Propagation delay LE to Qn

3-State output enable time

to Qn

OE 3-State output disble time

to Qn

OE LE pulse width HIGH Figure 2 4.0 – – 4.0 – – ns Set-up time

Dn to LE Hold time

Dn to LE

NOTE:

1. These typical values are at V

= 3.3V and T

CC

MIN TYP

Figures 1, 5 1.5 – 8.5 1.5 9.5 – ns

Figures 2, 5 1.5 – 9.5 1.5 11 – ns

Figures 3, 5 1.5 – 9.0 1.5 11 – ns

Figures 3, 5 1.5 – 6.0 1.5 6.5 – ns

Figure 4 2.0 – – 3.0 – – ns

= 25°C.

amb

AC WAVEFORMS

VM = 1.5 V at VCC w 2.7 V

= 0.5  VCC at VCC < 2.7 V

V

M

and VOH are the typical output voltage drop that occur with the output load.

V

OL

= VOL + 0.3 V at VCC ≥ 2.7 V

V

X

– VOL + 0.1 ⋅ VCC at VCC < 2.7 V

V

X

= VOH – 0.3 V at VCC ≥ 2.7 V

V

Y

= VOH – 0.1 ⋅ VCC at VCC < 2.7 V

V

Y

V

I

INPUTS

GND

t

PHL

V

OH

OUTPUTS

V

OL

Figure 1. nput (Dn) to output (Qn) propagation delays

V

M

t

PLH

V

M

SV00690

V

I

LE INPUT

Q

n

GND

V

OUTPUT

V

OH

OL

V

M

t

W

t

PHL

V

M

t

PLH

SV00691

Figure 2. Latch enable input (LE) pulse width, the latch enable

input to output (Qn) propagation delays

1997 Mar 12

6

Philips Semiconductors Product specification

Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State)

V

I

OE INPUT

GND

OUTPUT LOW–to–OFF OFF–to–LOW

OUTPUT HIGH–to–OFF OFF–to–HIGH

GND

V

CC

V

OL

V

OH

V

M

t

PLZ

t

PHZ

outputs

enabled

V

X

V

Y

outputs

disabled

Figure 3. 3-State enable and disable times

V

I

Dn INPUT

GND

V

I

LE INPUT

GND

NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.

V

M

t

h

t

su

V

M

Figure 4. Data set-up and hold times

for the Dn input to the LE input

t

PZL

V

M

t

PZH

V

M

outputs enabled

SV00692

t

h

t

su

SV00693

TEST CIRCUIT

PULSE

GENERATOR

74LVC2373A

74LVCH2373A

S

Open

2 < V

GND

1

500Ω

1

CC

V

CC

V

I

R

T

V

CC

t 2.7V V

2.7V – 3.6V 2.7V

V

D.U.T.

I

CC

V

O

C

L

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

50pF

Test S

Figure 5. Load circuitry for switching times

2 < V

CC

Open GND

SY00003

1997 Mar 12

7

Philips Semiconductors Product specification

Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State)

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

74LVC2373A

74LVCH2373A

1997 Mar 12

8

Philips Semiconductors Product specification

Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State)

SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1

74LVC2373A

74LVCH2373A

1997 Mar 12

9

Philips Semiconductors Product specification

Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State)

TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1

74LVC2373A

74LVCH2373A

1997 Mar 12

10

Philips Semiconductors Product specification

Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State)

NOTES

74LVC2373A

74LVCH2373A

1997 Mar 12

11

Philips Semiconductors Product specification

Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor (3-State)

74LVC2373A

74LVCH2373A

DEFINITIONS

Data Sheet Identification Product Status Definition

Objective Specification

Preliminary Specification

Product Specification

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

LIFE SUPPORT APPLICA TIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected

to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

Formative or in Design

Preproduction Product

Full Production

This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.

 Copyright Philips Electronics North America Corporation 1997

 

1997 Mar 12

12