Page 1
INTEGRATED CIRCUITS
74LV4040
12-stage binary ripple counter
Product specification 1998 Jun 23
IC24 Data Handbook
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Philips Semiconductors Product specification
74L V404012-stage binary ripple counter
FEA TURES
•Optimized for Low Voltage applications: 1.0 to 5.5V
•Accepts TTL input levels between V
•Typical V
T
amb
•Typical V
T
amb
(output ground bounce) 0.8V @ VCC = 3.3V,
OLP
= 25°C
(output VOH undershoot) 2V @ VCC = 3.3V,
OHV
= 25°C
= 2.7V and VCC = 3.6V
CC
•Frequency dividing circuits
•Time delay circuits
•Control counters
•Output capability: standard
•I
category: MSI
CC
QUICK REFERENCE DATA
GND = 0V; T
SYMBOL
t
PHL/tPLH
f
max
C
I
C
PD
NOTES:
is used to determine the dynamic power dissipation (PD in µW)
1. C
PD
= CPD V
P
D
f
= input frequency in MHz; CL = output load capacity in pF;
i
= output frequency in MHz; VCC = supply voltage in V;
f
o
(C
2. The condition is V
= 25°C; tr =tf 2.5 ns
amb
CC
2
V
L
fo) = sum of the outputs.
CC
PARAMETER CONDITIONS TYPICAL UNIT
Propagation delay
CP to Q
0
Qn to Q
n+1
MR to Q
n
Maximum clock frequency 100 MHz
Input capacitance 3.5 pF
Power dissipation capacitance per gate
2
x fi (CL V
= GND to V
I
CC
2
fo) where:
CC
DESCRIPTION
The 74LV4040 is a low–voltage Si–gate CMOS device and is pin
and function compatible with 74HC/HCT4040.
The 74LV4040 is a 12-stage binary ripple counter with a click input
(CP
), an overriding asynchronous master reset input (MR) and
twelve fully buffered parallel outputs (Q
advanced on the HIGH-to-LOW transition of CP
clears all counter stages and forces all outputs LOW, independent of
the state of CP
Each counter stage is a static toggle flip-flop.
CL = 15pF
VCC = 3.3V
Notes 1 and 2
.
to Q11). The counter is
0
. A HIGH on MR
12
7
16
30 pF
ns
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
16-Pin Plastic DIL –40°C to +125°C 74LV4040 N 74LV4040 N SOT38-4
16-Pin Plastic SO –40°C to +125°C 74LV4040 D 74LV4040 D SOT109-1
16-Pin Plastic SSOP Type II –40°C to +125°C 74LV4040 DB 74LV4040 DB SOT338-1
16-Pin Plastic TSSOP Type I –40°C to +125°C 74LV4040 PW 74LV4040PW DH SOT403-1
1998 Jun 23 853-2075 19619
2
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Philips Semiconductors Product specification
74LV404012-stage binary ripple counter
PIN CONFIGURATION
16
Q
GND
1
11
2
Q
5
3
Q
4
4
Q
6
5
Q
3
6
Q
2
Q
7
1
8
V
15
Q
Q
14
13
Q
Q
12
11
MR
CP
10
9
Q
SV00316
CC
10
9
7
8
0
Figure 1. Pin configuration
PIN DESCRIPTION
PIN
NUMBER
9, 7, 6, 5, 3,
2, 4, 13, 12,
14, 15, 1
8 GND Ground (0V)
10 CP
11 MR Master reset input (active HIGH)
16 V
SYMBOL FUNCTION
Q0 to Q
Parallel outputs
11
Clock input (HIGH-to-LOW, edgetriggered)
CC
Positive supply voltage
LOGIC SYMBOL
10
11
CP
MR
Figure 3. Logic symbol
FUNCTIONAL DIAGRAM
CP
T
11
MR
C
D
Q
Q
1
0
7109
12-STAGE COUNTER
Q3Q
2
9
Q
0
7
Q
1
6
Q
2
5
Q
3
3
Q
4
2
Q
5
4
Q
6
13
Q
7
12
Q
8
14
Q
9
15
Q
10
1
Q
11
SV00317
Q
4
5
Q8Q7Q6Q
Q9Q10Q
14 1512 11352543
11
LOGIC SYMBOL (IEEE/IEC)
CTR12
10
11
+
CT=0
CT
Figure 2. IEC Logic symbol
0
11
9
7
5
5
3
2
4
13
12
14
15
1
SV00318
Figure 4. Functional diagram
LOGIC DIAGRAM
CP
MR
SV00319
FF0 FF3 FF11
QQQ
T
Q
R
D
TT
Q Q
R
D
Q0
Q1 Q11
R
D
SV00320
Figure 5. Logic diagram
1998 Jun 23
3
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Philips Semiconductors Product specification
74LV404012-stage binary ripple counter
4.0962.0481.0245122561286432168421
CP INPUT
MR INPUT
OUTPUT
Q
0
OUTPUT
Q
1
Q
OUTPUT
2
Q
OUTPUT
3
OUTPUT
Q
4
Q
OUTPUT
5
Q
OUTPUT
6
Q7 OUTPUT
OUTPUT
Q
8
Q
OUTPUT
9
Q10 OUTPUT
Q
OUTPUT
11
FUNCTION TABLE
INPUTS OUTPUTS
CP MR Q0, Q3 to Q
L no change
L count
X H L
NOTES:
H = HIGH voltage level
L = LOW voltage level
X = Don’t care
= LOW -to-HIGH clock transition
= HIGH-to-LOW clock transition
SV00310
Figure 6. Timing diagram
13
1998 Jun 23
4
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Philips Semiconductors Product specification
74LV404012-stage binary ripple counter
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)
SYMBOL
V
CC
±I
IK
±I
OK
±I
O
±I
GND
±I
CC
T
stg
P
TOT
DC supply voltage –0.5 to +7.0 V
DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA
DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA
DC output source or sink current
– standard outputs
DC VCC or GND current for types with
,
–standard outputs 50
Storage temperature range –65 to +150 °C
Power dissipation per package
–plastic DIL
–plastic mini-pack (SO)
–plastic shrink mini-pack (SSOP and TSSOP)
PARAMETER CONDITIONS RATING UNIT
–0.5V < VO < VCC + 0.5V
25
mA
mA
for temperature range: –40 to +125°C
above +70°C derate linearly with 12mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K
750
500
400
mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT
1
1.0 3.3 5.5 V
CC
CC
–40
–40
–
–
–
–
–
–
–
–
+85
+125
500
200
100
50
ns/V
V
V
°C
T
V
V
tr, t
CC
V
amb
DC supply voltage See Note
Input voltage 0 – V
I
Output voltage 0 – V
O
Operating ambient temperature range in free
air
Input rise and fall times
f
NOTE:
1. The LV is guaranteed to function down to V
See DC and AC
characteristics
VCC = 1.0V to 2.0V
VCC = 2.0V to 2.7V
V
= 2.7V to 3.6V
CC
VCC = 3.6V to 5.5V
= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.
CC
1998 Jun 23
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Philips Semiconductors Product specification
V
V
V
V
HIGH l
t
voltage all out uts
V
g
V
LOW l
t
voltage all out uts
V
g
V
74LV404012-stage binary ripple counter
DC CHARACTERISTICS FOR THE LV FAMILY
Over recommended operating conditions voltages are referenced to GND (ground = 0V)
LIMITS
SYMBOL P ARAMETER TEST CONDITIONS
VCC = 1.2V 0.9 0.9
IH
HIGH level Input
voltage
VCC = 2.0V 1.4 1.4
VCC = 2.7 to 3.6V 2.0 2.0
VCC = 4.5 to 5.5V 0.7*V
VCC = 1.2V 0.3 0.3
IL
LOW level Input
voltage
VCC = 2.0V 0.6 0.6
VCC = 2.7 to 3.6V 0.8 0.8
VCC = 4.5 to 5.5 0.3*V
VCC = 1.2V; VI = VIH or V
VCC = 2.0V; VI = VIH or V
V
OH
evel outpu
;
VCC = 2.7V; VI = VIH or V
p
VCC = 3.0V; VI = VIH or V
VCC = 4.5V; VI = VIH or V
OH
HIGH level output
voltage;
STANDARD
outputs
VCC = 3.0V; VI = VIH or V
VCC = 4.5V; VI = VIH or V
VCC = 1.2V; VI = VIH or V
VCC = 2.0V; VI = VIH or V
V
OL
evel outpu
;
VCC = 2.7V; VI = VIH or V
p
VCC = 3.0V; VI = VIH or V
VCC = 4.5V; VI = VIH or V
LOW level output
voltage;
OL
STANDARD
outputs
Input leakage
I
I
current
CC
Quiescent supply
current; MSI
I
VCC = 3.0V; VI = VIH or V
VCC = 4.5V; VI = VIH or V
VCC = 5.5V; VI = VCC or GND 1.0 1.0 µA
VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 160 µA
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
IL;
Additional
CC
quiescent supply
current per input
VCC = 2.7V to 3.6V; VI = VCC –0.6V 500 850 µA
∆I
NOTE:
1. All typical values are measured at T
amb
= 25°C.
–IO = 100µA 1.2
–IO = 100µA 1.8 2.0 1.8
–IO = 100µA 2.5 2.7 2.5
–IO = 100µA 2.8 3.0 2.8
–IO = 100µA 4.3 4.5 4.3
–IO = 6mA 2.40 2.82 2.20
–IO = 12mA 3.60 4.20 3.50
IO = 100µA 0
IO = 100µA 0 0.2 0.2
IO = 100µA 0 0.2 0.2
IO = 100µA 0 0.2 0.2
IO = 100µA 0 0.2 0.2
IO = 6mA 0.25 0.40 0.50
IO = 12mA 0.35 0.55 0.65
-40°C to +85°C -40°C to +125°C
MIN TYP
CC
1
MAX MIN MAX
0.7*V
CC
CC
0.3*V
UNIT
CC
V
V
1998 Jun 23
6
Page 7
Philips Semiconductors Product specification
P
CP to Q
0
P
Q
n
Q
n+1
P
MR to Q
n
t
Figure 7
ns
t
Figure 8
ns
R
MR to CP
f
Figure 7
MHz
74LV404012-stage binary ripple counter
AC CHARACTERISTICS
GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 500W
SYMBOL
t
PHL/tPLH
t
PHL/tPLH
t
PHL
W
W
t
rem
max
PARAMETER WAVEFORM
ropagation delay
ropagation delay
to
ropagation delay
Figure 7, 9
Figure 7, 9
Figure 8, 9
Clock pulse width
HIGH to LOW
Master reset pulse
width HIGH
emoval time
Figure 8
Maximum clock
pulse frequency
NOTES:
1. Unless otherwise stated, all typical values are at T
2. Typical value measured at V
3. Typical value measured at V
CC
CC
= 3.3V.
= 5.0V.
amb
CONDITION
VCC(V) MIN TYP1MAX MIN MAX
1.2 – 60 – – –
2.0 – 27 43 – 54
2.7 – 19 31 – 38
3.0 to 3.6 – 16
4.5 to 5.5 – 1
1.2 – 40 – – –
2.0 – 18 29 – 54
2.7 – 13 21 – 38
3.0 to 3.6 – 11
4.5 to 5.5 – 7
1.2 – 55 – – –
2.0 – 27 44 – 54
2.7 – 19 31 – 38
3.0 to 3.6 – 16
4.5 to 5.5 – 11
2.0 35 7 – 41 54
2.7 25 5 – 30 –
3.0 to 3.6 20 4
4.5 to 5.5 15 3
2.0 35 11 – 41 –
2.7 25 9 – 30 –
3.0 to 3.6 20 8
4.5 to 5.5 15 7
1.2 – 10 – – –
2.0 22 5 – 26 –
2.7 16 4 – 19 –
3.0 to 3.6 13 3
4.5 to 5.5 10 2
2.0 14 60 – 12 –
2.7 19 76 – 16 –
3.0 to 3.6 24 94
4.5 to 5.5 36 112
= 25°C.
LIMITS
–40 to +85 °C
2
3
2
3
2
3
2
3
2
3
2
3
2
3
26 – 32
17 – 22
18 – 32
12 – 22
26 – 32
17 – 22
– 24 –
– 18 –
– 24 –
– 18 –
– 15 –
– 12 –
– 20 –
– 30 –
LIMITS
–40 to +125 °C
UNIT
ns
ns
ns
ns
1998 Jun 23
7
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Philips Semiconductors Product specification
74LV404012-stage binary ripple counter
AC WAVEFORMS
VM = 1.5V at VCC 2.7V 3.6V
V
= 0.5V * VCC at V
M
and V
V
OL
output load.
OH
are the typical output voltage drop that occur with the
2.7V and 4.5V
CC
TEST CIRCUIT
V
CC
f
1/
V
I
CP INPUT
GND
V
OH
Q
OUTPUT
n
V
OL
V
M
t
PHL
max
tW
V
M
t
PLH
SV00322
Figure 7. Clock (CP) to output (Qn) propagation delays, the
clock pulse width and the maximum clock pulse frequency
V
I
MR INPUT
CP
GND
INPUT
V
I
t
W
t
rem
PULSE
GENERATOR
V
I
D.U.T.
R
T
V
Test Circuit for switching times
DEFINITIONS
RL = Load resistor
C
= Load capacitance includes jig and probe capacitance
L
RT = Termination resistance should be equal to Z
TEST
t
PLH/tPHL
V
CC
< 2.7V V
2.7–3.6V 2.7V
V
I
CC
Figure 9.Load circuitry for switching times
O
50pF
C
L
of pulse generators.
OUT
RL = 1k
SV00901
GND
V
OH
Qn OUTPUT
GND
t
PHL
SV00908
Figure 8. Master reset (MR) pulse width, the master reset to
output (Q
) propagation delays and the master reset to clock
n
(CP
) removal time
1998 Jun 23
8
Page 9
Philips Semiconductors Product specification
12-stage binary ripple counter
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
74LV4040
1998 Jun 23
9
Page 10
Philips Semiconductors Product specification
12-stage binary ripple counter
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74LV4040
1998 Jun 23
10
Page 11
Philips Semiconductors Product specification
12-stage binary ripple counter
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
74LV4040
1998 Jun 23
11
Page 12
Philips Semiconductors Product specification
12-stage binary ripple counter
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
74LV4040
1998 Jun 23
12
Page 13
Philips Semiconductors Product specification
12-stage binary ripple counter
74LV4040
NOTES
1998 Jun 23
13
Page 14
Philips Semiconductors Product specification
74LV404012-stage binary ripple counter
Data sheet status
Data sheet
status
Objective
specification
Preliminary
specification
Product
specification
Product
status
Development
Qualification
Production
Definition
This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.
This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.
[1]
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For
detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one
or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can
reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.
Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
print code Date of release: 05-96
Document order number: 9397-750-04458
yyyy mmm dd
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