Datasheet 74lv374 DATASHEETS (Philips)

INTEGRATED CIRCUITS

74LV374

Octal D-type flip-flop; positive edge-trigger (3-State)

Product specification Supersedes data of 1996 Feb IC24 Data Handbook

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1997 Mar 20

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger (3-State)

FEATURES

•Wide operating voltage: 1.0 to 5.5V

•Optimized for Low Voltage applications: 1.0 to 3.6V

•Accepts TTL input levels between V

•Typical V

T

amb

•Typical V

T

amb

(output ground bounce)  0.8V @ VCC = 3.3V,

OLP

= 25°C

(output VOH undershoot)  2V @ VCC = 3.3V,

OHV

= 25°C

= 2.7V and VCC = 3.6V

CC

•Common 3-State output enable input

•Output capability: bus driver

•I

category: MSI

CC

QUICK REFERENCE DATA

GND = 0V; T

SYMBOL

t

PHL/tPLH

= 25°C; tr =tf 2.5 ns

amb

Propagation delay CP to Q

PARAMETER CONDITIONS TYPICAL UNIT

n

DESCRIPTION

The 74LV374 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT374.

The 74LV374 is an octal D-type flip–flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE common to all flip-flops.

The eight flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition.

When OE the outputs. When OE impedance OFF-state. Operation of the OE state of the flip-flops.

CL = 15pF VCC = 3.3V

is LOW, the contents of the eight flip-flops is available at

74L V374

) input are

is HIGH, the outputs go to the high

input does not affect the

14 ns

f

max

C

I

C

PD

NOTES:

is used to determine the dynamic power dissipation (PD in µW)

1. C

PD

= CPD  V

P

D

= input frequency in MHz; CL = output load capacity in pF;

f

i

f

= output frequency in MHz; VCC = supply voltage in V;

o

 V

 (C

L

2. The condition is V

Maximum clock frequency 77 MHz Input capacitance 3.5 pF Power dissipation capacitance per flip-flop Notes 1 and 2 25 pF

2

x fi  (CL  V

CC

2

 fo) = sum of the outputs.

CC

= GND to V

I

CC

2

 fo) where:

CC

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #

20-Pin Plastic DIL –40°C to +125°C 74LV374 N 74LV374 N SOT146-1 20-Pin Plastic SO –40°C to +125°C 74LV374 D 74LV374 D SOT163-1 20-Pin Plastic SSOP Type II –40°C to +125°C 74LV374 DB 74LV374 DB SOT339-1

PIN DESCRIPTION

NUMBER

1 OE Output enable input (active-LOW) 2, 5, 6, 9, 12,

15, 16, 19 3, 4, 7, 8, 13,

14, 17, 18 10 GND Ground (0V)

11 CP 20 V

SYMBOL FUNCTION

Q0 to Q7 3-State flip-flop outputs

D0 to D7 Data inputs

Clock input (LOW-to-HIGH, edgetriggered)

CC

Positive supply voltage

FUNCTION TABLE

OPERATING

MODES

Load and read

register

Load register and

disable outputsHH↑↑lh

H = HIGH voltage level h = HIGH voltage level one set-up time prior to the

LOW-to-HIGH CP transition L = LOW voltage level l = LOW voltage level one set-up time prior to the

LOW-to-HIGH CP transition Z = High impedance OFF-state ↑ = LOW–to–HIGH clock transition

INPUTS

OE CP Dn

LL↑↑l

FLIP-FLOPS

h

INTERNAL

L

H

L

H

OUTPUTS

Q0 to Q7

L

H Z

Z

1997 Mar 20

2

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger (3-State)

PIN CONFIGURATION

1 2

Q0

3

D0

4

D1

5

Q1

6

Q2

7

D2

8

D3

9

Q3

10 11

GND

LOGIC SYMBOL (IEEE/IEC)

11 1

3

4

7

8

13

14

17

18

C1

EN1

1D

20OE 19 18 17 16

15 14 13 12

SV00338

SV00340

V Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP

CC

2

5

6

9

12

15

16

19

LOGIC SYMBOL

FUNCTIONAL DIAGRAM

3

4

76

89

13 12

14 15

17 16

18 19

11

1

D

CP

OE

74LV374

11

3

4 7 8

13 14 17 18

0

1

2

3

FF1

to

4

FF8

5

6

7

CP

D0 D1 D2 D3 D4 D5 D6 D7

OE

Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

1

OUTPUTS

SV00339

3-STATE

2 5

6

9 12 15 16 19

2

Q

0

5

Q

1

Q

2

Q

3

Q

4

Q

5

Q

6

Q

7

LOGIC DIAGRAM

D0

CP

OE

1997 Mar 20

SV00341

D1 D2 D3 D4 D5 D6 D7

D

Q

CP

FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8

Q0

D Q

CP

D Q

CP

Q1 Q2 Q3 Q4 Q5 Q6 Q7

D Q

CP

D Q

CP

D Q

CP

D Q

CP

3

D Q

CP

SV00342

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger (3-State)

ABSOLUTE MAXIMUM RATINGS

1, 2

74LV374

In accordance with the Absolute Maximum Rating System (IEC 134) Voltages are referenced to GND (ground = 0V)

SYMBOL

V

CC

±I

IK

±I

OK

DC supply voltage –0.5 to +7.0 V DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA

PARAMETER CONDITIONS RATING UNIT

DC output source or sink current

±I

– standard outputs

O

– bus driver outputs

–0.5V < VO < VCC + 0.5V

25 35

mA

DC VCC or GND current for types with

±I

,

±I

P

GND

CC

T

stg

TOT

–standard outputs –bus driver outputs

Storage temperature range –65 to +150 °C Power dissipation per package

–plastic DIL –plastic mini-pack (SO) –plastic shrink mini-pack (SSOP and TSSOP)

for temperature range: –40 to +125°C above +70°C derate linearly with 12mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K

50 70

750 500 400

mA

mW

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT

V

CC

V

T

amb

tr, t

NOTES:

1. The LV is guaranteed to function down to V

DC supply voltage See Note1 1.0 3.3 5.5 V Input voltage 0 – V

I

Output voltage 0 – V

O

Operating ambient temperature range in free air

Input rise and fall times except for

f

Schmitt-trigger inputs

= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.

CC

See DC and AC characteristics per device

VCC = 1.0V to 2.0V VCC = 2.0V to 2.7V VCC = 2.7V to 3.6V VCC = 3.6V to 5.5V

–40 –40

– – –

– – – –

CC CC

+85

+125

500 200 100

50

V V

°C

ns/V

1997 Mar 20

4

Philips Semiconductors Product specification

V

HIGH l

t

voltage all out uts

V

g

V

voltage; BUS driver

V

LOW l

t

voltage all out uts

V

g

V

voltage; BUS driver

V

I

µA

I

µA

Octal D-type flip-flop; positive edge-trigger (3-State)

DC CHARACTERISTICS FOR THE LV FAMILY

Over recommended operating conditions voltages are referenced to GND (ground = 0V)

SYMBOL P ARAMETER TEST CONDITIONS

MIN TYP

VCC = 1.2V 0.9 0.9

HIGH level Input

IH

voltage

LOW level Input

IL

voltage

V

OH

evel outpu

;

HIGH level output voltage;

OH

STANDARD outputs

HIGH level output

OH

V

OL

;

outputs

evel outpu

;

LOW level output voltage;

OL

STANDARD outputs

LOW level output

OL

I

OZ

;

outputs Input leakage

current 3-State output

OFF-state current Quiescent supply

current; SSI

CC

Quiescent supply current; flip-flops

Quiescent supply current; MSI

CC

Quiescent supply current; LSI

Additional

CC

quiescent supply current per input

∆I

NOTE:

1. All typical values are measured at T

VCC = 2.0V 1.4 1.4 VCC = 2.7 to 3.6V 2.0 2.0 VCC = 4.5 to 5.5V 0.7*V

CC

VCC = 1.2V 0.3 0.3 VCC = 2.0V 0.6 0.6 VCC = 2.7 to 3.6V 0.8 0.8 VCC = 4.5 to 5.5 0.3*V VCC = 1.2V; VI = VIH or V VCC = 2.0V; VI = VIH or V VCC = 2.7V; VI = VIH or V

p

VCC = 3.0V; VI = VIH or V VCC = 4.5V;VI = VIH or V

VCC = 3.0V;VI = VIH or V

VCC = 4.5V;VI = VIH or V VCC = 3.0V;VI = VIH or V

VCC = 4.5V;VI = VIH or V VCC = 1.2V; VI = VIH or V

VCC = 2.0V; VI = VIH or V VCC = 2.7V; VI = VIH or V

p

VCC = 3.0V;VI = VIH or V VCC = 4.5V;VI = VIH or V

VCC = 3.0V;VI = VIH or V

VCC = 4.5V;VI = VIH or V VCC = 3.0V;VI = VIH or V

VCC = 4.5V;VI = VIH or V

–IO = 100µA 1.2

IL;

–IO = 100µA 1.8 2.0 1.8

IL;

–IO = 100µA 2.5 2.7 2.5

IL;

–IO = 100µA 2.8 3.0 2.8

IL;

–IO = 100µA 4.3 4.5 4.3

IL;

–IO = 6mA 2.40 2.82 2.20

IL;

–IO = 12mA 3.60 4.20 3.50

IL;

–IO = 8mA 2.40 2.82 2.20

IL;

–IO = 16mA 3.60 4.20 3.50

IL;

IO = 100µA 0

IL;

IO = 100µA 0 0.2 0.2

IL;

IO = 100µA 0 0.2 0.2

IL;

IO = 100µA 0 0.2 0.2

IL;

IO = 100µA 0 0.2 0.2

IL;

IO = 6mA 0.25 0.40 0.50

IL;

IO = 12mA 0.35 0.55 0.65

IL;

IO = 8mA 0.20 0.40 0.50

IL;

IO = 16mA 0.35 0.55 0.65

IL;

VCC = 5.5V; VI = VCC or GND 1.0 1.0 µA VCC = 5.5V; VI = VIH or V

VO = VCC or GND

IL;

VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 40

VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 80

VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 160

VCC = 5.5V; VI = VCC or GND; IO = 0 500 1000

VCC = 2.7V to 3.6V; VI = VCC –0.6V 500 850 µA

= 25°C.

amb

74LV374

LIMITS

-40°C to +85°C -40°C to +125°C

1

MAX MIN MAX

0.7*V

CC

5 10 µA

0.3*V

UNIT

CC

V

1997 Mar 20

5

Philips Semiconductors Product specification

P

CP to Qn

P

OE to Qn

P

OE to Qn

Clock

idth

HIGH or LOW

t

Figure 3

ns

t

Figure 3

ns

Maxi

k

ulse frequency

Octal D-type flip-flop; positive edge-trigger (3-State)

AC CHARACTERISTICS

GND = 0V; tr = tf = 2.5ns; CL = 50pF; RL = 500Ω

SYMBOL

t

PHL/tPLH

t

PZH/tPZL

t

PHZ/tPLZ

t

W

su

h

f

max

PARAMETER WAVEFORM

ropagation delay

pulse w

Figure 1

Figure 2

Figure 1

Set-up time Dn to CP

Hold time Dn to CP

mum cloc

p

Figure 2

NOTE:

1. Unless otherwise stated, all typical values are at T

2. Typical value measured at V

3. Typical value measured at V

= 3.3V.

CC

= 5.0V.

CC

amb

CONDITION

VCC(V) MIN TYP MAX MIN MAX

1.2 – 90 – – –

2.0 – 31 39 – 49

2.7 – 23 29 – 36

3.0 to 3.6 – 17

4.5 to 5.5 – – 19 – 24

1.2 – 75 – – –

2.0 – 26 34 – 43

2.7 – 19 25 – 31

3.0 to 3.6 – 14

4.5 to 5.5 – – 17 – 21

1.2 – 80 – – –

2.0 – 29 39 – 48

2.7 – 22 29 – 36

3.0 to 3.6 – 17

4.5 to 5.5 – – 20 – 24

2.0 34 12 – 41 –

2.7 25 9 – 30 –

3.0 to 3.6 20 7

1.2 – 25 – – –

2.0 22 9 – 26 –

2.7 16 6 – 19 –

3.0 to 3.6 13 5

1.2 – –10 – – –

2.0 5 –3 – 5 –

2.7 5 –2 – 5 –

3.0 to 3.6 5 –2

2.0 15 40 – 12 –

2.7 19 58 – 16 –

3.0 to 3.6 24 70

= 25°C.

LIMITS

–40 to +85 °C

2

74LV374

LIMITS

–40 to +125 °C

23 – 29

20 – 25

24 – 29

– 24 –

– 15 –

– 5 –

– 20 –

UNIT

ns

MHz

1997 Mar 20

6

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger (3-State)

AC WAVEFORMS

VM = 1.5V at VCC  2.7V  3.6V V

= 0.5V * VCC at V

M

and V

V

OL

output load.

CP INPUT

OUTPUT

Qn

are the typical output voltage drop that occur with the

OH

Figure 1. Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, output transition

times and the maximum clock pulse frequency

 2.7V and  4.5V

CC

1/f

max

V

M

t

W

t

PHL

90%

V

M

10%

t

THL

V

CP INPUT

GND

V

INPUT

D

n

GND

t

PLH

t

TLH

V

OH

Qn OUTPUT V

V

OL

NOTE: the shaded areas indicate when the input is permitted to change for predictable output performance.

Figure 3. Waveforms showing the data set-up and hold times

SV00343

NOTE:

The shaded areas indicate when the input is permitted to change for predictable output performance.

I

(1)

V

M

t

su

t

h

I

V

M

for the Dn input to the CP input

M

74LV374

t

su

t

h

SV00345

V

I

OE INPUT

GND

V

OUTPUT LOW-to-OFF OFF-to-LOW

V

OUTPUT

HIGH-to-OFF OFF-to-HIGH

GND

CC

OL

OH

V

M

t

PLZ

t

PHZ

outputs

enabled

t

PZL

V

X

t

PZH

V

Y

outputs

disabled

M

V

M

outputs enabled

SV00344

Figure 2. Waveforms showing the 3-state enable and disable

times

1997 Mar 20

7

Philips Semiconductors Product specification

Octal D-type flip-flop; positive edge-trigger (3-State)

TEST CIRCUIT

90%

NEGATIVE PULSE

POSITIVE PULSE

10%

RL = Load resistor C

= Load capacitance includes jig and probe capacitance

L

= Termination resistance should be equal to Z

R

T

pulse generators.

V

PULSE

GENERATOR

l

R

T

Test Circuit for Outputs

SWITCH POSITION

TEST S

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

V

S1

GND

1

V

cc

D.U.T.

V

< 2.7V

2.7–3.6V ≥ 4.5 V

CC

S

1

V

S1

Open

GND

V

O

CL= 50pF

V

I

V

CC

2.7V V

CC

RL = 1k

R

V

2  V 2  V 2  V

S1

L

= 1k

CC CC CC

74LV374

t

W

V

M

10% 10%

t

(t

)

THL

f

t

(tr)t

TLH

90% 90%

V

M

t

W

V

M

V

M

VM = 1.5V

Input Pulse Definition

DEFINITIONS

90%

10%

t

TLH

THL

(tr)

(tf)

OUT

V

I

0V

V

I

0V

of

Figure 4. Load circuitry for switching times

SY00044

1997 Mar 20

8

Philips Semiconductors Product specification

74LV374Octal D-type flip-flop; positive edge-trigger (3-State)

DIP20: plastic dual in-line package; 20 leads (300 mil) SOT146-1

1997 Mar 20

9

Philips Semiconductors Product specification

74LV374Octal D-type flip-flop; positive edge-trigger (3-State)

SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1

1997 Mar 20

10

Philips Semiconductors Product specification

74LV374Octal D-type flip-flop; positive edge-trigger (3-State)

SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT339-1

1997 Mar 20

11

Philips Semiconductors Product specification

74LV374Octal D-type flip-flop; positive edge-trigger (3-State)

DEFINITIONS

Data Sheet Identification Product Status Definition

Objective Specification

Preliminary Specification

Product Specification

Formative or in Design

Preproduction Product

Full Production

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

LIFE SUPPORT APPLICA TIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected

to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.

 Copyright Philips Electronics North America Corporation 1997

print code Date of release: 05-96 Document order number: 9397-750-04448

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