Page 1
INTEGRATED CIRCUITS
74LV175
Quad D-type flip-flop with reset;
positive-edge trigger
Product specification
Supersedes data of 1997 Feb 19
IC24 Data Handbook
1998 May 20
Page 2
Philips Semiconductors Product specification
74L V175Quad D-type flip-flop with reset; positive-edge trigger
FEA TURES
•Optimized for low voltage applications: 1.0 to 3.6 V
•Accepts TTL input levels between V
•Typical V
T
amb
•Typical V
T
amb
(output ground bounce) < 0.8 V at V
OLP
= 25°C
(output VOH undershoot) > 2 V at V
OHV
= 25°C
= 2.7 V and V
CC
CC
CC
CC
= 3.3 V,
= 3.3 V,
•Four edge-triggered D flip-flops
•Output capability: standard
•I
category: MSI
CC
QUICK REFERENCE DATA
GND = 0 V; T
= 25°C; tr = t
amb
SYMBOL
Propagation delay
t
PHL/tPLH
f
max
C
I
C
PD
CP to Q
MR to Q
Maximum clock frequency 77 MHz
Input capacitance 3.5 pF
Power dissipation capacitance per flip-flop
NOTE:
is used to determine the dynamic power dissipation (PD in µW)
1. C
PD
P
= CPD V
D
= input frequency in MHz; CL = output load capacitance in pF;
f
i
f
= output frequency in MHz; VCC = supply voltage in V;
o
V
(C
L
2
fi (CL V
CC
2
fo) = sum of the outputs.
CC
≤ 2.5 ns
f
PARAMETER CONDITIONS TYPICAL UNIT
Q
n,
n
Q
n,
n
2
fo) where:
CC
= 3.6 V
CL = 15 pF;
VCC = 3.3 V
VCC = 3.3 V
VI = GND to V
DESCRIPTION
The 74LV175 is a low-voltage Si-gate CMOS device and is pin and
function compatible with 74HC/HCT175.
The 74LV175 has four edge-triggered, D-type flip-flops with
individual D inputs and both Q and Q
(CP) and master reset (MR
) inputs load and reset (clear) all flip-flops
simultaneously .
The register is fully edge-triggered. The state of each D input, one
set-up time prior to the LOW-to-HIGH clock transition, is transferred
to the corresponding output (Q
All Qn outputs will be forced LOW independently of clock or data
inputs by a LOW voltage level on the MR
The device is useful for applications where both the true and
complement outputs are required and the clock and master reset are
common to all storage elements.
1
CC
outputs. The common clock
) of the flip-flop.
n
input.
16
14
32 pF
ns
ns
ORDERING INFORMATION
PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #
16-Pin Plastic DIL –40°C to +125°C 74LV175 N 74LV175 N SOT38-4
16-Pin Plastic SO –40°C to +125°C 74LV175 D 74LV175 D SOT109-1
16-Pin Plastic SSOP Type II –40°C to +125°C 74LV175 DB 74LV175 DB SOT338-1
16-Pin Plastic TSSOP Type I –40°C to +125°C 74LV175 PW 74LV175PW DH SOT403-1
PIN CONFIGURATION
1
MR
2
Q
0
3
Q
0
4
D
0
5
D
1
6
Q
1
7
Q
1
8
GND
1998 May 20 853–1926 19422
16
15
14
13
12
11
10
9
SV00596
V
Q
Q
D
D
Q
Q
CP
CC
3
3
3
2
2
2
PIN DESCRIPTION
PIN
NUMBER
1 MR Master reset input (active LOW)
2, 7, 10, 15 Q0 to Q3Flip-flop outputs
3, 6, 11, 14 Q0 to Q3Complementary flip-flop outputs
4, 5, 12, 13 D0 to D3Data inputs
8 GND Ground (0 V)
9 CP
16 V
2
SYMBOL FUNCTION
Clock input
(LOW-to-HIGH, edge-triggered)
CC
Positive supply voltage
Page 3
Philips Semiconductors Product specification
OPERATING MODES
74LV175Quad D-type flip-flop with reset; positive-edge trigger
LOGIC SYMBOL (IEEE/IEC)
9
C1
1
R
4
1D
5
12
13
LOGIC SYMBOL
CP
D
4
0
D
5
1
D
12
13
2
D
3
MR
SV00601
9
1
Q
0
Q
0
Q
1
Q
1
Q
2
Q
2
Q
3
Q
3
SV00600
FUNCTIONAL DIAGRAM
Q
4
D
0
2
3
7
6
10
11
15
14
2
3
7
6
10
11
15
14
5
D
1
FF0
12
13
1
9
to
D
FF3
2
D
3
CP
MR
Q
Q
Q
Q
Q
Q
Q
0
0
1
1
2
2
3
3
SV00602
2
3
7
6
10
11
15
14
LOGIC DIAGRAM
MR
CP
D
0
Q
D
FF0 FF2FF1 FF3
CP
Q QQ Q
R
D
Q
D
1
R
D
Q
0
0
Q
D
2
QQ Q
DD D
CPCP CP
R
D
Q
1
1
Q
D
3
R
D
Q
2
2
Q3Q
3
SV00603
FUNCTION TABLE
INPUTS OUTPUTS
MR CP D
n
Reset (clear) L X X L H
Load ‘1’ H ↑ h H L
Load ‘0’ H ↑ l L H
NOTES:
H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition
L = LOW voltage level
I = LOW voltage level level one set-up time prior to the LOW-to-HIGH clock transition
↑ = LOW-to-HIGH clock transition
X = don’t care
Q
n
Q
n
1998 May 20
3
Page 4
Philips Semiconductors Product specification
P
mW
74LV175Quad D-type flip-flop with reset; positive-edge trigger
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT
V
V
V
T
amb
tr, t
NOTE:
1. The LV is guaranteed to function down to V
DC supply voltage See Note 1 1.0 3.3 3.6 V
CC
Input voltage 0 – V
I
Output voltage 0 – V
O
Operating ambient temperature range in free air
Input rise and fall times
f
CC
See DC and AC
characteristics
VCC = 1.0V to 2.0V
VCC = 2.0V to 2.7V
V
= 2.7V to 3.6V
CC
= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V.
–40
–40
–
–
–
–
–
–
–
CC
CC
+85
+125
500
200
100
V
V
°C
ns/V
ABSOLUTE MAXIMUM RATINGS
1, 2
In accordance with the Absolute Maximum Rating System (IEC 134).
Voltages are referenced to GND (ground = 0V).
SYMBOL
V
CC
±I
IK
±I
OK
±I
O
±I
GND
±I
CC
T
stg
DC supply voltage –0.5 to +4.6 V
DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA
DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA
DC output source or sink current
– standard outputs
DC VCC or GND current for types with
,
–standard outputs
Storage temperature range –65 to +150 °C
PARAMETER CONDITIONS RATING UNIT
–0.5V < VO < VCC + 0.5V 25 mA
50 mA
Power dissipation per package for temperature range: –40 to +125°C
–plastic DIL above +70°C derate linearly with 12mW/K 750
tot
–plastic mini-pack (SO) above +70°C derate linearly with 8 mW/K 500
–plastic shrink mini-pack (SSOP and TSSOP) above +60°C derate linearly with 5.5 mW/K 400
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
1998 May 20
4
Page 5
Philips Semiconductors Product specification
voltage
voltage
V
V
V
V
74LV175Quad D-type flip-flop with reset; positive-edge trigger
DC CHARACTERISTICS FOR THE LV FAMILY
Over recommended operating conditions. V oltages are referenced to GND (ground = 0V).
LIMITS
SYMBOL P ARAMETER TEST CONDITIONS
VCC = 1.2V 0.9 0.9
IH
HIGH level Input
V
VCC = 2.0V 1.4 1.4
VCC = 2.7 to 3.6V 2.0 2.0
VCC = 1.2V 0.3 0.3
IL
LOW level Input
V
VCC = 2.0V 0.6 0.6
VCC = 2.7 to 3.6V 0.8 0.8
HIGH level output
OH
voltage; all outputs
VCC = 1.2V; VI = VIH or V
VCC = 2.0V; VI = VIH or V
VCC = 2.7V; VI = VIH or V
VCC = 3.0V; VI = VIH or V
IL;
IL;
IL;
IL;
HIGH level output
OH
voltage;
STANDARD
VCC = 3.0V; VI = VIH or V
IL;
V
outputs
LOW level output
OL
voltage; all outputs
VCC = 1.2V; VI = VIH or V
VCC = 2.0V; VI = VIH or V
VCC = 2.7V; VI = VIH or V
VCC = 3.0V; VI = VIH or V
IL;
IL;
IL;
IL;
LOW level output
OL
voltage;
STANDARD
VCC = 3.0V; VI = VIH or V
IL;
V
outputs
Input leakage
I
I
current
CC
Quiescent supply
current; MSI
I
VCC = 3.6V; VI = VCC or GND 1.0 1.0 µA
VCC = 3.6V; VI = VCC or GND; IO = 0 20.0 160 µA
Additional
CC
quiescent supply
current per input
VCC = 2.7V to 3.6V; VI = VCC – 0.6V 500 850 µA
∆I
NOTE:
1. All typical values are measured at T
amb
= 25°C.
–IO = 100µA 1.2
–IO = 100µA 1.8 2.0 1.8
–IO = 100µA 2.5 2.7 2.5
–IO = 100µA 2.8 3.0 2.8
–IO = 6mA 2.40 2.82 2.20 V
IO = 100µA 0
IO = 100µA 0 0.2 0.2
IO = 100µA 0 0.2 0.2
IO = 100µA 0 0.2 0.2
IO = 6mA 0.25 0.40 0.50 V
-40°C to +85°C -40°C to +125°C
MIN TYP
1
MAX MIN MAX
UNIT
V
V
1998 May 20
5
Page 6
Philips Semiconductors Product specification
CONDITION
t
gy
Figures 1
ns
t
gy
Figures 2
ns
HIGH or LOW
width LOW
t
Figures 2
ns
t
Figures 3
ns
t
Figures 3
ns
y
ulse frequency
74LV175Quad D-type flip-flop with reset; positive-edge trigger
AC CHARACTERISTICS
GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = K
LIMITS
SYMBOL PARAMETER WAVEFORM
PHL/tPLH
PHL/tPLH
t
w
t
w
rem
su
h
f
max
Propagation delay
CP to Q
Q
n,
n
Propagation delay
MR to Q
Q
n,
n
Clock pulse width
HIGH or LOW
Master reset pulse
width LOW
Removal time
MR to CP
Set-up time
Dn to CP
Hold time
Dn to CP
Maximum clock
pulse frequenc
Figures 1
Figures 2
Figures 1
NOTES:
1. Unless otherwise stated, all typical values are measured at T
2. Typical values are measured at V
= 3.3 V.
CC
VCC(V) MIN TYP
1.2 100
2.0 34 65 77
2.7 25 48 56
3.0 to 3.6 19
1.2 90
2.0 31 58 70
2.7 23 43 51
3.0 to 3.6 17
2.0 34 14 41
2.7 25 10 30
3.0 to 3.6 20 8
2.0 34 14 41
2.7 25 9 30
3.0 to 3.6 20 7
1.2 –60
2.0 5 –20 5
2.7 5 –15 5
3.0 to 3.6 5 –12
1.2 5
2.0 22 2 26
2.7 16 2 19
3.0 to 3.6 13 1
1.2 –5
2.0 5 –1 5
2.7 5 0 5
3.0 to 3.6 5 0
2.0 14 40 12
2.7 19 58 16
3.0 to 3.6 24 70
= 25°C.
amb
–40 to +85 °C –40 to +125 °C
1
MAX MIN MAX
2
38 45
2
34 41
2
2
2
2
2
2
24
24
5
15
5
20
UNIT
ns
ns
MHz
1998 May 20
6
Page 7
Philips Semiconductors Product specification
74LV175Quad D-type flip-flop with reset; positive-edge trigger
AC WAVEFORMS
VM = 1.5 V at VCC ≥ 2.7 V;
= 0.5 V × VCC at VCC < 2.7 V .
V
M
V
and VOH are the typical output voltage drop that occur with the
OL
output load.
1/f
max
t
W
V
M
V
M
t
t
PLH
PHL
CP INPUT
GND
V
Q
OUTPUT
n
V
V
Qn OUTPUT
V
V
I
V
M
t
t
PHL
PLH
OH
OL
OH
OL
SV00604
Figure 1. Clock (CP) to outputs (Qn, Qn) propagation delays,
the clock pulse width and the maximum clock pulse frequency.
V
I
CP INPUT
GND
V
I
Dn INPUT
GND
V
OH
OUTPUT
Q
n
V
OL
V
OH
OUTPUT
Q
n
V
OL
The shaded areas indicate when the input is permitted to change for
predictable output performance.
V
M
t
su
t
h
V
M
V
M
V
M
t
su
t
h
SV00606
V
I
MR INPUT
GND
CP INPUT
GND
V
OH
Qn OUTPUT
VOL
V
OH
Q
OUTPUT
n
V
OL
V
I
V
M
t
W
t
PHL
V
M
t
PLH
V
M
Figure 2. Master reset (MR) pulse width,
the master reset to outputs (Q
, Qn) propagation delay
n
and master reset to clock (CP) removal time.
Figure 3. Data set-up and hold times for data input (Dn).
TEST CIRCUIT
V
t
rem
V
M
PULSE
GENERATOR
V
I
R
T
Test Circuit for switching times
DEFINITIONS
RL = Load resistor
C
= Load capacitance includes jig and probe capacitance
L
SV00605
RT = Termination resistance should be equal to Z
TEST
t
PLH/tPHL
< 2.7V V
2.7–3.6V 2.7V
Figure 4. Load circuitry for switching times.
CC
V
O
D.U.T.
50pF
C
L
of pulse generators.
OUT
V
CC
V
I
CC
RL = 1k
SV00901
1998 May 20
7
Page 8
Philips Semiconductors Product specification
Quad D-type flip-flop with reset; positive-edge trigger
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
74LV175
1998 May 20
8
Page 9
Philips Semiconductors Product specification
Quad D-type flip-flop with reset; positive-edge trigger
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74LV175
1998 May 20
9
Page 10
Philips Semiconductors Product specification
Quad D-type flip-flop with reset; positive-edge trigger
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
74LV175
1998 May 20
10
Page 11
Philips Semiconductors Product specification
Quad D-type flip-flop with reset; positive-edge trigger
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
74LV175
1998 May 20
11
Page 12
Philips Semiconductors Product specification
Quad D-type flip-flop with reset; positive-edge trigger
NOTES
74LV175
1998 May 20
12
Page 13
Philips Semiconductors Product specification
Quad D-type flip-flop with reset; positive-edge trigger
DEFINITIONS
74LV175
Data Sheet Identification Product Status Definition
Objective Specification
Preliminary Specification
Product Specification
Formative or in Design
Preproduction Product
Full Production
This data sheet contains the design target or goal specifications for product development. Specifications
may change in any manner without notice.
This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips
Semiconductors reserves the right to make changes at any time without notice in order to improve design
and supply the best possible product.
This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes
at any time without notice, in order to improve design and supply the best possible product.
Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products,
including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright,
or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask
work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes
only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing
or modification.
LIFE SUPPORT APPLICA TIONS
Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices,
or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected
to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips
Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully
indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.
Philips Semiconductors
811 East Arques Avenue
Copyright Philips Electronics North America Corporation 1998
All rights reserved. Printed in U.S.A.
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone 800-234-7381
print code Date of release: 05-96
Document order number: 9397-750-04434
1998 May 20
13
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