Datasheet 74lv161 DATASHEETS (Philips)

INTEGRATED CIRCUITS

74LV161

Presettable synchronous 4-bit binary counter; asynchronous reset

Product specification Supersedes data of 1997 Feb 12 IC24 Data Handbook

 

1997 May 15

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary counter; asynchronous reset

FEA TURES

•Optimized for low voltage applications: 1.0 to 3.6 V

•Accepts TTL input levels between V

•Typical V

T

amb

•Typical V

T

amb

(output ground bounce) < 0.8 V at V

OLP

= 25°C

(output VOH undershoot) > 2 V at V

OHV

= 25°C

= 2.7 V and V

CC

•Asynchronous reset

•Synchronous counting and loading

•Two count enable inputs for n-bit cascading

•Positive-edge triggered clock

•Output capability: standard

•I

category: MSI

CC

= 3.6 V

CC

= 3.3 V,

DESCRIPTION

The 74LV161 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT161.

The 74LV161 is a synchronous presettable binary counter which features an internal look-head carry and can be used for high-speed counting. Synchronous operation is provided by having all flip-flops clocked simultaneously on the positive-going edge of the clock (CP). The outputs (Q LOW level. A LOW level at the parallel enable input (PE counting action and causes the data at the data inputs (D loaded into the counter on the positive-going edge of the clock (providing that the set-up and hold time requirements for PE Preset takes place regardless of the levels at count enable inputs (CEP and CET). A low level at the master reset input (MR four outputs of the flip-flops (Q levels at CP , PE asynchronous clear function).

The look-ahead carry simplifies serial cascading of the counters. Both count enable inputs (CEP and CET) must be HIGH to count. The CET input is fed forward to enable the terminal count output (TC). The TC output thus enabled will produce a HIGH output pulse of a duration approximately equal to a HIGH level output of Q pulse can be used to enable the next cascading stage. The maximum clock frequency for the cascaded counters is determined by the CP to TC propagation delay and CEP to CP set-up time, according to the following formula:

f



max

to Q3) of the counters may be preset to a HIGH or

0

to Q3) to LOW level regardless of the

0

, CET and CEP inputs (thus providing an

1

(CP to TC) tsu(CEP to CP)

tp

(max)

74L V161

) disables the

to D3) to be

0

are met).

) sets all

. This

0

QUICK REFERENCE DATA

GND = 0 V; T

= 25°C; tr = t

amb

SYMBOL

Propagation delay CP to Q

t

PHL/tPLH

CP to TC

to Q

MR MR to TC

CET to TC f C C

max

I PD

Maximum clock frequency 77 MHz

Input capacitance 3.5 pF

Power dissipation capacitance per gate VI = GND to V

NOTES:

is used to determine the dynamic power dissipation (PD in µW)

1. C

PD

= CPD  V

P

D

f

= input frequency in MHz; CL = output load capacity in pF;

i

= output frequency in MHz; VCC = supply voltage in V;

f

o

 V

 (C

L

2

 fi  (CL  V

CC

2

 fo) = sum of the outputs.

CC

≤ 2.5 ns

f

PARAMETER CONDITIONS TYPICAL UNIT

CL = 15 pF;

= 3.3 V

V

n

CC

15 18 15 17

9

2

 fo) where:

CC

1

25 pF

ns

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #

16-Pin Plastic DIL –40°C to +125°C 74LV161 N 74LV161 N SOT38-4 16-Pin Plastic SO –40°C to +125°C 74LV161 D 74LV161 D SOT109-1 16-Pin Plastic SSOP Type II –40°C to +125°C 74LV161 DB 74LV161 DB SOT338-1 16-Pin Plastic TSSOP Type I –40°C to +125°C 74LV161 PW 74LV161PW DH SOT403-1

1997 May 15 853–1917 18039

2

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary counter; asynchronous reset

PIN CONFIGURATION

1

MR

2

CP

3

D

0

4

D

1

5

D

2

6

D

3

7

CEP

8

GND

PIN DESCRIPTION

NUMBER

1 MR Asynchronous master reset (active LOW) 2 CP 3, 4, 5, 6 D0 to D3Data inputs

7 CEP Count enable inputs 8 GND Ground (0 V) 9 PE Parallel enable input (active LOW) 10 CET Count enable carry input 14, 13, 12,

11 15 TC Terminal count output 16 V

SYMBOL FUNCTION

Clock input (LOW-to-HIGH, edge-triggered)

Q0 to Q3Flip-flop outputs

CC

Positive supply voltage

V

16

CC

15

TC

14

Q

0

13

Q

1

12

Q

2

11

Q

3

10

CET

9

PE

SV00569

LOGIC SYMBOL

D

3

4

5

6

9

D

PE

0

1

2

3

FUNCTIONAL DIAGRAM

D

0

9

PE

CET

10

7

CEP

CP

2 1

MR

PARALLEL LOAD

CIRCUITRY

COUNTER

Q

0

14

15

TC

CPCETCEP

21071

D

1

BINARY

Q

1

Q

MR

6115124133 D

2

3

Q

2

3

74LV161

14

0

13

1

12

2

11

3

TC

SV00570

15

SV00572

LOGIC SYMBOL (IEEE/IEC)

R M1 G3

G4

1, 2D

CTR4

C2/1,3,4+

4CT = 15

1 9 7

10

2

3

4 5

6

1997 May 15

14

13

12 11

15

SV00571

3

Philips Semiconductors Product specification

OPERATING MODES

Parallel load

Hold (do nothing)

Presettable synchronous 4-bit binary counter; asynchronous reset

FUNCTION TABLE

INPUTS OUTPUTS

MR CP CEP CET PE D

Reset (clear) L X X X X X L L

H ↑ X X I I L L H ↑ X X I h H *

Count H ↑ h h h X Count *

H X I X h X q H X X I h X q

NOTES:

* = The TC output is HIGH when CET is HIGH and the counter is at terminal count (HHHH) H = HIGH voltage level h = HIGH voltage level one set-up time prior to the LOW-to-HIGH clock transition L = LOW voltage level I = LOW voltage level level one set-up time prior to the LOW-to-HIGH clock transition q = lower case letters indicate the state of the referenced output one set-up time prior to the LOW-to-HIGH clock transition X = don’t care ↑ = LOW-to-HIGH clock transition

STATE DIAGRAM

0 1 2 3 4

15

14

13

12

5

6

7

891011

SV00573

TYPICAL TIMING SEQUENCE

MR

PE D

0

D

1

D

2

D

3

CP CEP CET

Q

0

Q

1

Q

2

Q

3

TC

reset preset

Typical timing sequence: reset outputs to zero; preset to binary twelve; count to thirteen, fourteen, fifteen, zero, on and two; inhibit.

13 14 15 0 1 2

12

n

count inhibit

74LV161

Q

n

n n

TC

* L

SV00574

1997 May 15

4

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary counter; asynchronous reset

LOGIC DIAGRAM

CET

CEP

PE

D

0

D

1

74LV161

D

2

D

3

CP

MR

FF0 FF1 FF2 FF3

QQQQ

DDDD CP

Q

R

D

Q

0

CP CP CP

QQQ

R

D

Q

1

R

D

Q

2

R

D

Q3TC

SV00575

1997 May 15

5

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary counter; asynchronous reset

ABSOLUTE MAXIMUM RATINGS

In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0 V).

SYMBOL

V

I

DC supply voltage –0.5 to +4.6 V

CC

DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA

IK

DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA

OK

DC output source or sink current

I

– standard outputs

O

– bus driver outputs DC VCC or GND current for types with

I

,

I

GND

T

– standard outputs – bus driver outputs

CC

Storage temperature range –65 to +150 °C

stg

Power dissipation per package

P

TOT

– plastic DIL – plastic mini-pack (SO) – plastic shrink mini-pack (SSOP and TSSOP)

NOTES:

1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability .

2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

PARAMETER CONDITIONS RATING UNIT

1, 2

–0.5V < VO < VCC + 0.5V

for temperature range: –40 to +125°C above +70°C derate linearly with 12 mW/K above +70°C derate linearly with 8 mW/K above +60°C derate linearly with 5.5 mW/K

74LV161

25 35

50 70

750 500 400

mA

mW

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNIT

V

T

amb

tr, t

NOTE:

1. The LV is guaranteed to function down to V

DC supply voltage See Note 1 1.0 3.3 3.6 V

CC

Input voltage 0 – V

I

Output voltage 0 – V

O

Operating ambient temperature range in free air

Input rise and fall times except for

f

Schmitt-trigger inputs

CC

See DC and AC

characteristics per device

VCC = 1.0V to 2.0V

= 2.0V to 2.7V

V

CC

= 2.7V to 3.6V

V

CC

= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 3.6V.

–40 –40

– – –

CC CC

+85

+125

500 200 100

ns/V

V V

°C

1997 May 15

6

Philips Semiconductors Product specification

voltage

V

A

I

A

Presettable synchronous 4-bit binary counter; asynchronous reset

DC ELECTRICAL CHARACTERISTICS

Over recommended operating conditions. V oltages are referenced to GND (ground = 0 V).

SYMBOL P ARAMETER TEST CONDITIONS

VCC = 1.2 V 0.9 0.9

IH

HIGH level Input

V

VCC = 2.0 V 1.4 1.4 VCC = 2.7 to 3.6 V 2.0 2.0 VCC = 1.2 V 0.3 0.3

IL

LOW level Input

V

VCC = 2.0 V 0.6 0.6 VCC = 2.7 to 3.6 V 0.8 0.8

HIGH level output

OH

voltage; all outputs

VCC = 1.2 V; VI = VIH or V VCC = 2.0 V; VI = VIH or V VCC = 2.7 V; VI = VIH or V VCC = 3.0 V; VI = VIH or V

IL; IL; IL; IL;

HIGH level output

OH

voltage; STANDARD

VCC = 3.0 V; VI = VIH or V

IL;

V

outputs HIGH level output

V

voltage; BUS driver

OH

outputs

LOW level output

OL

voltage; all outputs

VCC = 3.0 V; VI = VIH or V

VCC = 1.2 V; VI = VIH or V VCC = 2.0 V; VI = VIH or V VCC = 2.7 V; VI = VIH or V VCC = 3.0 V; VI = VIH or V

IL;

IL; IL; IL; IL;

LOW level output

OL

voltage; STANDARD

VCC = 3.0 V; VI = VIH or V

IL;

V

outputs LOW level output

V

I

voltage; BUS driver

OL

outputs Input leakage

I

current 3-State output

OZ

OFF-state current Quiescent supply

current; SSI Quiescent supply

current; flip-flops

CC

Quiescent supply current; MSI

Quiescent supply current; LSI

VCC = 3.0 V; VI = VIH or V

IL;

VCC = 3.6 V; VI = VCC or GND 1.0 1.0 µA VCC = 3.6 V; VI = VIH or V

VO = VCC or GND

IL;

VCC = 3.6V; VI = VCC or GND; IO = 0 20.0 40

VCC = 3.6V; VI = VCC or GND; IO = 0 20.0 80

VCC = 3.6 V; VI = VCC or GND; IO = 0 20.0 160

VCC = 3.6 V; VI = VCC or GND; IO = 0 500 1000

Additional

CC

quiescent supply current per input

VCC = 2.7 V to 3.6 V; VI = VCC – 0.6 V 500 850 µA

∆I

NOTE:

1. All typical values are measured at T

amb

= 25°C.

–IO = 100µA 1.2 –IO = 100µA 1.8 2.0 1.8 –IO = 100µA 2.5 2.7 2.5 –IO = 100µA 2.8 3.0 2.8

–IO = 6mA 2.40 2.82 2.20 V

–IO = 8mA 2.40 2.82 2.20 V

IO = 100µA 0 IO = 100µA 0 0.2 0.2 IO = 100µA 0 0.2 0.2 IO = 100µA 0 0.2 0.2

IO = 6mA 0.25 0.40 0.50 V

IO = 8mA 0.20 0.40 0.50 V

-40°C to +85°C -40°C to +125°C

MIN TYP

LIMITS

1

MAX MIN MAX

5 10 µA

74LV161

UNIT

V

µ

1997 May 15

7

Philips Semiconductors Product specification

CONDITION

t

gy

Figures 1, 6

ns

t

gy

Figures 1, 6

ns

t

gy

Figures 2, 6

ns

t

gy

Figures 2, 6

ns

t

gy

Figures 1, 6

ns

Clock

idth

HIGH or LOW

Mast

idth

LOW

t

Figures 2, 6

ns

t

Figures 4, 6

ns

t

Figures 4, 6

ns

t

Figures 5, 6

ns

Presettable synchronous 4-bit binary counter; asynchronous reset

AC CHARACTERISTICS

GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ

SYMBOL PARAMETER WAVEFORM

VCC(V) MIN TYP

1.2 95

PHL/tPLH

t

w

t

w

rem

su

Propagation delay CP to Q

n

Propagation delay CP to TC

Propagation delay MR to Q

n

Propagation delay MR to TC

Propagation delay CET to TC

pulse w

er reset w

Removal time MR to CP

Set-up time Dn to CP

Set-up time PE to CP

Set-up time CEP, CET to CP

;

Figures 2, 6

2.0 32 61 75

2.7 24 45 55

3.0 to 3.6 18

1.2 115

2.0 39 75 90

2.7 29 55 66

3.0 to 3.6 22

1.2 95

2.0 32 61 75

2.7 24 45 55

3.0 to 3.6 18

1.2 105

2.0 36 68 82

2.7 26 50 60

3.0 to 3.6 20

1.2 55

2.0 19 36 44

2.7 14 26 33

3.0 to 3.6 10

2.0 34 10 41

2.7 25 8 30

3.0 to 3.6 20 6

2.0 34 14 41

2.7 25 10 30

3.0 to 3.6 20 8

1.2 25

2.0 22 9 26

2.7 16 6 19

3.0 to 3.6 13 5

1.2 25

2.0 22 9 26

2.7 16 6 19

3.0 to 3.6 13 5

1.2 30

2.0 22 10 26

2.7 16 8 19

3.0 to 3.6 13 6

1.2 30

2.0 22 10 26

2.7 16 8 19

3.0 to 3.6 13 6

74LV161

LIMITS

–40 to +85 °C –40 to +125 °C

1

MAX MIN MAX

2

36 44

2

44 53

2

36 44

2

40 48

2

21 26

2

24

15

UNIT

ns

1997 May 15

8

Philips Semiconductors Product specification

CONDITION

t

D

CEP, CET to

Figures 4

6

ns

Maxi

k

ulse frequency

Presettable synchronous 4-bit binary counter; asynchronous reset

AC ELECTRICAL CHARACTERISTICS (Continued)

SYMBOL PARAMETER WAVEFORM

VCC(V) MIN TYP

Hold time

–

Figures 1, 6

f

max

h

CP

, PE,

n

mum cloc

p

NOTES:

1. Unless otherwise stated, all typical values are measured at T

2. Typical values are measured at V

= 3.3 V.

CC

AC WAVEFORMS

VM = 1.5 V at VCC ≥ 2.7 V; V

= 0.5 × VCC at VCC < 2.7 V;

M

V

and VOH are the typical output voltage drop that occur with the output load.

OL

1/f

max

V

I

CP INPUT

GND

V

OH

Qn, TC

OUTPUT

V

OL

Figure 1. Clock (CP) to outputs (Qn, TC) propagation delays,

the clock pulse width and the maximum clock frequency.

V

MR INPUT

GND

V

CP INPUT

GND

V

OH

Qn, TC

OUTPUT

V

OL

Figure 2. Master reset (MR) pulse width,

the master reset to output (Q

and the master reset to clock (CP) removal times.

V

M

t

W

t

PHL

V

M

I

V

M

t

W

I

t

PHL

V

M

, TC) propagation delays

n

t

PLH

SV00576

t

rem

V

M

1.2 –35

2.0 0 –12 0

2.7 0 –9 0

3.0 to 3.6 0 –7

2.0 14 40 12

2.7 19 58 16

3.0 to 3.6 24 70 20

= 25°C

amb

SV00577

74LV161

LIMITS

–40 to +85 °C –40 to +125 °C

1

MAX MIN MAX

CET INPUT

GND

V

OH

TC OUTPUT

V

OL

2

V

I

V

M

V

M

t

0

PLH

Figure 3. Input (CET) to output (TC) propagation delays.

V

I

PE INPUT

GND

V

I

CP INPUT

GND

V

I

Dn INPUT

GND

The shaded areas indicate when the input is permitted to change for predictable output performance.

V

M

t

su

t

h

V

M

t

su

t

h

V

M

t

su

Figure 4. Set-up and hold times for input (Dn)

and parallel enable input (PE

).

UNIT

MHz

t

PHL

SV00578

t

h

t

su

t

h

SV00579

1997 May 15

9

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary counter; asynchronous reset

V

I

CEP, CET

INPUT

GND

V

I

CP INPUT

GND

The shaded areas indicate when the input is permitted to change for predictable output performance.

Figure 5. CEP and CET set-up and hold times.

TEST CIRCUIT

V

M

t

su

t

h

V

M

GENERATOR

PULSE

t

su

t

h

SV00580

V

CC

V

I

D.U.T.

R

T

74LV161

S

1

2 x V

CC

Open

GND

R

V

O

C

L

R

L

SWITCH POSITION

TEST S

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Open

2 x V

GND

1

CC

V

CC

< 2.7V V

Test Circuit for switching times

R

= Load resistor; see AC CHARACTERISTICS for value.

V

I

CC

2.7V2.7–3.6V

L

C

= Load capacitance includes jig and probe capacitance:

L

See AC CHARACTERISTICS for value.

= Termination resistance should be equal to Z

R

T

pulse generators.

Figure 6. Load circuitry for switching times.

DEFINITIONS

OUT

of

SV00776

1997 May 15

10

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary counter; asynchronous reset

DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4

74LV161

1997 May 15

11

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary counter; asynchronous reset

SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1

74LV161

1997 May 15

12

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary counter; asynchronous reset

SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1

74LV161

1997 May 15

13

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary counter; asynchronous reset

TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1

74LV161

1997 May 15

14

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary counter; asynchronous reset

NOTES

74LV161

1997 May 15

15

Philips Semiconductors Product specification

Presettable synchronous 4-bit binary counter; asynchronous reset

74LV161

DEFINITIONS

Data Sheet Identification Product Status Definition

Objective Specification

Preliminary Specification

Product Specification

Philips Semiconductors and Philips Electronics North America Corporation reserve the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification.

LIFE SUPPORT APPLICA TIONS Philips Semiconductors and Philips Electronics North America Corporation Products are not designed for use in life support appliances, devices, or systems where malfunction of a Philips Semiconductors and Philips Electronics North America Corporation Product can reasonably be expected

to result in a personal injury. Philips Semiconductors and Philips Electronics North America Corporation customers using or selling Philips Semiconductors and Philips Electronics North America Corporation Products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors and Philips Electronics North America Corporation for any damages resulting from such improper use or sale.

Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088–3409 Telephone 800-234-7381

Formative or in Design

Preproduction Product

Full Production

This data sheet contains the design target or goal specifications for product development. Specifications may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.

This data sheet contains Final Specifications. Philips Semiconductors reserves the right to make changes at any time without notice, in order to improve design and supply the best possible product.

 Copyright Philips Electronics North America Corporation 1997

 

1997 May 15

16