Datasheet 74lv03 DATASHEETS (Philips)

INTEGRATED CIRCUITS

74LV03

Quad 2-input NAND gate

Product specification
Supersedes data of 1997 Mar 28
IC24 Data Handbook

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1998 Apr 20

Philips Semiconductors Product specification

Quad 2-input NAND gate

FEA TURES

•Wide operating voltage: 1.0 to 5.5V

•Optimized for Low Voltage applications: 1.0 to 3.6V

•Accepts TTL input levels between V

•Typical V

T

amb

•Typical V

T

amb

(output ground bounce)  0.8V @ VCC = 3.3V,

OLP

= 25°C

(output VOH undershoot)  2V @ VCC = 3.3V,

OHV

= 25°C

•Level shifter capability

•Output capability: standard (open drain)

•I

category: SSI

CC

QUICK REFERENCE DATA

GND = 0V; T

SYMBOL

t

PZL/tPLZ

C

I

C

PD

NOTES:

is used to determine the dynamic power dissipation (PD in µW)

1C

PD

= CPD  V

P

D

f

= input frequency in MHz; CL = output load capacitance in pF;

i

= output frequency in MHz; VCC = supply voltage in V;

f

o

 (C
2 The condition is V
3 The given value of CPD is obtained with : CL = 0 pF and RL = ∞

= 25°C; tr =tf 2.5 ns

amb

CC

2

 V

L

 fo) = sum of the outputs.

CC

Propagation delay
nA, nB to nY

Input capacitance 3.5 pF
Power dissipation capacitance per gate Notes 1, 2 4 pF

2

x fi  (CL  V

= GND to V

I

= 2.7V and VCC = 3.6V

CC

PARAMETER CONDITIONS TYPICAL UNIT

2

 fo) where:

CC

CC

DESCRIPTION

The 74LV03 is a low–voltage Si–gate CMOS device and is pin and
function compatible with 74HC/HCT03.

The 74LV03 provides the 2–input NAND function.
The 74LV03 has open–drain N–transistor outputs, which are not

clamped by a diode connected to V
one input is LOW, the output may be pulled to any voltage between
GND and V
LOW–to–HIGH or HIGH–to–LOW level shifter. For digital operation
and OR–tied output applications, these devices must have a pull–up
resistor to establish a logic HIGH level.

CL = 15pF
VCC = 3.3V

. This allows the device to be used as a

Omax

. In the OFF–state, i.e. when

CC

8 ns

74L V03

ORDERING INFORMATION

PACKAGES TEMPERATURE RANGE OUTSIDE NORTH AMERICA NORTH AMERICA PKG. DWG. #

14-Pin Plastic DIL –40°C to +125°C 74LV03 N 74LV03 N SOT27-1
14-Pin Plastic SO –40°C to +125°C 74LV03 D 74LV03 D SOT108-1
14-Pin Plastic SSOP Type II –40°C to +125°C 74LV03 DB 74LV03 DB SOT337-1
14-Pin Plastic TSSOP Type I –40°C to +125°C 74L V03 PW 74LV03PW DH SOT402-1

PIN DESCRIPTION

PIN

NUMBER

1, 4, 9, 12 1A to 4A Data inputs
2, 5, 10, 13 1B to 4B Data inputs
3, 6, 8, 11 1Y to 4Y Data outputs
7 GND Ground (0V)
14 V

SYMBOL FUNCTION

CC

Positive supply voltage

FUNCTION TABLE

INPUTS OUTPUT

nA nB nY

L L Z

L H Z
H L Z
H H L

NOTES:

H = HIGH voltage level
L = LOW voltage level
Z = High impedance OFF-state

1998 Apr 20 853–1963 19257

2

Philips Semiconductors Product specification

74LV03Quad 2-input NAND gate

PIN CONFIGURATION

1

1A

2

1B

3

1Y

4

2A

5

2B

6

2Y

GND

LOGIC SYMBOL (IEEE/IEC)

1

2

&

14

V

13

4B

12

4A

11

4Y

3B

10

3A

9

3Y

87

SV00354

LOGIC SYMBOL

1A

1

CC

2

1B

4

2A

5

2B

9

3A

3B

10

12

4A

13

4B

1Y

2Y

3Y

4Y

SV00355

3

6

8

11

LOGIC DIAGRAM

Y

3

A

4

5

9

10

12

13

&

6

B

&

8

&

11

SV00356

GND

SV00357

1998 Apr 20

3

Philips Semiconductors Product specification

74LV03Quad 2-input NAND gate

RECOMMENDED OPERATING CONDITIONS

SYMBOL PARAMETER CONDITIONS MIN TYP. MAX UNIT

V

CC

V

V

T

amb

tr, t

NOTES:

1 The LV is guaranteed to function down to V

DC supply voltage See Note1 1.0 3.3 5.5 V
Input voltage 0 – V

I

Output voltage 0 – V

O

Operating ambient temperature range in free
air

Input rise and fall times

f

= 1.0V (input levels GND or VCC); DC characteristics are guaranteed from VCC = 1.2V to VCC = 5.5V.

CC

See DC and AC
characteristics

VCC = 1.0V to 2.0V
VCC = 2.0V to 2.7V
VCC = 2.7V to 3.6V
VCC = 3.6V to 5.5V

–40
–40

–
–
–

–
–
–
–

CC
CC

+85

+125

500
200
100

50

V
V

°C

ns/V

ABSOLUTE MAXIMUM RATINGS

1, 2

In accordance with the Absolute Maximum Rating System (IEC 134)
Voltages are referenced to GND (ground = 0V)

SYMBOL

V

CC

±I

IK

±I

OK

±I

O

±I

GND

±I

CC

T

stg

P

TOT

DC supply voltage –0.5 to +7.0 V
DC input diode current VI < –0.5 or VI > VCC + 0.5V 20 mA
DC output diode current VO < –0.5 or VO > VCC + 0.5V 50 mA
DC output source or sink current

– standard outputs
DC VCC or GND current for types with

,

–standard outputs 50
Storage temperature range –65 to +150 °C

Power dissipation per package
–plastic DIL
–plastic mini-pack (SO)
–plastic shrink mini-pack (SSOP and TSSOP)

PARAMETER CONDITIONS RATING UNIT

–0.5V < VO < VCC + 0.5V

25

mA

mA

for temperature range: –40 to +125°C
above +70°C derate linearly with 12mW/K
above +70°C derate linearly with 8 mW/K
above +60°C derate linearly with 5.5 mW/K

750
500
400

mW

NOTES:

1 Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the

device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability .

2 The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

1998 Apr 20

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Philips Semiconductors Product specification

V

V

V

V

HIGH l

t

voltage all out uts

V

g

V

LOW l

t

voltage all out uts

V

g

V

74LV03Quad 2-input NAND gate

DC CHARACTERISTICS

Over recommended operating conditions voltages are referenced to GND (ground = 0V)

LIMITS

SYMBOL P ARAMETER TEST CONDITIONS

VCC = 1.2V 0.9 0.9

IH

HIGH level Input
voltage

VCC = 2.0V 1.4 1.4
VCC = 2.7 to 3.6V 2.0 2.0
VCC = 4.5 to 5.5V 0.7*V
VCC = 1.2V 0.3 0.3

IL

LOW level Input
voltage

VCC = 2.0V 0.6 0.6
VCC = 2.7 to 3.6V 0.8 0.8
VCC = 4.5 to 5.5 0.3*V
VCC = 1.2V; VI = VIH or V
VCC = 2.0V; VI = VIH or V

V

OH

evel outpu

;

VCC = 2.7V; VI = VIH or V

p

VCC = 3.0V; VI = VIH or V
VCC = 4.5V;VI = VIH or V

OH

HIGH level output
voltage;
STANDARD
outputs

VCC = 3.0V;VI = VIH or V

VCC = 4.5V;VI = VIH or V
VCC = 1.2V; VI = VIH or V

VCC = 2.0V; VI = VIH or V

V

OL

evel outpu

;

VCC = 2.7V; VI = VIH or V

p

VCC = 3.0V;VI = VIH or V
VCC = 4.5V;VI = VIH or V

LOW level output
voltage;

OL

STANDARD
outputs

OZ

OZ

CC

I

I

HIGH level output
leakage current

HIGH level output
leakage current

Input leakage
current

Quiescent supply
current; SSI

I

I

I

VCC = 3.0V;VI = VIH or V

VCC = 4.5V;VI = VIH or V
VCC = 2.0 to 3.6V; VI = V

VO = VCC or GND
VCC = 2.0 to 3.6V; VI = V

VO = 6.0V

2

VCC = 5.5V; VI = VCC or GND 1.0 1.0 µA

VCC = 5.5V; VI = VCC or GND; IO = 0 20.0 40 µA

IL;
IL;
IL;
IL;

IL;

IL;

IL;

IL;
IL;

IL;
IL;
IL;

IL;

IL;

IL;

IL;

Additional

CC

quiescent supply
current per input

VCC = 2.7V to 3.6V; VI = VCC –0.6V 500 850 µA

∆I

NOTES:

1 All typical values are measured at T
2 The maximum operating output voltage (V

amb

= 25°C.

O(max)

) is 6.0V.

–IO = 100µA 1.2
–IO = 100µA 1.8 2.0 1.8
–IO = 100µA 2.5 2.7 2.5
–IO = 100µA 2.8 3.0 2.8

–IO = 100µA 4.3 4.5 4.3
–IO = 6mA 2.40 2.82 2.20

–IO = 12mA 3.60 4.20 3.50

IO = 100µA 0
IO = 100µA 0 0.2 0.2

IO = 100µA 0 0.2 0.2
IO = 100µA 0 0.2 0.2
IO = 100µA 0 0.2 0.2

IO = 6mA 0.25 0.40 0.50

IO = 12mA 0.35 0.55 0.65

-40°C to +85°C -40°C to +125°C

MIN TYP

CC

1

MAX MIN MAX

0.7*V

CC

CC

5.0 10 µA

10 20 µA

0.3*V

UNIT

CC

V

V

1998 Apr 20

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Philips Semiconductors Product specification

P

nA, nB, to nY

74LV03Quad 2-input NAND gate

AC CHARACTERISTICS FOR 74L V03

GND = 0V; tr = tf ≤ 2.5ns; CL = 50pF; RL = 1KΩ

SYMBOL

t

PZL/tPLZ

PARAMETER WAVEFORM

ropagation delay

Figures, 1, 2

NOTE:

1 Unless otherwise stated, all typical values are at T
2 Typical value measured at V
3 Typical value measured at V

CC
CC

= 3.3V.
= 5.0V.

amb

CONDITION

VCC(V) MIN TYP1MAX MIN MAX

1.2 – 50 – – –

2.0 – 17 26 – 31

2.7 – 13 19 – 23

3.0 to 3.6 – 10

4.5 to 5.5 – –

= 25°C.

LIMITS

–40 to +85 °C

2

3

16 – 19
13 – 16

LIMITS

–40 to +125 °C

UNIT

ns

AC WAVEFORMS

VM = 1.5V at VCC  2.7V  3.6V

= 0.5V * VCC at V

V

M

V

and V

OL

output load.
VX = V
V

= V

X

nA, nB INPUT

nY OUTPUT

are the typical output voltage drop that occur with the

OH

+ 0.3V at VCC  2.7V and  3.6V

OL

+ 0.1 * VCC at V

OL

V

I

V

CC

GND

V

OL

 2.7V and  4.5V

CC

 2.7V and  4.5V

CC

V

M

t

PLZ

V

TEST CIRCUIT

V

CC

PULSE

GENERATOR

V

I

D.U.T.

R

T

V

O

50 pF

C

L

Test Circuit for Outputs

DEFINITIONS

RL = Load resistor
C

= Load capacitance includes jig and probe capacitiance.

L

RT = Termination resistance should be equal to Z

of pulse generators.

OUT

SWITCH POSITION

Open

2 * V

GND

S

1

CC

V

CC

< 2.7V V

2.7–3.6V

 4.5V

V

CC

2.7V
V

CC

I

t

PZL

V

M

X

TEST

t

PLH/tPHL

t

PLZ/tPZL

t

PHZ/tPZH

Figure 2. Load circuitry for switching times

2 * V

Open
GND

R

= 1k

L

R

= 1k

L

SV00896

CC

Figure 1. Input (nA, nB) to output (nY) propagation delays.

1998 Apr 20

SV00358

6

Philips Semiconductors Product specification

Quad 2-input NAND gate

DIP14: plastic dual in-line package; 14 leads (300 mil) SOT27-1

74LV03

1998 Apr 20

7

Philips Semiconductors Product specification

Quad 2-input NAND gate

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

74LV03

1998 Apr 20

8

Philips Semiconductors Product specification

Quad 2-input NAND gate

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1

74LV03

1998 Apr 20

9

Philips Semiconductors Product specification

Quad 2-input NAND gate

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

74LV03

1998 Apr 20

10

Philips Semiconductors Product specification

Quad 2-input NAND gate

74LV03

NOTES

1998 Apr 20

11

Philips Semiconductors Product specification

74LV03Quad 2-input NAND gate

Data sheet status

Data sheet
status

Objective
specification

Preliminary
specification

Product
specification

Product
status

Development

Qualification

Production

Definition

This data sheet contains the design target or goal specifications for product development.
Specification may change in any manner without notice.

This data sheet contains preliminary data, and supplementary data will be published at a later date.
Philips Semiconductors reserves the right to make chages at any time without notice in order to
improve design and supply the best possible product.

This data sheet contains final specifications. Philips Semiconductors reserves the right to make
changes at any time without notice in order to improve design and supply the best possible product.

[1]

[1] Please consult the most recently issued datasheet before initiating or completing a design.

Definitions

Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For

detailed information see the relevant data sheet or data handbook.
Limiting values definition — Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one

or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or
at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended
periods may affect device reliability.

Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips
Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or
modification.

Disclaimers

Life support — These products are not designed for use in life support appliances, devices or systems where malfunction of these products can

reasonably be expected to result in personal injury . Philips Semiconductors customers using or selling these products for use in such applications
do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application.

Right to make changes — Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard
cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no
responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these
products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless
otherwise specified.

Philips Semiconductors
811 East Arques Avenue
P.O. Box 3409
Sunnyvale, California 94088–3409
Telephone [phone]

 Copyright Philips Electronics North America Corporation 1998

All rights reserved. Printed in U.S.A.

print code Date of release: 08-98
Document order number: 9397-750-04403

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