Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT75
Quad bistable transparent latch
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
Page 2
December 1990 2
Philips Semiconductors Product specification
Quad bistable transparent latch 74HC/HCT75
FEATURES
• Complementary Q and Q outputs
• VCC and GND on the centre pins
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT75 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT75 have four bistable latches. The two
latches are simultaneously controlled by one of two active
HIGH enable inputs (LE
1-2
and LE
3-4
). When LE
n-n
is
HIGH, the data enters the latches and appears at the nQ
outputs. The nQ outputs follow the data inputs (nD) as long
as LE
n-n
is HIGH (transparent). The data on the nD inputs
one set-up time prior to the HIGH-to-LOW transition of the
LE
n-n
will be stored in the latches. The latched outputs
remain stable as long as the LE
n-n
is LOW.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; tr=tf=6ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PD in µW):
PD=CPD× V
CC
2
× fi+∑ (CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC−1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay CL= 15 pF; VCC=5V
nD to nQ, n
Q1112ns
LE
n-n
to nQ, nQ1111ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per latch notes 1 and 2 42 42 pF
Page 3
December 1990 3
Philips Semiconductors Product specification
Quad bistable transparent latch 74HC/HCT75
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 14, 11, 8 1
Q to 4Q complementary latch outputs
2, 3, 6, 7 1D to 4D data inputs
4LE
3-4
latch enable input, latches 3 and 4 (active HIGH)
5V
CC
positive supply voltage
12 GND ground (0 V)
13 LE
1-2
latch enable input, latches 1 and 2 (active HIGH)
16, 15, 10, 9 1Q to 4Q latch outputs
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
Page 4
December 1990 4
Philips Semiconductors Product specification
Quad bistable transparent latch 74HC/HCT75
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
q = lower case letters indicate the state of the
referenced output one set-up time prior
to the HIGH-to-LOW LE
n-n
transition
X = don’t care
OPERATING
MODES
INPUTS OUTPUTS
LE
n-n
nD nQ nQ
data enabled
H
H
L
H
L
H
H
L
data latched L X q
q
Fig.4 Functional diagram.
Fig.5 Logic diagram.
Page 5
December 1990 5
Philips Semiconductors Product specification
Quad bistable transparent latch 74HC/HCT75
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r=tf
= 6 ns; CL=50pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS+25 −40 to+85 −40 to+125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
nD to nQ
33
12
10
110
22
19
140
28
24
165
33
28
ns 2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
nD to nQ
39
14
11
120
24
20
150
30
26
180
36
31
ns 2.0
4.5
6.0
Fig.7
t
PHL
/ t
PLH
propagation delay
LE
n-n
to nQ
33
12
10
120
24
20
150
30
26
180
36
31
ns 2.0
4.5
6.0
Fig.8
t
PHL
/ t
PLH
propagation delay
LE
n-n
to nQ
39
14
11
125
25
21
155
31
26
190
38
32
ns 2.0
4.5
6.0
Fig.8
t
THL
/ t
TLH
output transition time 19
7
6
75
15
13
95
19
16
110
22
19
ns 2.0
4.5
6.0
Figs 6 and 7
t
W
enable pulse width
HIGH
80
16
14
17
6
5
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.8
t
su
set-up time
nD to LE
n-n
60
12
10
14
5
4
75
15
13
90
18
15
ns 2.0
4.5
6.0
Fig.9
t
h hold time
nD to LE
n-n
3
3
3
−8
−3
−2
3
3
3
3
3
3
ns 2.0
4.5
6.0
Fig.9
Page 6
December 1990 6
Philips Semiconductors Product specification
Quad bistable transparent latch 74HC/HCT75
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND=0V; t
r
=tf= 6 ns; CL=50pF
INPUT UNIT LOAD COEFFICIENT
nD
LE
n-n
0.75
1.00
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
nD to nQ
15 28 35 42 ns 4.5 Fig.6
t
PHL
/ t
PLH
propagation delay
nD to nQ
15 28 35 42 ns 4.5 Fig.7
t
PHL
/ t
PLH
propagation delay
LE
n-n
to nQ
13 28 35 42 ns 4.5 Fig.8
t
PHL
/ t
PLH
propagation delay
LE
n-n
to nQ
15 30 38 45 ns 4.5 Fig.8
t
THL
/ t
TLH
output transition time 7 15 19 22 ns 4.5 Figs 6 and 7
t
W
enable pulse width
HIGH
16 4 20 24 ns 4.5 Fig.8
t
su
set-up time
nD to LE
n-n
12 4 15 18 ns 4.5 Fig.9
t
h
hold time
nD to LE
n-n
3 −2 3 3 ns 4.5 Fig.9
Page 7
December 1990 7
Philips Semiconductors Product specification
Quad bistable transparent latch 74HC/HCT75
AC WAVEFORMS
Fig.6 Waveforms showing the data input (nD) to
output (nQ) propagation delays and the
output transition times.
(1) HC : VM = 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Fig.7 Waveforms showing the data input (nD) to
output (nQ) propagation delays and the
output transition times.
(1) HC : VM = 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Fig.8 Waveforms showing the latch enable input
(LE
n-n
) pulse width, the latch enable input to
outputs (nQ, nQ) propagation delays and
the output transition times.
(1) HC : VM = 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.9 Waveforms showing the data set-up and
hold times for nD input to LE
n-n
input.
The shaded areas indicate when the input is permitted to change
for predictable output performance.
(1) HC : V
M
= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Loading...