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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7597
8-bit shift register with input latches
Product specification
File under Integrated Circuits, IC06
December 1990
Page 2
Philips Semiconductors Product specification
8-bit shift register with input latches 74HC/HCT7597
FEATURES
• 8-bit parallel input latches
• Shift register has direct overriding load and clear
• Output capability: standard
• ICCcategory: MSI
The 74HC/HCT7597 both consist of an 8-bit storage latch
feeding a parallel-in, serial-out 8-bit shift register.
LE is LOW, data at the Dninputs enter the latches.
When
In this condition the latches are transparent, i.e. a latch
output will change state each time its corresponding
D-input changes.
When LE is HIGH the latches store the information that
GENERAL DESCRIPTION
The 74HC/HCT7597 are high-speed Si-gate CMOS
devices and are pin compatible with low power Schottky
TTL (LSTTL). They are specified in compliance with
was present at the D-inputs, a set-up time preceding the
LOW-to-HIGH transition of LE.
The shift register has a positive edge-triggered clock,
direct load (from storage) and clear inputs.
JEDEC standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL
/ t
PLH
propagation delay CL= 15 pF; VCC= 5 V
to Q 15 17 ns
SH
CP
LE to Q 22 27 ns
PL to Q 20 23 ns
to Q 20 24 ns
D
7
f
max
C
C
I
PD
maximum clock frequency SH
CP
input capacitance 3.5 3.5 pF
power dissipation capacitance per package notes 1, 2 29 30 pF
TYPICAL
UNIT
HC HCT
99 79 MHz
Notes
1. C
is used to determine the dynamic power dissipation (PDin µW):
PD
PD=CPD× V
2
× fi+∑(CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz; fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF; VCC= supply voltage in V
2. For HC the condition is VI= GND to VCC; for HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
.
December 1990 2
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Philips Semiconductors Product specification
8-bit shift register with input latches 74HC/HCT7597
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
8 GND ground (0 V)
9 Q serial data output
10
11 SH
12
13
14 D
15, 1, 2, 3, 4, 5, 6, 7 D
16 V
MR asynchronous reset input (active LOW)
CP
shift clock input (LOW-to-HIGH, edge-triggered)
LE latch enable input (active LOW)
PL parallel load input (active LOW)
S
0
CC
to D
7
serial data input
parallel data inputs
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 3
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Philips Semiconductors Product specification
8-bit shift register with input latches 74HC/HCT7597
FUNCTION TABLE
LE SHCPPL MR FUNCTION
L X X X data enabled to input latches (transparent)
H X X X data stored into latches (non-transparent)
X X L H data transferred from input latches to shift register
X X L L invalid logic, state of shift register indeterminate when signals removed
X X H L shift register cleared
X ↑ H H shift register clocked Q
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH CP transition
n=Qn-1
, Q0=D
S
Fig.4 Functional diagram.
December 1990 4
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Philips Semiconductors Product specification
8-bit shift register with input latches 74HC/HCT7597
Fig.5 Logic diagram.
December 1990 5
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Philips Semiconductors Product specification
8-bit shift register with input latches 74HC/HCT7597
Fig.6 Timing diagram.
December 1990 6
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Philips Semiconductors Product specification
8-bit shift register with input latches 74HC/HCT7597
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: standard
ICCcategory: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
SYMBOL PARAMETER
t
PHL
/ t
propagation delay
PLH
SHCPto Q
t
PHL
propagation delay
MR to Q
t
PHL
/ t
propagation delay
PLH
LE to Q
t
PHL
/ t
propagation delay
PLH
PL to Q
t
PHL
/ t
propagation delay
PLH
D7to Q
t
THL
t
W
/ t
output transition time 19
TLH
SHCPpulse width
HIGH or LOW
t
W
LE pulse width
LOW
t
W
MR pulse width
LOW
t
W
PL pulse width
LOW
t
rem
removal time
MR to SH
CP
(°C)
T
amb
74HC
min. typ. max. min. max. min. max.
50
80
16
14
80
16
14
80
16
14
80
16
14
50
10
9
18
14
52
19
15
72
26
21
63
23
18
63
23
18
7
6
11
4
3
11
4
3
17
6
5
17
6
5
−3
−1
−1
175
35
30
175
35
30
250
50
43
190
38
32
190
38
32
75
15
13
100
20
17
100
20
17
100
20
17
100
20
17
65
13
11
220
44
37
220
44
37
315
63
54
240
48
41
240
48
41
95
19
16
265
53
45
265
53
45
375
75
64
285
57
48
285
57
48
110
22
19
120
24
20
120
24
20
120
24
20
120
24
20
75
15
13
.
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
TEST CONDITIONS
V
CC
WAVEFORMS+25 −40 to +85 −40 to +125
(V)
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
December 1990 7
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Philips Semiconductors Product specification
8-bit shift register with input latches 74HC/HCT7597
T
SYMBOL PARAMETER
t
rem
removal time
MR to PL
t
su
set-up time
Dnto LE
t
su
t
su
t
h
set-up time
DSto SH
set-up time
PL to SH
hold time
CP
CP
Dnto LE
t
h
t
h
f
max
hold time
DSto SH
CP
hold time
PL to SH
CP
maximum pulse frequency
SH
CP
(°C)
amb
74HC
min. typ. max. min. max. min. max.
100
20
17
80
16
14
80
16
14
80
16
14
4
4
4
2
2
2
2
2
2
6.0
30
35
22
8
6
6
2
2
11
4
3
8
3
2
−3
−1
−1
−8
−3
−2
−8
−3
−2
30
90
107
125
25
21
100
20
17
100
20
17
100
20
17
4
4
4
2
2
2
2
2
2
4.8
24
28
150
30
26
120
24
20
120
24
20
120
24
20
4
4
4
2
2
2
2
2
2
4.0
20
24
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
MHz 2.0
TEST CONDITIONS
V
CC
WAVEFORMS+25 −40 to +85 −40 to +125
(V)
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
December 1990 8
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Philips Semiconductors Product specification
8-bit shift register with input latches 74HC/HCT7597
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICCcategory: MSI
Note to HCT types
The value of additional quiescent supply current (∆ICC) for a unit load of 1 is given in the family specifications.
To determine ∆I
per input, multiply this value by the unit load coefficient shown in the table below.
CC
INPUT UNIT LOAD COEFFICIENT
D
S
D
n
PL, MR
LE, SH
CP
0.25
0.40
1.50
1.50
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
= 6 ns; CL= 50 pF
r=tf
T
amb
(°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
V
(V)
CC
WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
propagation delay
PLH
20 35 44 53 ns 4.5 Fig.7
SHCPto Q
t
PHL
propagation delay
25 42 53 63 ns 4.5 Fig.7
MR to Q
t
PHL
/ t
propagation delay
PLH
31 53 66 80 ns 4.5 Fig.7
LE to Q
t
PHL
/ t
propagation delay
PLH
27 46 58 69 ns 4.5 Fig.7
PL to Q
t
PHL
/ t
propagation delay
PLH
28 49 61 74 ns 4.5 Fig.7
D7to Q
t
THL
/ t
output transition time 7 15 19 22 ns 4.5 Fig.7
TLH
t
W
SHCPpulse width
16 6 20 24 ns 4.5 Fig.7
HIGH or LOW
t
W
LE pulse width
16 7 20 24 ns 4.5 Fig.7
LOW
t
W
MR pulse width
20 11 25 30 ns 4.5 Fig.7
LOW
t
W
PL pulse width
18 9 23 27 ns 4.5 Fig.7
LOW
t
t
rem
rem
removal time
MR to SH
removal time
10 −1 13 15 ns 4.5 Fig.7
CP
20 9 25 30 ns 4.5 Fig.7
MR to PL
December 1990 9
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Philips Semiconductors Product specification
8-bit shift register with input latches 74HC/HCT7597
T
SYMBOL PARAMETER
t
su
set-up time
Dnto LE
t
su
t
su
t
h
set-up time
DSto SH
set-up time
PL to SH
hold time
CP
CP
Dnto LE
t
h
t
h
f
max
hold time
DSto SH
CP
hold time
PL to SH
CP
maximum pulse frequency
SH
CP
(°C)
amb
74HCT
UNIT
min. typ. max. min. max. min. max.
16 5 20 24 ns 4.5 Fig.7
16 5 20 24 ns 4.5 Fig.7
16 3 20 24 ns 4.5 Fig.7
4 −2 4 4 ns 4.5 Fig.7
2 −4 2 2 ns 4.5 Fig.7
2 −3 2 2 ns 4.5 Fig.7
30 72 24 20 MHz 4.5 Fig.7
TEST CONDITIONS
V
CC
WAVEFORMS+25 −40 to +85 −40 to +125
(V)
December 1990 10
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Philips Semiconductors Product specification
8-bit shift register with input latches 74HC/HCT7597
AC WAVEFORMS
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
= 1.3 V; VI= GND to 3 V.
M
Fig.7 Waveforms showing the SHCP input to Q
output propagation delays, the SHCPpulse
width and maximum clock pulse frequency.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.8 Waveforms showing the MR input to Q
output propagation delay and the MR pulse
width.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
= 1.3 V; VI= GND to 3 V.
M
Fig.9 Waveforms showing the LE input to Q
output propagation delays and theLE pulse
width.
December 1990 11
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.10 Waveforms showing the PL input to Q
output propagation delays, PL pulse width
and output transition times.
Page 12
Philips Semiconductors Product specification
8-bit shift register with input latches 74HC/HCT7597
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
= 1.3 V; VI= GND to 3 V.
M
Fig.11 Waveforms showing the D7input to Q
output propagation delays and output
transition times.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.12 Waveforms showing the MR input to PL,
SHCPremoval times.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
HCT: V
= 50%; VI= GND to VCC.
M
= 1.3 V; VI= GND to 3 V.
M
Fig.13 Waveforms showing hold and set-up times
for DS, Dninputs to SH
LE inputs.
CP,
December 1990 12
Fig.14 Waveforms showing set-up and hold times
for PL input to SHCPinput.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
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