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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT75
Quad bistable transparent latch
Product specification
File under Integrated Circuits, IC06
December 1990
Page 2
Philips Semiconductors Product specification
Quad bistable transparent latch 74HC/HCT75
FEATURES
• Complementary Q and Q outputs
• VCC and GND on the centre pins
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT75 have four bistable latches. The two
latches are simultaneously controlled by one of two active
HIGH enable inputs (LE
HIGH, the data enters the latches and appears at the nQ
outputs. The nQ outputs follow the data inputs (nD) as long
as LE
is HIGH (transparent). The data on the nD inputs
n-n
one set-up time prior to the HIGH-to-LOW transition of the
LE
will be stored in the latches. The latched outputs
n-n
remain stable as long as the LE
The 74HC/HCT75 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf=6ns
amb
SYMBOL PARAMETER CONDITIONS
/ t
t
PHL
PLH
C
I
C
PD
propagation delay CL= 15 pF; VCC=5V
nD to nQ, n
LE
n-n
Q1112ns
to nQ, nQ1111ns
input capacitance 3.5 3.5 pF
power dissipation capacitance per latch notes 1 and 2 42 42 pF
and LE
1-2
TYPICAL
HC HCT
3-4
is LOW.
n-n
). When LE
n-n
UNIT
is
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC−1.5 V
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
.
December 1990 2
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Philips Semiconductors Product specification
Quad bistable transparent latch 74HC/HCT75
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1, 14, 11, 8 1
2, 3, 6, 7 1D to 4D data inputs
4LE
5V
12 GND ground (0 V)
13 LE
16, 15, 10, 9 1Q to 4Q latch outputs
Q to 4Q complementary latch outputs
3-4
CC
1-2
latch enable input, latches 3 and 4 (active HIGH)
positive supply voltage
latch enable input, latches 1 and 2 (active HIGH)
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 3
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Philips Semiconductors Product specification
Quad bistable transparent latch 74HC/HCT75
FUNCTION TABLE
OPERATING
MODES
data enabled
data latched L X q
Notes
1. H = HIGH voltage level
L = LOW voltage level
q = lower case letters indicate the state of the
referenced output one set-up time prior
to the HIGH-to-LOW LE
X = don’t care
INPUTS OUTPUTS
LE
n-n
H
H
nD nQ nQ
L
H
transition
n-n
L
H
H
L
q
Fig.4 Functional diagram.
Fig.5 Logic diagram.
December 1990 4
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Philips Semiconductors Product specification
Quad bistable transparent latch 74HC/HCT75
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= 6 ns; CL=50pF
r=tf
SYMBOL PARAMETER
t
PHL
/ t
propagation delay
PLH
nD to nQ
t
PHL
/ t
propagation delay
PLH
nD to nQ
t
PHL
t
PHL
t
THL
t
W
/ t
/ t
/ t
propagation delay
PLH
LE
to nQ
n-n
propagation delay
PLH
LE
to nQ
n-n
output transition time 19
TLH
enable pulse width
HIGH
t
su
t
h hold time
set-up time
nD to LE
nD to LE
n-n
n-n
(°C)
T
amb
74HC
min. typ. max. min. max. min. max.
33
80
16
14
60
12
10
3
3
3
12
10
39
14
11
33
12
10
39
14
11
7
6
17
6
5
14
5
4
−8
−3
−2
110
22
19
120
24
20
120
24
20
125
25
21
75
15
13
100
20
17
75
15
13
3
3
3
140
28
24
150
30
26
150
30
26
155
31
26
95
19
16
165
33
28
180
36
31
180
36
31
190
38
32
110
22
19
120
24
20
90
18
15
3
3
3
.
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
TEST CONDITIONS
V
CC
WAVEFORMS+25 −40 to+85 −40 to+125
(V)
Fig.6
4.5
6.0
Fig.7
4.5
6.0
Fig.8
4.5
6.0
Fig.8
4.5
6.0
Figs 6 and 7
4.5
6.0
Fig.8
4.5
6.0
Fig.9
4.5
6.0
Fig.9
4.5
6.0
December 1990 5
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Philips Semiconductors Product specification
Quad bistable transparent latch 74HC/HCT75
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
) for a unit load of 1 is given in the family specifications.
CC
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
nD
LE
n-n
0.75
1.00
AC CHARACTERISTICS FOR 74HCT
GND=0V; t
=tf= 6 ns; CL=50pF
r
T
amb
(°C)
TEST CONDITIONS
74HCT
SYMBOL PARAMETER
UNIT
V
CC
(V)
min. typ. max. min. max. min. max.
t
PHL
/ t
propagation delay
PLH
15 28 35 42 ns 4.5 Fig.6
nD to nQ
t
PHL
/ t
propagation delay
PLH
15 28 35 42 ns 4.5 Fig.7
nD to nQ
t
PHL
t
PHL
t
THL
/ t
/ t
/ t
propagation delay
PLH
LE
to nQ
n-n
propagation delay
PLH
LE
to nQ
n-n
output transition time 7 15 19 22 ns 4.5 Figs 6 and 7
TLH
13 28 35 42 ns 4.5 Fig.8
15 30 38 45 ns 4.5 Fig.8
WAVEFORMS+25 −40 to +85 −40 to +125
t
W
enable pulse width
16 4 20 24 ns 4.5 Fig.8
HIGH
t
su
t
h
set-up time
nD to LE
hold time
nD to LE
12 4 15 18 ns 4.5 Fig.9
n-n
3 −2 3 3 ns 4.5 Fig.9
n-n
December 1990 6
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Philips Semiconductors Product specification
Quad bistable transparent latch 74HC/HCT75
AC WAVEFORMS
(1) HC : VM = 50%; VI= GND to VCC.
HCT: V
= 1.3 V; VI= GND to 3 V.
M
Fig.6 Waveforms showing the data input (nD) to
output (nQ) propagation delays and the
output transition times.
(1) HC : VM = 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.7 Waveforms showing the data input (nD) to
output (nQ) propagation delays and the
output transition times.
The shaded areas indicate when the input is permitted to change
for predictable output performance.
(1) HC : V
= 50%; VI= GND to VCC.
M
= 1.3 V; VI= GND to 3 V.
HCT: V
M
(1) HC : VM = 50%; VI= GND to VCC.
HCT: V
= 1.3 V; VI= GND to 3 V.
M
Fig.8 Waveforms showing the latch enable input
(LE
) pulse width, the latch enable input to
n-n
outputs (nQ, nQ) propagation delays and
the output transition times.
December 1990 7
Fig.9 Waveforms showing the data set-up and
hold times for nD input to LE
n-n
input.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
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