Page 1
DATA SH EET
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
1998 Feb 23
INTEGRATED CIRCUITS
74HC/HCT74
Dual D-type flip-flop with set and
reset; positive-edge trigger
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
Page 2
1998 Feb 23 2
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC/HCT74
FEATURES
• Output capability: standard
• ICC category: flip-flops
GENERAL DESCRIPTION
The 74HC/HCT74 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT74 are dual positive-edge triggered, D-type
flip-flops with individual data (D) inputs, clock (CP) inputs,
set (
SD) and reset (RD) inputs; also complementary Q and
Q outputs.
The set and reset are asynchronous active LOW inputs
and operate independently of the clock input. Information
on the data input is transferred to the Q output on the
LOW-to-HIGH transition of the clock pulse. The D inputs
must be stable one set-up time prior to the LOW-to-HIGH
clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25 °C; tr= tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PDin µW):
PD= CPD× V
CC
2
× fi+∑(CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL
/ t
PLH
propagation delay CL= 15 pF; VCC= 5 V
nCP to nQ, n
Q1415ns
n
S
D
to nQ, nQ1518ns
n
R
D
to nQ, nQ1618ns
f
max
maximum clock frequency 76 59 MHz
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per flip-flop notes 1 and 2 24 29 pF
Page 3
1998 Feb 23 3
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC/HCT74
ORDERING INFORMATION
PIN DESCRIPTION
TYPE
NUMBER
PACKAGE
NAME DESCRIPTION VERSION
74HC(T)74N DIP14 plastic dual in-line package; 14 leads (300 mil) SOT27-1
74HC(T)74D SO14 plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74HCT74DB SSOP14 plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1
74HCT74PW TSSOP14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1
PIN NO. SYMBOL NAME AND FUNCTION
1, 13 1
RD, 2R
D
asynchronous reset-direct input (active LOW)
2, 12 1D, 2D data inputs
3, 11 1CP, 2CP clock input (LOW-to-HIGH, edge-triggered)
4, 10 1
SD, 2S
D
asynchronous set-direct input (active LOW)
5, 9 1Q, 2Q true flip-flop outputs
6, 8 1
Q, 2Q complement flip-flop outputs
7 GND ground (0 V)
14 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
Page 4
1998 Feb 23 4
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC/HCT74
Fig.4 Functional diagram.
FUNCTION TABLE
Note
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH CP transition
Q
n+1
= state after the next LOW-to-HIGH CP transition
INPUTS OUTPUTS
S
D
R
D
CP D Q Q
LHXXHL
HLXXLH
LLXXHH
INPUTS OUTPUTS
S
D
R
D
CP D Q
n+1
Q
n+1
HH↑LL H
HH↑HH L
Fig.5 Logic diagram (one flip-flop).
Page 5
1998 Feb 23 5
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC/HCT74
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICCcategory: flip-flops
AC CHARACTERISTICS
GND = 0 V; t
r
= tf= 6 ns; CL= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max min. max.
t
PHL
/ t
PLH
propagation delay
nCP to nQ, nQ
47 175 220 265 ns 2.0 Fig.6
17 35 44 53 4.5
14 30 37 45 6.0
t
PHL
/ t
PLH
propagation delay
nSDto nQ, nQ
50 200 250 300 ns 2.0 Fig.7
18 40 50 60 4.5
14 34 43 51 6.0
t
PHL
/ t
PLH
propagation delay
nRDto nQ, nQ
52 200 250 300 ns 2.0 Fig.7
19 40 50 60 4.5
15 34 43 51 6.0
t
THL
/ t
TLH
output transition time 19 75 95 110 ns 2.0 Fig.6
7 15 19 22 4.5
6 13 16 19 6.0
t
W
clock pulse width
HIGH or LOW
80 19 100 120 ns 2.0 Fig.6
16 7 20 24 4.5
14 6 17 20 6.0
t
W
set or reset pulse width
LOW
80 19 100 120 ns 2.0 Fig.7
16 7 20 24 4.5
14 6 17 20 6.0
t
rem
removal time
set or reset
30 3 40 45 ns 2.0 Fig.7
6 1 8 9 4.5
5 1 7 8 6.0
t
su
set-up time
nD to nCP
60 6 75 90 ns 2.0 Fig.6
12 2 15 18 4.5
10 2 13 15 6.0
t
h
hold time
nCP to nD
3 −6 3 3 ns 2.0 Fig.6
3 −2 3 3 4.5
3 −2 3 3 6.0
f
max
maximum clock pulse
frequency
6.0 23 4.8 4.0 MHz 2.0 Fig.6
30 69 24 20 4.5
35 82 28 24 6.0
Page 6
1998 Feb 23 6
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC/HCT74
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICCcategory: flip-flops
Note to HCT types
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r
= tf= 6 ns; CL= 50 pF
INPUT UNIT LOAD COEFFICIENT
nD 0.70
nR
D
0.70
n
S
D
0.80
nCP 0.80
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
nCP to nQ, nQ
18 35 44 53 ns 4.5 Fig.6
t
PHL
/ t
PLH
propagation delay
nSDto nQ, nQ
23 40 50 60 ns 4.5 Fig.7
t
PHL
/ t
PLH
propagation delay
nRDto nQ, nQ
24 40 50 60 ns 4.5 Fig.7
t
THL
/ t
TLH
output transition time 7 15 19 22 ns 4.5 Fig.6
t
W
clock pulse width
HIGH or LOW
18 9 23 27 ns 4.5 Fig.6
t
W
set or reset pulse width
LOW
16 9 20 24 ns 4.5 Fig.7
t
rem
removal time
set or reset
6 1 8 9 ns 4.5 Fig.7
t
su
set-up time
nD to nCP
12 5 15 18 ns 4.5 Fig.6
t
h
hold time
nCP to nD
3 −3 3 3 ns 4.5 Fig.6
f
max
maximum clock pulse
frequency
27 54 22 18 MHz 4.5 Fig.6
Page 7
1998 Feb 23 7
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC/HCT74
AC WAVEFORMS
Fig.6 Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD
to nCP set-up, the nCP to nD hold times, the output transition times and the maximum clock pulse
frequency.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
M
= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
handbook, full pagewidth
t
rem
t
W
t
W
t
PLH
t
rem
V
M
(1)
V
M
(1)
V
M
(1)
V
M
(1)
nQ OUTPUT
t
PHL
t
PLH
t
PHL
V
M
(1)
nRD INPUT
nSD INPUT
nCP INPUT
nQ OUTPUT
MGL350
Fig.7 Waveforms showing the set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set
and reset pulse widths and the nRD, nSDto nCP removal time.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Page 8
1998 Feb 23 8
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC/HCT74
PACKAGE OUTLINES
UNIT
A
max.
1 2
(1) (1)
b
1
cD
(1)
Z
Ee M
H
L
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC EIAJ
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT27-1
92-11-17
95-03-11
A
min.
A
max.
b
max.
w
M
E
e
1
1.73
1.13
0.53
0.38
0.36
0.23
19.50
18.55
6.48
6.20
3.60
3.05
0.2542.54 7.62
8.25
7.80
10.0
8.3
2.24.2 0.51 3.2
0.068
0.044
0.021
0.015
0.77
0.73
0.014
0.009
0.26
0.24
0.14
0.12
0.010.10 0.30
0.32
0.31
0.39
0.33
0.0870.17 0.020 0.13
050G04 MO-001AA
M
H
c
(e )
1
M
E
A
L
seating plane
A
1
w M
b
1
e
D
A
2
Z
14
1
8
7
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
DIP14: plastic dual in-line package; 14 leads (300 mil)
SOT27-1
Page 9
1998 Feb 23 9
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC/HCT74
UNIT
A
max.
A
1
A2A3b
p
cD
(1)E(1)
(1)
eHELLpQZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC EIAJ
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
8.75
8.55
4.0
3.8
1.27
6.2
5.8
0.7
0.6
0.7
0.3
8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
1.0
0.4
SOT108-1
X
w M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v M
A
(A )
3
A
7
8
1
14
y
076E06S MS-012AB
pin 1 index
0.069
0.010
0.004
0.057
0.049
0.01
0.019
0.014
0.0100
0.0075
0.35
0.34
0.16
0.15
0.050
1.05
0.041
0.244
0.228
0.028
0.024
0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
95-01-23
97-05-22
0 2.5 5 mm
scale
SO14: plastic small outline package; 14 leads; body width 3.9 mm
SOT108-1
Page 10
1998 Feb 23 10
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC/HCT74
UNIT A1A2A3b
p
cD
(1)E(1)
eHELLpQZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC EIAJ
mm
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
0.65 1.25 0.2
7.9
7.6
1.03
0.63
0.9
0.7
1.4
0.9
8
0
o
o
0.13 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT337-1
95-02-04
96-01-18
(1)
w M
b
p
D
H
E
E
Z
e
c
v M
A
X
A
y
1
7
14
8
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
MO-150AB
pin 1 index
0 2.5 5 mm
scale
SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm
SOT337-1
A
max.
2.0
Page 11
1998 Feb 23 11
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC/HCT74
UNIT A1A2A
3
b
p
cD
(1)E(2) (1)
eHELLpQZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC EIAJ
mm
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
0.4
0.3
0.72
0.38
8
0
o
o
0.13 0.10.21.0
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT402-1 MO-153
94-07-12
95-04-04
w M
b
p
D
Z
e
0.25
17
14
8
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v M
A
X
A
y
0 2.5 5 mm
scale
TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm
SOT402-1
A
max.
1.10
pin 1 index
Page 12
1998 Feb 23 12
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC/HCT74
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“IC Package Databook”
(order code 9398 652 90011).
DIP
SOLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
stg max
). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
R
EPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
SO, SSOP and TSSOP
REFLOW SOLDERING
Reflow soldering techniques are suitable for all SO, SSOP
and TSSOP packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method.
Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
W
AVE SOLDERING
Wave soldering can be used for all SO packages. Wave
soldering is not recommended for SSOP and TSSOP
packages, because of the likelihood of solder bridging due
to closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
If wave soldering is used - and cannot be avoided for
SSOP and TSSOP packages - the following conditions
must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow and must incorporate solder
thieves at the downstream end.
Even with these conditions:
• Only consider wave soldering SSOP packages that
have a body width of 4.4 mm, that is
SSOP16 (SOT369-1) or SSOP20 (SOT266-1).
• Do not consider wave soldering TSSOP packages
with 48 leads or more, that is TSSOP48 (SOT362-1)
and TSSOP56 (SOT364-1).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
R
EPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
Page 13
1998 Feb 23 13
Philips Semiconductors Product specification
Dual D-type flip-flop with set and reset;
positive-edge trigger
74HC/HCT74
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
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