Page 1
INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT7403
4-Bit x 64-word FIFO register;
3-state
Product specification
Supersedes data of October 1990
File under Integrated Circuits, IC06
September 1993
Page 2
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
FEATURES
• Synchronous or asynchronous
operation
• 3-state outputs
• 30 MHz (typical) shift-in and
shift-out rates
• Readily expandable in word and bit
dimensions
• Pinning arranged for easy board
layout: input pins directly opposite
output pins
• Output capability: driver (8 mA)
• ICC category: LSI.
APPLICATIONS
• High-speed disc or tape controller
• Communications buffer.
GENERAL DESCRIPTION
The 74HC/HCT7403 are high-speed
Si-gate CMOS devices. They are
specified in compliance with JEDEC
standard no.7A.
QUICK REFERENCE DATA
GND = 0 V; T
= 25 °C; tr = tf = 6 ns.
amb
TYP.
SYMBOL PARAMETER CONDITIONS
HC HCT
t
PHL/tPLH
f
max
propagation delay SO,
SI to DIR and DOR
maximum clock
CL = 15 pF;
VCC = 5 V
15 17 ns
30 30 MHz
frequency
C
I
C
PD
input capacitance 3.5 3.5 pF
power dissipation
note 1 475 490 pF
capacitance per
package
Note
1. For HC the condition is V
= GND to VCC.
I
For HCT the condition is VI = GND to VCC−1.5 V.
ORDERING INFORMATION
EXTENDED
TYPE NUMBER
PINS PIN POSITION MATERIAL CODE
PACKAGE
74HC/HCT7403N 16 DIL plastic SOT38Z
74HC/HCT7403D 16 SO16L plastic SOT162
UNIT
The “7403” is an expandable, First-In
First-Out (FIFO) memory organized
as 64 words by 4 bits. A guaranteed
15 MHz data-rate makes it ideal for
high-speed applications. A higher
data-rate can be obtained in
applications where the status flags
are not used (burst-mode).
With separate controls for shift-in (SI)
and shift-out (
SO), reading and
writing operations are completely
independent, allowing synchronous
and asynchronous data transfers.
Additional controls include a
master-reset input (MR), an output
enable input (OE) and flags. The
data-in-ready (DIR) and
data-out-ready (DOR) flags indicate
the status of the device.
September 1993 2
Page 3
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
PINNING
SYMBOL PIN DESCRIPTION
OE 1 output enable input (active LOW)
DIR 2 data-in-ready output
SI 3 shift-in input (active HIGH)
D
to D
O
4, 5,
3
parallel data input
6, 7
GND 8 ground
MR 9 asynchronous master-reset
input (active LOW)
Q
to Q
3
10, 1 1,
0
data output
12, 13
DOR 14 data-out-ready output
SO 15 shift-out input (active LOW)
V
CC
16 positive supply voltage
handbook, halfpage
OE
DIR
D
D
D
D
GND
1
2
SI
3
4
0
1
2
3
7403
5
6
7
8
MGA672
V
16
CC
15
SO
14
DOR
Q
13
0
Q
12
1
Q
11
2
Q
10
3
9
MR
handbook, halfpage
Fig.1 Pin configuration.
1
OE
D
4
D
5
D
6
D
7
SI
3
15
SO
Q
13
MR
9
Q
Q
Q
DOR
DIR
0
1
2
3
MGA674
12
11
10
14
2
0
1
2
3
handbook, halfpage
1
3
9
15
4
5
6
7
EN4
1Z2
1 ( /C2)
CT = 0
5
5Z6
2D
FIFO 64 x 4
CTR
<
CT 64
CT 0
>
[IR] 3
[OR] 6
G1
G5
MGA676
2
14
13
4
12
11
10
Fig.2 Logic symbol.
September 1993 3
Fig.3 IEC logic symbol.
Page 4
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
SI
DIR
DATA INPUT
4
MR
OE
FUNCTIONAL DESCRIPTION
A DIR flag indicates the input stage
status, either empty and ready to
receive data (DIR = HIGH) or full and
busy (DIR = LOW). When DIR and SI
are HIGH, data present at D0 to D3 is
shifted into the input stage; once
complete DIR goes LOW. When SI is
set LOW, data is automatically shifted
to the output stage or to the last
empty location. A FIFO which can
receive data is indicated by DIR set
HIGH.
SI
B
DIR
B
4
D
nB
MR
SI
DIR
D
nA
A
A
MR
7403
FIFO A
DOR
OE
SO
Q
A
A
nA
Fig.4 Functional diagram.
Expanded format (see Fig.17)
The DOR and DIR signals are used to
allow the “7403” to be cascaded. Both
parallel and serial expansion is
possible.
Serial expansion is only possible with
typical devices.
Parallel expansion
Parallel expansion is accomplished
by logically ANDing the DOR and DIR
signals to form a composite signal.
7403
FIFO B
DOR
OE
4
DOR
SO
DATA OUTPUT
SO
Q
B
B
nB
MGA679
Serial expansion
Serial expansion is accomplished by:
• tying the data outputs of the first
device to the data inputs of the
second device
• connecting the DOR pin of the first
device to the SI pin of the second
device
• connecting the SO pin of the first
device to the DIR pin of the second
device.
A DOR flag indicates the output stage
status, either data available (DOR =
HIGH) or busy (DOR = LOW). When
SO and DOR are HIGH, data is
available at the outputs (Q0 to Q3).
When SO is set LOW new data may
be shifted into the output stage, once
complete DOR is set HIGH.
September 1993 4
Page 5
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
DOR
ll pagewidth
SO
FP
(1)
R
SQ
R
61 x
FB
(1)
R
(2)
FF64
R
RQ
to
FF3
FF63
R
RQ
SQ
SQ
SQ
OE
Q0Q
CL CL
CL CL
1
3-STATE
4
4
OUTPUT
LATCHES
LATCHES
Q2Q
BUFFER
3
MSB118
position 64
position 3 to 63
Fig.5 Logic diagram.
(2)
FF2
RQ
SQ
R
(2)
FF1
SQ
R
FS
SQ
R
MR
RQ
(1)
SI
September 1993 5
DIR
4
CL CL
CL CL
D0D1D2D
LATCHES
4
LATCHES
3
position 2
position 1
R input of FF1 to FF64 will set Q output to LOW independent of state on S input.
S input of flip-flops FS, FB and FP will set Q output to HIGH independent of state on R input.
LOW on
(see control flip-flops)
LOW on
Page 6
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
valid for driver output.
They are replaced by the values given below.
Output capability: driver 8 mA
ICC category: LSI.
Voltages are referenced to GND (ground = 0 V).
DC CHARACTERISTICS FOR 74HC
SYMBOL PARAMETER
+25 −40 to +85 −40 to +125
MIN TYP MAX MIN MAX MIN MAX
V
OH
V
OH
HIGH level
output voltage
all outputs
HIGH level
output voltage
1.9
4.4
5.9
3.98
5.48
2.0
4.5
6
4.32
5.81−−
driver outputs
V
OL
V
OL
LOW level
output voltage
all outputs
LOW level
output voltage
−
−
−
−
−
0
0
0
0.15
0.15
driver outputs
T
−
−
−
0.1
0.1
0.1
0.26
0.26−−
(°C)
amb
1.9
4.4
5.9
3.84
5.34−−
−
−
−
−
−
−
0.1
0.1
0.1
0.33
0.33−−
1.9
4.4
5.9
3.70
5.20−−
−
−
−
−
−
−
0.1
0.1
0.1
0.40
0.40VV
, except that VOH and VOL are not
TEST CONDITION
UNIT
V
V
V
V
V
V
V
V
V
(V)
2.0
4.5
6.0
4.5
6.0
2.0
4.5
6.0
4.5
6.0
CC
V
or
V
V
or
V
V
or
V
V
or
V
V
I
IH
IL
IH
IL
IH
IL
IH
IL
OTHER
IO = −20 µA
IO = −8 mA
IO = −10 mA
IO = 20 µA
IO = 8 mA
IO = 10 mA
September 1993 6
Page 7
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= tf = 6 ns; CL = 50 pF.
r
SYMBOL PARAMETER
t
PHL/tPLH
propagation
delay
MR to DIR,
DOR
t
PHL
propagation
delay
t
PHL/tPLH
MR to Q
propagation
n
delay
SI to DIR
t
PHL/tPLH
propagation
delay
SO to DOR
t
PHL/tPLH
propagation
delay
t
PHL/tPLH
DOR to Q
propagation
n
delay
t
PLH
SO to Q
propagation
n
delay/ripple
through delay
SI to DOR
t
PLH
propagation
delay/bubble-up
delay
SO to DIR
t
PZH/tPZL
3-state output
enable
t
PHZ/tPLZ
OE to Q
3-state output
n
disable
t
THL/tTLH
OE to Q
output
n
transition time−−
t
W
SI pulse
width
HIGH or LOW
t
W
SO pulse
width
HIGH or LOW
(°C)
T
amb
+25 −40 to +85 −40 to +125
MIN TYP MAX MIN MAX MIN MAX
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
35
7
6.0
70
14
12
69
25
20
52
19
15
66
24
19
94
34
27
11
4
3
105
38
30
2.2
0.8
0.6
2.8
1.0
0.8
44
16
13
50
18
14
14
5
4
11
4
3
22
8
6.0
210
42
36
160
32
27
205
41
35
290
58
49
35
7
6.0
325
65
55
7
1.4
1.2
9
1.8
1.5
150
30
26
150
30
26
60
12
10
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
45
9
8
90
18
15
265
53
45
200
40
34
255
51
43
365
73
62
45
9
8
406
81
69
8.8
1.8
1.5
11.2
2.2
1.9
190
38
32
190
38
33
75
15
13
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
55
11
9
105
21
18
315
63
54
240
48
41
310
62
53
435
87
74
55
11
9
488
98
83
10.5
2.1
1.8
13.5
2.7
2.3
225
45
38
225
45
38
90
18
15
−
−
−
−
−
−
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TEST CONDITION
V
CC
(V)
2.0
WAVEFORMS
Fig.8
4.5
6.0
2.0
Fig.8
4.5
6.0
2.0
Fig.6
4.5
6.0
2.0
Fig.9
4.5
6.0
2.0
Fig.10
4.5
6.0
2.0
Fig.14
4.5
6.0
2.0
Fig.10
4.5
6.0
2.0
Fig.7
4.5
6.0
2.0
Fig.16
4.5
6.0
2.0
Fig.16
4.5
6.0
2.0
Fig.16
4.5
6.0
2.0
Fig.6
4.5
6.0
2.0
Fig.9
4.5
6.0
September 1993 7
Page 8
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
T
SYMBOL PARAMETER
t
W
DIR pulse width
HIGH
t
W
DOR pulse
width HIGH
t
W
MR pulse width
LOW
t
rem
removal time
MR to SI
t
su
set-up time
Dn to SI
t
h
hold time
Dn to SI
f
max
maximum
clock pulse
frequency
SI, SO burst
mode
f
max
maximum clock
pulse frequency
SI, SO using
flags
f
max
maximum clock
pulse frequency
SI, SO
cascaded
(°C)
amb
+25 −40 to +85 −40 to +125
MIN TYP MAX MIN MAX MIN MAX
10
5
4
14
7
6.0
120
24
20
80
16
14
−8
−4
−3
135
27
23
3.6
18
21
3.6
18
21
−
−
−
41
15
12
52
19
15
39
14
11
24
8
7
−36
−13
−10
44
16
13
9.9
30
36
9.9
30
36
7.6
23
27
130
26
22
160
32
27
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
8
4
3
12
6
5
150
30
26
100
20
17
−6
−3
−3
170
34
29
2.8
14
16
2.8
14
16
−
−
−
165
33
28
200
40
34
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
8
4
3
12
6.0
5.0
180
36
31
120
24
20
−6
−3
−3
205
41
35
2.4
12
14
2.4
12
14
−
−
−
195
39
33
240
48
41
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
TEST CONDITION
V
CC
(V)
2.0
WAVEFORMS
Fig.7
4.5
6.0
2.0
Fig.10
4.5
6.0
2.0
Fig.8
4.5
6.0
2.0
Fig.15
4.5
6.0
2.0
Fig.13
4.5
6.0
2.0
Fig.13
4.5
6.0
2.0
Figs 11 and 12
4.5
6.0
2.0
Figs 6 and 9
4.5
6.0
2.0
Figs 6 and 9
4.5
6.0
September 1993 8
Page 9
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
valid for driver output.
They are replaced by the values given below.
Output capability: driver 8 mA.
ICC category: LSI.
Voltages are referenced to GND (ground = 0 V).
DC CHARACTERISTICS FOR 74HCT
SYMBOL PARAMETER
+25 −40 to +85 −40 to +125
MIN TYP MAX MIN MAX MIN MAX
V
OH
HIGH level
4.4 4.5 − 4.4 − 4.4 − V 4.5 V
output voltage
all outputs
V
OH
HIGH level
3.98 4.32 − 3.84 − 3.7 − V 4.5 V
output voltage
driver outputs
V
OL
LOW level
− 0 0.1 − 0.1 − 0.1 V 4.5 V
output voltage
all outputs
V
OL
LOW level
− 0.15 0.26 − 0.33 − 0.4 V 4.5 V
output voltage
driver outputs
T
amb
(°C)
, except that VOH and VOL are not
TEST CONDITION
UNIT
V
(V)
CC
V
I
IH
OTHER
IO = −20 µA
or
V
IL
IH
IO = −8 mA
or
V
IL
IH
IO = 20 µA
or
V
IL
IH
IO = 8 mA
or
V
IL
Notes to the HCT DC Characteristics
1. The value of additional quiescent supply current (∆I
) for a unit load of 1 is given in the family specifications.
CC
2. To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
UNIT LOAD COEFFICIENT
INPUT UNIT LOAD COEFFICIENT
OE 1
SI 1.5
D
n
0.75
MR 1.5
SO 1.5
September 1993 9
Page 10
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
= tf = 6 ns; CL = 50 pF
r
SYMBOL PARAMETER
t
PHL/tPLH
propagation
delay
MR to DIR,
DOR
t
PHL
propagation
delay
t
PHL/tPLH
MR to Q
propagation
n
delay
SI to DIR
t
PHL/tPLH
propagation
delay
SO to DOR
t
PHL/tPLH
propagation
delay
t
PHL/tPLH
SO to Q
propagation
n
delay
t
PLH
DOR to Q
propagation
n
delay/ripple
through delay
SI to DOR
t
PLH
propagation
delay/bubble-up
delay
SO to DIR
t
PZH/tPZL
3-state output
enable time
t
PHZ/tPLZ
OE to Q
3-state output
n
disable time
t
THL/tTLH
OE to Q
output transition
n
time
t
W
SI pulse width
HIGH or LOW
t
W
SO pulse width
HIGH or LOW
t
W
DIR pulse width
HIGH
(°C)
T
amb
−25 −40 to +85 −40 to +125
MIN TYP MAX MIN MAX MIN MAX
UNIT
TEST CONDITION
V
CC
(V)
WAVEFORMS
− 30 51 − 53 − 63 ns 4.5 Fig.8
− 22 38 − 48 − 57 ns 4.5 Fig.8
− 25 43 − 54 − 65 ns 4.5 Fig.6
− 36 61 − 76 − 92 ns 4.5 Fig.9
− 42 72 − 90 − 108 ns 4.5 Fig.14
− 712−15 − 18 ns 4.5 Fig.10
− 0.8 1.4 − 1.75 − 2.1 µs 4.5 Fig.10
− 1 1.8 − 2.25 − 2.7 µs 4.5 Fig.7
− 16 30 − 38 − 45 ns 4.5 Fig.16
− 19 30 − 38 − 45 ns 4.5 Fig.16
− 512−15 − 18 ns 4.5 Fig.16
95−6−8−ns 4.5 Fig.6
14 8 − 18 − 21 − ns 4.5 Fig.9
5 17 29 4 36 4 44 ns 4.5 Fig.7
September 1993 10
Page 11
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
T
SYMBOL PARAMETER
t
W
DOR pulse
width
HIGH
t
W
MR pulse width
LOW
t
rem
removal time
MR to SI
t
su
set-up time
Dn to SI
t
h
hold time
Dn to SI
f
max
maximum
clock pulse
frequency
SI, SO burst
mode
f
max
maximum
clock pulse
frequency
SI, SO using
flags
f
max
maximum
clock pulse
frequency
SI, SO
cascaded
(°C)
amb
−25 −40 to +85 −40 to +125
UNIT
MIN TYP MAX MIN MAX MIN MAX
7 21 36 6.0 45 6.0 54 ns 4.5 Fig.10
26 15 − 33 − 39 − ns 4.5 Fig.8
18 10 − 23 − 27 − ns 4.5 Fig.15
−5 −16 −−4−−4−ns 4.5 Fig.13
30 18 − 38 − 45 − ns 4.5 Fig.13
18 30 − 14 − 12 − MHz 4.5 Figs 11 and 12
18 30 − 14 − 12 − MHz 4.5 Figs 6 and 9
− 23 −−−−−MHz 4.5 Figs 6 and 9
TEST CONDITION
V
CC
(V)
WAVEFORMS
September 1993 11
Page 12
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
AC WAVEFORMS
Shifting in sequence FIFO empty to FIFO full
handbook, full pagewidth
SI INPUT
DIR OUTPUT
Dn INPUT
(1) HC : VM = 50%; VI = GND to VCC.
= 1.3 V; VI = GND to 3 V.
HCT: V
M
1st word 2nd word 64th word
1/ f max
(1)
t
V
PLH
M
t
W
2
t
PHL
15
(1)
V
M
64
73
MGA659
Fig.6 Waveforms showing the SI input to DIR output propagation delay, the SI pulse width and SI maximum
pulse frequency.
Notes to Fig.6
1. DIR initially HIGH; FIFO is prepared for valid data
2. SI set HIGH; data loaded into input stage
3. DIR goes LOW, input stage “busy”
4. SI set LOW; data from first location “ripple through”
5. DIR goes HIGH, status flag indicates FIFO prepared for additional data
6. Repeat process to load 2nd word through to 64th word into FIFO
DIR remains LOW; with attempt to shift into full FIFO, no data transfer occurs.
September 1993 12
Page 13
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
With FIFO full; SI held HIGH in anticipation of empty location
handbook, full pagewidth
SO INPUT
SI INPUT
DIR OUTPUT
(1) HC : VM = 50%; VI = GND to VCC.
= 1.3 V; VI = GND to 3 V.
HCT: V
M
(1)
1
V
M
(1)
2
V
M
t
PLH
bubble - up
delay
t
W
(1)
V
M
34
5
MGA660
Fig.7 Waveforms showing bubble-up delay, SO input to DIR output and DIR output pulse width.
Notes to Fig.7
1. FIFO is initially full, shift-in is held HIGH
SO pulse; data in the output stage is unloaded, “bubble-up” process of empty location begins
2.
3. DIR HIGH; when empty location reaches input stage, flag indicates FIFO is prepared for data input
4. DIR returns to LOW; data shift-in to empty location is complete, FIFO is full again
5. SI set LOW; necessary to complete shift-in process, DIR remains LOW, because FIFO is full.
September 1993 13
Page 14
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
Master reset applied with FIFO full
handbook, halfpage
t
PLH
t
PHL
(1)
M
t
W
(1)
V
M
3
MR INPUT V
DIR OUTPUT
2
1
t
PHL
4
(1)
V
M
5
MGA668
(1) HC : VM = 50%; VI = GND to VCC.
= 1.3 V; VI = GND to 3 V.
HCT: V
M
DOR OUTPUT
Qn OUTPUT
Fig.8 Waveforms showing the MR input to DIR, DOR and Qn output propagation delays and the MR pulse width.
Notes to Fig.8
1. DIR LOW, output ready HIGH; assume FIFO is full
2. MR pulse LOW; clears FIFO
3. DIR goes HIGH; flag indicates input prepared for valid data
4. DOR goes LOW; flag indicates FIFO empty
5. Qn outputs go LOW (only last bit will be reset).
September 1993 14
Page 15
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
handbook, full pagewidth
SO INPUT
DOR OUTPUT
Qn OUTPUT
(1) HC : VM = 50%; VI = GND to VCC.
= 1.3 V; VI = GND to 3 V.
HCT: V
M
1st SO pulse 2nd SO pulse 64th SO pulse
1/ f
max
(1)
t
V
PLH
M
t
W
(1)
V
M
2
t
PHL
15
1st word 2nd word 64th word
(1)
V
M
64
73
MGA661
Fig.9 Waveforms showing the SO input to DOR output propagation delay. The SO pulse widths and maximum
pulse frequency.
Notes to Fig.9
1. DOR HIGH; no data transfer in progress, valid data is present at output stage
2. SO set HIGH; results in DOR going LOW
3. DOR goes LOW; output stage “busy”
4. SO set LOW; data in the input stage is unloaded, and new data replaces it as empty location “bubbles-up” to input
stage
5. DOR goes HIGH; transfer process completed, valid data present at output after the specified propagation delay
6. Repeat process to unload the 3rd through to the 64th word from FIFO
7. DOR remains LOW; FIFO is empty.
September 1993 15
Page 16
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
With FIFO empty; SO is held HIGH in anticipation
handbook, full pagewidth
(1) HC : VM = 50%; VI = GND to VCC.
= 1.3 V; VI = GND to 3 V.
HCT: V
M
SI INPUT
SO INPUT
DOR OUTPUT
Q OUTPUT
n
(1)
1
V
M
(1)
2
V
M
6
t
PLH
ripple through
delay
35
t
W
(1)
V
M
t
t
PLH
PHL
4
MGA658
Fig.10 Waveforms showing ripple through delay SI input to DOR output, DOR output pulse width and propagation
delay from the DOR pulse to the Qnoutput.
Notes to Fig.10
1. FIFO is initially empty,
SO is held HIGH
2. SI pulse; loads data into FIFO and initiates ripple through process
3. DOR flag signals the arrival of valid data at the output stage
4. Output transition; data arrives at output stage after the specified propagation delay between the rising edge of the
DOR pulse to the Qn output
5. DOR goes LOW; data shift-out is complete, FIFO is empty again
6. SO set LOW; necessary to complete shift-out process. DOR remains LOW, because FIFO is empty.
September 1993 16
Page 17
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
Shift-in operation; high-speed burst mode
1/ f
handbook, full pagewidth
SI INPUT
Dn INPUT
DIR OUTPUT
(1)
V
M
max
t
W
MGA662
(1) HC : VM = 50%; VI = GND to VCC.
= 1.3 V; VI = GND to 3 V.
HCT: V
M
Fig.11 Waveforms showing SI minimum pulse width and maximum pulse frequency, in high-speed shift-in burst
mode.
Note to Fig.11
In the high-speed mode, the burst-in rate is determined by the minimum shift-in HIGH and shift-in LOW specifications.
The DIR status flag is a don't care condition, and a shift-in pulse can be applied regardless of the flag. A SI pulse which
would overflow the storage capacity of the FIFO is ignored.
September 1993 17
Page 18
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
Shift-out operation; high-speed burst mode
1/ f
handbook, full pagewidth
SO INPUT
Qn OUTPUT
DOR OUTPUT
(1)
V
M
max
t
W
MGA663
(1) HC : VM = 50%; VI = GND to VCC.
= 1.3 V; VI = GND to 3 V.
HCT: V
M
Fig.12 Waveforms showing SO minimum pulse width and maximum pulse frequency, in high-speed shift-out
burst mode.
Note to Fig.12
In the high-speed mode, the burst-out rate is determined by the minimum shift-out HIGH and shift-out LOW
specifications. The DOR flag is a don't care condition and an
SO pulse can be applied without regard to the flag.
September 1993 18
Page 19
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
handbook, full pagewidth
Dn INPUT
SI INPUT
(1) HC : VM = 50%; VI = GND to VCC.
The shaded areas indicate when the input is permitted to change for predictable output performance.
= 1.3 V; VI = GND to 3 V.
HCT: V
M
(1)
V
M
t
su
t
h
(1)
V
M
Fig.13 Waveforms showing hold and set-up times for Dn input to SI input.
t
su
t
h
MGA657
handbook, full pagewidth
(1) HC : VM = 50%; VI = GND to VCC.
= 1.3 V; VI = GND to 3 V.
HCT: V
M
SO INPUT
Qn OUTPUT
MGA664
(1)
V
M
t
PLH
t
TLH
Fig.14 Waveforms showing SO input to Qn output propagation delays and output transition time.
September 1993 19
t
PHL
(1)
V
M
t
THL
Page 20
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
handbook, halfpage
(1)
t
V
rem
M
(1)
V
M
MGA665
MR INPUT
SI INPUT
(1) HC : VM = 50%; VI = GND to VCC.
handbook, full pagewidth
= 1.3 V; VI = GND to 3 V.
HCT: V
M
Fig.15 Waveform showing the MR input to SI input removal time.
t
outputs
disabled
f
t
PZL
(1)
V
M
t
PZH
(1)
V
M
outputs
enabled
OE INPUT
Q OUTPUT
n
LOW - to - OFF
OFF - to - LOW
Q OUTPUT
n
HIGH - to - OFF
OFF - to - HIGH
MGA656
10 %
t
r
V
90 %
(1)
M
t
PLZ
t
PHZ
outputs
enabled
10 %
90 %
(1) HC : VM = 50%; VI = GND to VCC.
= 1.3 V; VI = GND to 3 V.
HCT: V
M
Fig.16 Waveforms showing the 3-state enable and disable times for input OE.
September 1993 20
Page 21
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
APPLICATION INFORMATION
handbook, full pagewidth
8-bit
data
DIR
MR
OE
SO
8-bit
data
DOR
SI
SI DOR
OE
D
0
D
1
7403
D
2
D
3
DIR
SI DOR
OE
D
0
D
1
7403
D
2
D
3
DIR
Q
0
Q
1
Q
2
Q
3
SOMR
Q
0
Q
1
Q
2
Q
3
SOMR
SI DOR
OE
D
0
D
1
7403
D
2
D
3
DIR
SI DOR
OE
D
0
D
1
7403
D
2
D
3
DIR
Q
0
Q
1
Q
2
Q
3
SOMR
Q
0
Q
1
Q
2
Q
3
SOMR
MGA684
Fig.17 Expanded FIFO (parallel and serial) for increased word length; 8 bits wide x 64 n-bits.
September 1993 21
Page 22
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
handbook, full pagewidth
DATA INPUT
COMPOSITE
DIR
FLAG
DATA INPUT DATA OUTPUT
SI
MR
4 4
4 4
D
DIR
SI
MR
DIR
SI
MR
D
n
n
7403
7403
Q
DOR
SO
OE
DOR
SO
OE
Q
MGA678
n
n
DATA OUTPUT
COMPOSITE
DOR
FLAG
SO
OE
Fig.18 Expanded FIFO for increased word length; 64 words x 10 bits.
Note to Fig.18
The “7403” is easily expanded to increase word length. Composite DIR and DOR flags are formed with the addition of
an AND gate. The basic operation and timing are identical to a single FIFO, with the exception of an added gate delay
on the flags.
September 1993 22
Page 23
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
handbook, full pagewidth
composite
DIR
DQ
74
CP
Q
DQ
CP
Q
R
4
D
n
DIR
7403
SI
MR
DIR
SI
SI
7403
MR
MR
4 4
D
n
Q
DOR
SO
OE
DOR
SO
OE
Q
4
n
DQ
74
CP
Q
DQ
CP
SO
OE
n
Q
R
MGA683
composite
DOR
Fig.19 Expanded FIFO for increased word length.
Note to Fig.19
This circuit is only required if the SI input is constantly held HIGH, when the FIFO is empty and the automatic shift-in
cycles are started or if SO output is constantly held HIGH, when the FIFO is full and the automatic shift-out cycles are
started (see Figs 7 and 10).
September 1993 23
Page 24
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
Expanded format
Figure 20 shows two cascaded FIFOs
providing a capacity of 128 words x
4 bits. Figure 21 shows the signals on
the nodes of both FIFOs after the
application of a SI pulse, when both
FIFOs are initially empty. After a
ripple through delay, data arrives at
the output of FIFOA. Due to SO
A
being HIGH, a DORA pulse is
generated. The requirements of SI
SI
DIR
DATA INPUT
B
4
and DnB are satisfied by the DOR
pulse width and the timing between
the rising edge of DORA and QnA.
After a second ripple through delay,
data arrives at the output of FIFOB.
Figure 22 shows the signals on the
nodes of both FIFOs after the
application of aSOB pulse, when both
FIFOs are initially full. After a
bubble-up delay a DIRB pulse is
generated, which acts as aSOA pulse
SI
B
DIR
B
4
D
nB
MR
SI
DIR
D
nA
A
A
MR
7403
FIFO A
DOR
OE
SO
Q
A
A
nA
7403
FIFO B
A
DOR
OE
for FIFOA. One word is transferred
from the output of FIFOA to the input
of FIFOB. The requirements of the
SOA pulse for FIFOA is satisfied by
the pulse width of DORB. After a
second bubble-up delay an empty
space arrives at DnA, at which time
DIRA goes HIGH. Figure 23 shows
the waveforms at all external nodes of
both FIFOs during a complete shift-in
and shift-out sequence.
4
DOR
SO
DATA OUTPUT
SO
Q
B
B
nB
MR
OE
MGA679
Fig.20 Cascading for increased word capacity; 128 words x 4 bits.
Note to Fig.20
The “7403” is easily cascaded to increase word capacity without any external circuitry. In cascaded format, all necessary
communications are handled by the FIFOs. Figures 21 and 22 demonstrate the intercommunication timing between
and FIFOB. Figure 23 provides an overview of pulses and timing of two cascaded FIFOs, when shifted full and
FIFO
A
shifted empty again.
September 1993 24
Page 25
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
handbook, full pagewidth
DIR
SI
A
DOR
DIR
Q
nA nB
DOR
Q
nB
(1)
A
SI
B
A
SO
1
A
B
D
B
V
M
(1)
V
M
2
ripple through
delay
4
(1)
V
M
(1)
56
V
M
3
ripple through
delay
7
V
(1)
M
MGA666
Fig.21 FIFO to FIFO communication; input timing under empty condition.
Notes to Fig.21
1. FIFOA and FIFOB initially empty, SOA held HIGH in anticipation of data
2. Load one word into FIFOA; SI pulse applied, results in DIR pulse
3. Data-outA/data-inB transition; valid data arrives at FIFOA output stage after a specified delay of the DOR flag,
meeting data input set-up requirements of FIFO
B
4. DORA and SIB pulse HIGH; (ripple through delay after SIA LOW) data is unloaded from FIFOA as a result of the data
output ready pulse, data is shifted into FIFO
B
5. DIRB and SOA go LOW; flag indicates input stage of FIFOB is busy, shift-out of FIFOA is complete
6. DIRB and SOA go HIGH automatically; the input stage of FIFOB is again able to receive data, SO is held HIGH in
anticipation of additional data
7. DORB goes HIGH; (ripple through delay after SIB LOW) valid data is present one propagation delay later at the FIFO
output stage.
September 1993 25
B
Page 26
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
handbook, full pagewidth
DOR
SO
DIR
DOR
Q
nA nB
DIR
(1)
V
B
B
SO
A
B
SI
1
B
A
D
A
M
(1)
V
M
2
bubble - up
delay
3
(1)
V
M
(1)
4
V
M
5
bubble - up
delay
V
M
MGA667
6
(1)
Fig.22 FIFO to FIFO communication; output timing under full condition.
Notes to Fig.22
1. FIFOA and FIFOB initially full, SIB held HIGH in anticipation of shifting in new data as an empty location bubbles-up
2. Unload one word from FIFOB; SO pulse applied, results in DOR pulse
3. DIRB and SOA pulse HIGH; (bubble-up delay after SOB LOW) data is loaded into FIFOB as a result of the DIR pulse,
data is shifted out of FIFO
A
4. DORA and SIB go LOW; flag indicates the output stage of FIFOA is busy, shift-in to FIFOB is complete
5. DORA and SIB go HIGH; flag indicates valid data is again available at FIFOA output stage, SIB is held HIGH, awaiting
bubble-up of empty location
6. DIRA goes HIGH; (bubble-up delay after SOA LOW) an empty location is present at input stage of FIFOA.
September 1993 26
Page 27
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
handbook, full pagewidth
SO INPUT
B
DORB OUTPUT
Q OUTPUT
nB
DIRB OUTPUT
DORA OUTPUT
QnA OUTPUT
DIRA OUTPUT
SI INPUT
A
sequence 1 sequence 2 sequence 3 sequence 4 sequence 5 sequence 6
(8)
(3) (4)
(13)
(12)
(1)
(2)
(5)
(9)
(6)
(10)
(7)
(11)
(14)
D INPUT
nA
MR INPUT
MGA687
Fig.23 Waveforms showing the functionality and intercommunication between two FIFOs (refer to Fig.18).
Note to Fig.23
Sequence 1 (both FIFOS empty, starting SHIFT-IN process)
MR pulse has been applied FIFOA and FIFOB are empty. The DOR flags of FIFOA and FIFOB go LOW due to no
After a
valid data being present at the outputs. The DIR flags are set HIGH due to the FIFOs being ready to accept data. SO
is held HIGH and two SIA pulses are applied (1). These pulses allow two data words to ripple through to the output stage
of FIFOA and to the input stage of FIFOB (2). When data arrives at the output of FIFOB, a DORB pulse is generated (3).
When SOB goes LOW, the first bit is shifted out and a second bit ripples through to the output after which DORB goes
HIGH (4).
B
September 1993 27
Page 28
Philips Semiconductors Product specification
4-Bit x 64-word FIFO register; 3-state 74HC/HCT7403
Sequence 2 (FIFOB runs full)
After the
MR pulse, a series of 64 SI pulses are applied. When 64 words are shifted in, DIRB remains LOW due to FIFO
being full (5). DORA goes LOW due to FIFOA being empty.
Sequence 3 (FIFO
When 65 words are shifted in, DOR
runs full)
A
remains HIGH due to valid data remaining at the output of FIFOA. QnA remains
A
HIGH, being the polarity of the 65th data word (6). After the 128th SI pulse, DIR remains LOW and both FIFOs are full
(7). Additional pulses have no effect.
Sequence 4 (both FIFOs full, starting SHIFT-OUT process)
SI
is held HIGH and two SOB pulses are applied (8). These pulses shift out two words and thus allow two empty
A
locations to bubble-up to the input stage of FIFOB, and proceed to FIFOA (9). When the first empty location arrives at the
input of FIFOA, a DIRA pulse is generated (10) and a new word is shifted into FIFOA. SIA is made LOW and now the
second empty location reaches the input stage of FIFOA, after which DIRA remains HIGH (11).
Sequence 5 (FIFO
At the start of sequence 5 FIFO
runs empty)
A
contains 63 valid words due to two words being shifted out and one word being shifted
A
in, in sequence 4. An additional series of SOB pulses are applied. After 63 SOB pulses, all words from FIFOA are shifted
into FIFOB. DORA remains LOW (12).
Sequence 6 (FIFO
After the next
runs empty)
B
SOB pulse, DIRB remains HIGH due to the input stage of FIFOB being empty. After another 63 SOB pulses,
DORB remains LOW due to both FIFOs being empty (14). Additional SOB pulses have no effect. The last word remains
available at the output Qn.
B
PACKAGE OUTLINES
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
See
.
September 1993 28
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