Datasheet 74 hct73 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT73

Dual JK flip-flop with reset;
negative-edge trigger

Product specification
File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product specification

Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT73

FEATURES

• Output capability: standard

• ICC category: flip-flops

The 74HC/HCT73 are dual negative-edge triggered
JK-type flip-flops featuring individual J, K, clock (n
reset (nR) inputs; also complementary Q and Q outputs.

The J and K inputs must be stable one set-up time prior to
the HIGH-to-LOW clock transition for predictable

GENERAL DESCRIPTION

The 74HC/HCT73 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.

operation.
The reset (nR) is an asynchronous active LOW input.

When LOW, it overrides the clock and data inputs, forcing
the Q output LOW and the Q output HIGH.

Schmitt-trigger action in the clock input makes the circuit
highly tolerant to slower clock rise and fall times.

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

SYMBOL PARAMETER CONDITIONS

/ t

t

PHL

PLH

f

max

C

I

C

PD

propagation delay CL= 15 pF; VCC=5 V

n

CP to nQ 16 15 ns

n

CP to nQ 1618ns

n

R to nQ, nQ 1515ns
maximum clock frequency 77 79 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per flip-flop notes 1 and 2 30 30 pF

CP) and

TYPICAL

UNIT

HC HCT

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V

2

× fi+∑(CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF
VCC= supply voltage in V

2. For HC the condition is VI= GND to V

CC

For HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

.

December 1990 2

Philips Semiconductors Product specification

Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT73

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

1, 5 1
2, 6 1
4V
11 GND ground (0 V)
12, 9 1Q, 2Q true flip-flop outputs
13, 8 1
14, 7, 3, 10 1J, 2J, 1K, 2K synchronous inputs; flip-flops 1 and 2

CP, 2CP clock input (HIGH-to-LOW, edge-triggered)
R, 2R asynchronous reset inputs (active LOW)

CC

Q, 2Q complement flip-flop outputs

positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3

Philips Semiconductors Product specification

Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT73

FUNCTION TABLE

OPERATING

MODE

asynchronous reset L X X X L H

toggle
load “0” (reset)
load “1” (set)
hold “no change”

Notes

1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP

transition
L = LOW voltage level
I = LOW voltage level one set-up time prior to the HIGH-to-LOW CP

transition

q = lower case letters indicate the state of the referenced output one

set-up time prior to the HIGH-to-LOW CP transition
X = don’t care
↓ = HIGH-to-LOW CP transition

nRnCP J K Q Q

H
H
H
H

INPUTS OUTPUTS

↓
↓
↓
↓

h

l

h

l

h
h

l
l

q
L

H

q

q

H

L
q

Fig.4 Functional diagram.

Fig.5 Logic diagram (one flip-flop).

December 1990 4

Philips Semiconductors Product specification

Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT73

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

Output capability: standard
ICC category: flip-flops

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

SYMBOL PARAMETER

t

PHL

/ t

propagation delay

PLH

nCP to nQ

t

PHL

/ t

propagation delay

PLH

nCP to nQ

t

PHL

/ t

propagation delay

PLH

nR to nQ, nQ

t

THL

t

W

/ t

output transition time 19

TLH

clock pulse width

HIGH or LOW

t

W

reset pulse width

HIGH or LOW

t

rem

removal time

nR to nCP

t

su

set-up time

nJ, nK to nCP

t

h

hold time

nJ, nK to nCP

f

max

maximum clock pulse

frequency

(°C) TEST CONDITIONS

T

amb

74HC

min. typ. max. min. max. min. max.

52

80
16
14

80
16
14

80
16
14

80
16
14

3
3
3

6.0
30
35

19
15

52
19
15

50
18
14

7
6

22
8
6

22
8
6

22
8
6

22
8
6

−8

−3

−2

23
70
83

160
32
27

160
32
27

145
29
25

75
15
13

100
20
17

100
20
17

100
20
17

100
20
17

3
3
3

4.8
24
28

200
40
34

200
40
34

180
36
31

95
19
16

240
48
41

240
48
41

220
44
38

110
22
19

120
24
20

120
24
20

120
24
20

120
24
20

3
3
3

4.0
20
24

.

UNIT

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

MHz 2.0

V

(V)

4.5

6.0

4.5

6.0

4.5

6.0

4.5

6.0

4.5

6.0

4.5

6.0

4.5

6.0

4.5

6.0

4.5

6.0

4.5

6.0

CC

WAVEFORMS+25 −40 to +85 −40 to +125

Fig.6

Fig.6

Fig.7

Fig.6

Fig.6

Fig.7

Fig.7

Fig.6

Fig.6

Fig.6

December 1990 5

Philips Semiconductors Product specification

Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT73

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

.

Output capability: standard
ICC category: flip-flops

Note to HCT types

The value of additional quiescent supply current (∆I

) for a unit load of 1 is given in the family specifications.

CC

To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT UNIT LOAD COEFFICIENT

nK
nR
nCP, nJ

0.60

0.65

1.00

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

(°C) TEST CONDITIONS

T

amb

74 HCT

SYMBOL PARAMETER

+25 −40 to +85 −40 to +125

UNIT

V

(V)

CC

min. typ. max. min. max. min. max.

t

PHL

/ t

propagation delay

PLH

18 38 48 57 ns 4.5 Fig.6

nCP to nQ

t

PHL

/ t

propagation delay

PLH

21 36 45 54 ns 4.5 Fig.6

nCP to nQ

t

PHL

/ t

propagation delay

PLH

20 34 43 51 ns 4.5 Fig.7

nR to nQ, nQ

t

THL

/ t

output transition time 7 15 19 22 ns 4.5 Fig.6

TLH

WAVEFORMS

t

W

clock pulse width

16 8 20 24 ns 4.5 Fig.6

HIGH or LOW

t

W

reset pulse width

18 9 23 27 ns 4.5 Fig.7

HIGH or LOW

t

rem

removal time

14 8 18 21 ns 4.5 Fig.7

nR to nCP

t

su

set-up time

12 6 15 18 ns 4.5 Fig.6

nJ, nK to nCP

t

h

hold time

3 −2 3 3 ns 4.5 Fig.6

nJ, nK to nCP

f

max

maximum clock pulse

30 72 24 20 MHz 4.5 Fig.6

frequency

December 1990 6

Philips Semiconductors Product specification

Dual JK flip-flop with reset; negative-edge trigger 74HC/HCT73

AC WAVEFORMS

The shaded areas indicate when the input is
permitted to change for predictable output
performance.

(1) HC : V

HCT: VM= 1.3 V; VI= GND to 3 V.

= 50%; VI= GND to VCC.

M

Fig.6 Waveforms showing the clock (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the J

and K to nCP set-up and hold times, the output transition times and the maximum clock pulse frequency.

(1) HC : VM= 50%; VI= GND to VCC.

HCT: VM= 1.3 V; VI= GND to 3 V.

Fig.7 Waveforms showing the reset (nR) input to output (nQ, nQ) propagation delays and the reset pulse width

and the nR to nCP removal time.

PACKAGE OUTLINES

“74HC/HCT/HCU/HCMOS Logic Package Outlines”

See

.

December 1990 7