Datasheet 74 hct652 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT652

Octal bus transceiver/register; 3-state

Product speciﬁcation File under Integrated Circuits, IC06

September 1993

Philips Semiconductors Product speciﬁcation

Octal bus transceiver/register; 3-state 74HC/HCT652

FEATURES

• Multiplexed real-time and stored data

• Independent register for A and B buses

• Independent enables for A and B buses

• 3-state

• Output capability: Bus driver

• Low power consumption by CMOS

technology

• ICC category: MSI.

APPLICATIONS

• Bus interfaces.

DESCRIPTION

The 74HC/HCT652 are high-speed SI-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in

compliance with Jedec standard no. 7A.

The 74HC/HCT652 consist of 8 non-inverting bus transceiver circuits with 3-state outputs, D-type flip-flops and central circuitry arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. Data on the “A” or “B” or both buses, will be stored in the internal registers, at the appropriate clock pins (CP

AB

or CPBA) regardless of the select pins (SAB and SBA) or output enable (OE

AB

and OEBA) control pins. Depending on the select inputs SAB and SBA data can directly go from input to output (real time mode) or data can be controlled by the clock (storage mode), this is when the output enable pins this operating mode permits. The output enable pins OEABand OE

BA

determine the operation mode of the transceiver. When OEABis LOW, no data transmission from Anto Bnis

possible and when OEBAis HIGH, there is no data transmission from B to Anpossible. When SABand SBAare in the real time transfer mode, it is also possible to store data without using the internal D-type flip-flops by simultaneously enabling OEABand OEBA. In this configuration each output reinforces its input. Thus when all other data sources to the two sets of bus lines are at high-impedance, each set of the bus lines will remain at its last state. This type differs from the HC/HCT646 in one extra bus-management function. This is the possibility to transfer stored “A data to the “B” bus and transfer stored ”B” data to the ”A” bus at the same time. The examples at the application information demonstrate all bus management functions. Schmitt-trigger action in the clock inputs makes the circuit highly tolerant to slower clock rise and fall times.

n

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns; VCC= 4.5 V; CL= 50 pF.

amb

SYMBOL PARAMETER CONDITIONS

t

PLH/tPZL

t

PHZ/tPZL

t

PHZ/tPLZ

f

max

C

I

C

PD

propagation delay An/Bnto Bn/A propagation delay CP propagation delay S

/CPBAto Bn/A

AB

AB/SBA

n

to Bn/A

n

3-state output enable time OEAB/OEBAto Bn/A 3-state output disable time OEAB/OEBAto Bn/A

n

CL= 15 pF; VCC=5 V

maximum clock frequency 92 92 MHz input capacitance 3.5 3.5 pF power dissipation capacitance per channel notes 1 and 2 26 28 pF

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V

2

× fi+ ∑ (CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz; CL= output load capacitance in pF; fo= output frequency in MHz; VCC= supply voltage in V; ∑ (CL× V

2. For HC the condition is VI= GND to V

2

× fo) = sum of the outputs

CC

For HCT the condition is VI= GND to VCC− 1.5 V

TYPICAL

UNIT

HC HCT

13 13 ns 18 20 ns 20 23 ns 14 15 ns 12 13 ns

September 1993 2

Philips Semiconductors Product speciﬁcation

Octal bus transceiver/register; 3-state 74HC/HCT652

ORDERING AND PACKAGE INFORMATION

TYPE NUMBER

PACKAGE

PINS PIN POSITION MATERIAL CODE

74HC/HCT652N 24 DIL plastic SOT101L 74HC/HCT652D 24 SO plastic SOT137A

PINNING

SYMBOL PIN DESCRIPTION

CP S OE A

AB

0

AB

..A

7

1 A to B clock input 2 select A to B source input 3 output enable A to B input

4..11 A data inputs/outputs GND 12 ground (0 V) B OE S CP V

7

BA

CC

..B

BA

0

13..20 B data inputs/outputs 21 output enable B to A input 22 select B to A source input 23 B to A clock input 24 positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

September 1993 3

Philips Semiconductors Product speciﬁcation

Octal bus transceiver/register; 3-state 74HC/HCT652

FUNCTION TABLE

AB

(1)

CP

BASABSBA

DATA I/O

A1THRU A

8

Input Input

INPUTS

OEABOE

BA

CP

L H H or L H or L X X LH↑↑X X Store A and B data

(2)

B1THRU B

OPERATION OR FUNCTION

8

HC/HCT652

Isolation

XH↑H or L X X Input Not speciﬁed Store A, Hold B

HH↑↑L X Input Output Store A in both registers

L X H or L ↑ X X Not speciﬁed Input Hold A, Store B LL↑↑X L Ouput Input Store B in both registers LLXXXL

L L X H or L X H Stored B Data to A Bus HHXXLX H H H or L X H X Stored A Data to B Bus

Ouput Input

Input Output

H L H or L H or L H H Output Output

Real Time B Data to A Bus

Real Time A Data to B Bus

Stored A Data to B Bus and Stored B Data to A Bus

Notes

1. H = HIGH voltage level L = LOW voltage level X = don’t care ↑ = LOW-to-HIGH transition

2. The data output functions may be enabled or disabled by various signals at OEABand OEBAinputs. Data input functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock inputs.

Fig.4 Functional diagram.

September 1993 4

Philips Semiconductors Product speciﬁcation

Octal bus transceiver/register; 3-state 74HC/HCT652

Fig.5 Logic diagram.

September 1993 5

Philips Semiconductors Product speciﬁcation

Octal bus transceiver/register; 3-state 74HC/HCT652

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

Output capability: bus driver ICC category: MSI.

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t

= 6 ns; CL= 50 pF.

r=tf

SYMBOL PARAMETER

t

PHL/tPLH

t

PHL/tPLH

t

PHL/tPLH

t

PZH/tPZL

propagation delay An, Bn to Bn, A

n

propagation delay CPAB, CPBAto Bn, A

propagation delay SAB, SBAto Bn, A

n

3-state output enable

n

time

t

PHZ/tPLZ

OEAB, OEBAto An, B 3-state output disable

n

time

t

THL/tTLH

t

W

OEAB, OEBAto An, B output transition time −

clock pulse width

n

HIGH or LOW

t

su

t

h

f

max

CPABor CP

set-up time An, Bn to CPAB, CP

hold time An, Bn to CPAB, CP

maximum clock pulse

BA

frequency

(°C)

T

amb

74HC

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

−

44

−

80 16 14

100 20 17

25 5 4

6.0 30 35

16 13

61 22 18

63 23 18

47 17 14

41 15 12

14 5 4

17 6 5

−8

−3

−2

16 83 98

135 27 23

190 38 32

195 39 33

150 30 26

60 12 10

−

100 20 17

125 25 21

30 6 5

4.8 24 28

170 34 29

240 48 41

245 49 42

190 38 33

75 15 13

−

120 24 20

150 30 26

35 7 6

4.0 20 24

205 41 35

285 57 48

295 59 50

225 45 38

90 18 15

−

.

UNIT

ns 2.0

MHz 2.0

TEST CONDITIONS

V

CC

WAVEFORMS+25 −40 to +85 −40 to +125

(V)

Fig.6

4.5

6.0 Fig.7

4.5

6.0 Fig.8

4.5

6.0 Fig.9

4.5

6.0 Fig.9

4.5

6.0 Figs 6, 8

4.5

6.0 Fig.7

4.5

6.0 Fig.7

4.5

6.0 Fig.7

4.5

6.0 Fig.7

4.5

6.0

September 1993 6

Philips Semiconductors Product speciﬁcation

Octal bus transceiver/register; 3-state 74HC/HCT652

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

. Output capability: bus driver ICC category: MSI.

Note to the HCT types

The value of additional quiescent supply current (∆ICC) for unit a load of 1 is given in the family specifications. To determine ∆I

per input, multiply this value by the unit load coefficient shown in the table below

CC

INPUT UNIT LOAD COEFFICIENT

SAB, S

BA

A

to A7 and B0to B

0

, CP

CP

AB

BA

OE

AB

OE

BA

0.75

7

1.50

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t

INPUT PARAMETER

t

PHL/tPLH

t

PHL/tPLH

t

PHL/tPLH

t

PZH/tPZL

= 6 ns; CL= 50 pF.

r=tf

propagation delay An, Bn to Bn, A

n

propagation delay CPAB, CPBAto Bn, A

propagation delay SAB, SBAto Bn, A

n

3-state output enable

(°C)

T

amb

+25 −40 to +85 −40 to +125

UNIT

MIN. TYP. MAX. MIN. MAX. MIN. MAX.

− 16 27 − 34 − 41 ns 4.5 Fig.6

− 23 39 − 49 − 59 ns 4.5 Fig.7

n

− 27 46 − 55 − 66 ns 4.5 Fig.8

− 18 33 − 41 − 50 ns 4.5 Fig.9

TEST CONDITIONS V

CC

WAVEFORMS

(V)

time

t

PHZ/tPLZ

OEAB, OEBAto An, B 3-state output disable

n

− 16 35 − 44 − 53 ns 4.5 Fig.9

time

t

THL/tTLH

OEAB, OEBAto An, B output transition time − 512−15 − 18 ns 4.5 Fig.6, 8

n

t

W

clock pulse width

16 6 − 20 − 24 − ns 4.5 Fig.7

HIGH or LOW

t

su

t

h

f

max

CPABor CP set-up time

An, Bn to CPAB, CP hold time

An, Bn to CPAB, CP maximum clock pulse

BA

10 5 − 13 − 15 − ns 4.5 Fig.7

BA

5 −2 − 6 − 8 − ns 4.5 Fig.7

BA

30 83 − 24 − 20 − MHz 4.5 Fig.7

frequency

September 1993 7

Philips Semiconductors Product speciﬁcation

Octal bus transceiver/register; 3-state 74HC/HCT652

(1) HC: VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

M

Fig.6 Waveforms showing the input An, Bn to

output Bn, Anpropagation delay times and the output transition times.

(1) HC: VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

M

Fig.7 Waveforms showing the An, Bn to CPAB,

CPBAset-up and hold times, clock CPAB, CPBApulse width, maximum clock pulse frequency and the CPAB, CPBAto output Bn, Anpropagation delays.

(1) HC: VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

M

Fig.8 Waveforms showing the input SAB, SBAto

output Bn, Anpropagation delay times and the output transition times.

September 1993 8

(1) HC: VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

M

Fig.9 Waveforms showing the output enable

inputs (OEAB, OEBA) to outputs An, B enable and disable times and the input rise and fall times.

n

Philips Semiconductors Product speciﬁcation

Octal bus transceiver/register; 3-state 74HC/HCT652

APPLICATION INFORMATION

Fig.10 Application information.

September 1993 9

Philips Semiconductors Product speciﬁcation

Octal bus transceiver/register; 3-state 74HC/HCT652

PACKAGE OUTLINES

See

“74HC/HCT/HCU/HCMOS Logic Package Outlines”

.

September 1993 10