Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT648
Octal bus transceiver/register;
3-state; inverting
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
Page 2
December 1990 2
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
FEATURES
• Independent register for A and B buses
• Multiplexed real-time and stored data
• Output capability: bus driver
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT648 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT648 consist of bus transceiver circuits with
3-state inverting outputs, D-type flip-flops, and control
circuitry arranged for multiplexed transmission of data
directly from the internal registers. Data on the “A” or “B”
bus will be clocked into the registers as the appropriate
clock (CP
AB
and CPBA) goes to a HIGH logic level. Output
enable (OE) and direction (DIR) inputs are provided to
control the transceiver function. In the transceiver mode,
data present at the high-impedance port may be stored in
either the “A” or “B” register, or in both. The select source
inputs (SAB and SBA) can multiplex stored and real-time
(transparent mode) data. The direction (DIR) input
determines which bus will receive data when OE is active
(LOW). In the isolation mode (OE = HIGH), “A” data may
be stored in the “B” register and/or “B” data may be stored
in the “A” register.
When an output function is disabled, the input function is
still enabled and may be used to store and transmit data.
Only one of the two buses, A or B, may be driven at a time.
The “648” is functionally identical to the “646”, but has
inverting data paths.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; tr=tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PD in µW):
PD=CPD× V
CC
2
× fi+∑ (CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL/ tPLH
propagation delay An, Bn to Bn, A
n
CL= 15 pF; VCC=5 V
11 11 ns
f
max
maximum clock frequency 75 88 MHz
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per
channel
notes 1 and 2 30 31 pF
Page 3
December 1990 3
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1CP
AB
A to B clock input (LOW-to-HIGH, edge-triggered)
2S
AB
select A to B source input
3 DIR direction control input
4, 5, 6, 7, 8, 9, 10, 11
A0 to A
7
A data inputs/outputs
12 GND ground (0 V)
20, 19, 18, 17, 16, 15, 14, 13
B0 to B
7
B data inputs/outputs
21
OE output enable input (active LOW)
22 S
BA
select B to A source input
23 CP
BA
B to A clock input (LOW-to-HIGH, edge-triggered)
24 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
Page 4
December 1990 4
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
FUNCTION TABLE
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH level transition
2. The data output functions may be enabled or disabled by various signals at the
OE and DIR inputs. Data input
functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock
inputs.
INPUTS
(1)
DATA I/O
(2)
FUNCTION
OE DIR CP
AB
CP
BA
S
AB
S
BA
A0 TO A
7
B0 TO B
7
H
H
X
X
H or L↑H or L↑X
X
X
X
input input
isolation
store A and B data
L
L
L
L
X
X
X
H or LXX
L
H
output input
real-time
B data to A bus
stored B data to A bus
L
L
H
H
X
H or LXX
L
H
X
X
input output
real-time
A data to B bus
stored A data to B bus
Fig.4 Functional diagram.
Page 5
December 1990 5
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
Fig.5 Logic diagram.
Page 6
December 1990 6
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; tr=tf= 6 ns; CL= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
An, Bn to Bn, A
n
39
14
11
135
27
23
170
34
29
205
41
35
ns 2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
CPAB, CPBA to Bn, A
n
74
27
22
230
46
39
290
58
49
345
69
59
ns 2.0
4.5
6.0
Fig.7
t
PHL
/ t
PLH
propagation delay
SAB, SBA to Bn, A
n
55
20
16
190
38
32
240
48
41
285
57
48
ns 2.0
4.5
6.0
Fig.8
t
PZH
/ t
PZL
3-state output enable
time OE to An, B
n
52
19
15
175
35
30
220
44
37
265
53
45
ns 2.0
4.5
6.0
Fig.9
t
PHZ
/ t
PLZ
3-state output disable
time OE to An, B
n
61
22
18
175
35
30
220
44
37
265
53
45
ns 2.0
4.5
6.0
Fig.9
t
PZH
/ t
PZL
3-state output enable
time DIR to An, B
n
52
19
15
175
35
30
220
44
37
265
53
45
ns 2.0
4.5
6.0
Fig.10
t
PHZ
/ t
PLZ
3-state output disable
time DIR to An, B
n
55
20
16
175
35
30
220
44
37
265
53
45
ns 2.0
4.5
6.0
Fig.10
t
THL
/ t
TLH
output transition time 14
5
4
60
12
10
75
15
13
90
18
15
ns 2.0
4.5
6.0
Fig.6 and Fig.8
t
W
clock pulse width
HIGH or LOW
CPAB or CP
BA
80
16
14
25
9
7
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.7
t
su
set-up time
An, Bn to CPAB, CP
BA
60
12
10
0
0
0
75
15
13
90
18
15
ns
2.0
4.5
6.0
Fig.7
t
h
hold time
An, Bn to CPAB, CP
BA
35
7
6
6
2
2
45
9
8
55
11
9
ns
2.0
4.5
6.0
Fig.7
f
max
maximum clock pulse
frequency
6.0
30
35
22
68
81
4.8
24
28
4.0
20
24
MHz
2.0
4.5
6.0
Fig.7
Page 7
December 1990 7
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT
UNIT LOAD COEFFICIENT
S
AB
, S
BA
A0 to A7; and B0 to B7;
0.60
0.75
INPUT UNIT LOAD COEFFICIENT
CP
AB
; CPBA;
OE
DIR
1.50
1.50
1.25
Page 8
December 1990 8
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
An, Bn to Bn, A
n
14 27 34 41 ns 4.5 Fig.6
t
PHL
/ t
PLH
propagation delay
CPAB, CPBA to Bn, A
n
25 46 58 69 ns 4.5 Fig.7
t
PHL
/ t
PLH
propagation delay
SAB, SBA to Bn, A
n
20 38 48 57 ns 4.5 Fig.8
t
PZH
/ t
PZL
3-state output enable
time
OE to An, B
n
21 40 50 60 ns 4.5 Fig.9
t
PHZ
/ t
PLZ
3-state output disable
time
OE to An, B
n
20 35 44 53 ns 4.5 Fig.9
t
PZH
/ t
PZL
3-state output enable
time
DIR to An, B
n
20 40 50 60 ns 4.5 Fig.10
t
PHZ
/ t
PLZ
3-state output disable
time
DIR to An, B
n
21 35 44 53 ns 4.5 Fig.10
t
THL
/ t
TLH
output transition time 5 12 15 18 ns 4.5 Fig.6 and Fig.8
t
W
clock pulse width
HIGH or LOW
CPAB or CP
BA
16 7 20 24 ns 4.5 Fig.7
t
su
set-up time
An, Bn to CPAB, CP
BA
12 2 15 18 ns 4.5 Fig.7
t
h
hold time
An, Bn to CPAB, CP
BA
5 0 5 5 ns 4.5 Fig.7
f
max
maximum clock pulse
frequency
30 80 24 20 ns MHz Fig.7
Page 9
December 1990 9
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
AC WAVEFORMS
Fig.6 Waveforms showing the input An, Bn to output Bn, An propagation delays and the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Fig.7 Waveforms showing the An, Bn to CPAB, CPBA set-up and hold times, clock CPAB, CPBA pulse width,
maximum clock pulse frequency and the CPAB, CPBA to output Bn, An propagation delays.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Fig.8 Waveforms showing the input SAB, SBA to output Bn, An propagation delays and output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Page 10
December 1990 10
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
Fig.9 Waveforms showing the input OE to output An, Bn 3-state enable and disable times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Fig.10 Waveforms showing the input DIR to output An, Bn 3-state enable and disable times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Page 11
December 1990 11
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
APPLICATION INFORMATION
Fig.11 Data storage from A and/or B bus.
Fig.12 Real-time transfer from bus A to bus B.
Fig.13 Real-time transfer from bus B to bus A.
Page 12
December 1990 12
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state;
inverting
74HC/HCT648
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
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