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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT646
Octal bus transceiver/register;
3-state
Product specification
File under Integrated Circuits, IC06
September 1993
Page 2
Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT646
FEATURES
• Independent register for A and B buses
• Multiplexed real-time and stored data
• Output capability: bus driver
• ICC category: MSI
clocked into the registers as the appropriate clock
and CPBA) goes to a HIGH logic level. Output
(CP
AB
enable (OE) and direction (DIR) inputs are provided to
control the transceiver function. In the transceiver mode,
data present at the high-impedance port may be stored in
either the “A” or “B” register, or in both. The select source
inputs (SABand SBA) can multiplex stored and real-time
(transparent mode) data. The direction (DIR) input
GENERAL DESCRIPTION
The 74HC/HCT646 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT646 consist of bus transceiver circuits with
3-state outputs, D-type flip-flops, and control circuitry
arranged for multiplexed transmission of data directly from
the internal registers. Data on the “A” or “B” bus will be
determines which bus will receive data when OE is active
(LOW). In the isolation mode (OE = HIGH), “A” data may
be stored in the “B” register and/or “B” data may be stored
in the “A” register.
When an output function is disabled, the input function is
still enabled and may be used to store and transmit data.
Only one of the two buses, A or B, may be driven at a time.
The “646” is functionally identical to the “648”, but has
non-inverting data paths.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL
f
max
C
C
I
PD
/ t
PLH
propagation delay An, Bn to Bn, A
n
CL= 15 pF; VCC=5V 11 13 ns
maximum clock frequency 69 85 MHz
input capacitance 3.5 3.5 pF
power dissipation capacitance per channel notes 1 and 2 30 33 pF
TYPICAL
UNIT
HC HCT
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
“74HC/HCT/HCU/HCMOS Logic Package Information”
See
September 1993 2
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Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT646
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
1CP
2S
AB
AB
3 DIR direction control input
4, 5, 6, 7, 8, 9, 10, 11 A
to A
0
7
12 GND ground (0 V)
20, 19, 18, 17, 16, 15, 14, 13 B
21
22 S
23 CP
24 V
to B
0
7
OE output enable input (active LOW)
BA
BA
CC
A to B clock input (LOW-to-HIGH, edge-triggered)
select A to B source input
A data inputs/outputs
B data inputs/outputs
select B to A source input
B to A clock input (LOW-to-HIGH, edge-triggered)
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
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Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT646
Fig.4 Functional diagram.
FUNCTION TABLE
INPUTS
(1)
DATA I/O
(2)
FUNCTION
OE DIR CP
H
H
L
L
L
L
X
X
L
L
H
H
H or L↑H or L↑X
X
X
X
H or LXX
AB
CP
BA
X
H or LXX
S
AB
X
L
H
S
BA
X
X
L
H
X
X
A0to A
B0to B
7
input input
output input
input output
7
isolation
store A and B data
real-time B data to A bus
stored B data to A bus
real-time A data to B bus
stored A data to B bus
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH level transition
2. The data output functions may be enabled or disabled by various signals at the
OE and DIR inputs. Data input
functions are always enabled, i.e., data at the bus inputs will be stored on every LOW-to-HIGH transition on the clock
inputs.
September 1993 4
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Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT646
Fig.5 Logic diagram.
September 1993 5
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Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT646
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= 6 ns; CL=50pF
r=tf
SYMBOL PARAMETER
t
PHL
t
PHL
t
PHL
t
PZH
/ t
/ t
/ t
/ t
propagation delay
PLH
An,Bn to Bn,A
propagation delay
PLH
CPAB,CPBA to Bn,A
propagation delay
PLH
SAB,SBA to Bn,A
3-state output enable
PZL
n
n
n
time
t
PHZ
t
PZH
t
PHZ
t
THL
t
W
OE to An,B
/ t
3-state output disable
PLZ
time OE to An,B
/ t
3-state output enable
PZL
time DIR to An,B
/ t
3-state output disable
PLZ
time DIR to An,B
/ t
output transition time 14
TLH
clock pulse width
n
n
n
n
HIGH or LOW
t
su
t
h
f
max
CPAB or CP
set-up time
An,Bnto CPAB,CP
hold time
An,Bnto CPAB,CP
maximum clock pulse
frequency
BA
BA
BA
(°C)
T
amb
74HC
min. typ. max. min. max. min. max.
39
80
16
14
60
12
10
35
7
6
6.0
30
35
14
11
66
24
19
55
20
16
47
17
14
58
21
17
50
18
14
50
18
14
5
4
25
9
7
−3
−1
−1
6
2
2
21
63
75
135
27
23
220
44
37
190
38
32
175
35
30
175
35
30
175
35
30
175
35
30
60
12
10
100
24
20
75
15
13
45
9
8
4.8
24
28
170
34
29
275
55
47
240
48
41
220
44
37
220
44
37
220
44
37
220
44
37
75
15
13
205
41
35
330
66
56
285
57
48
265
53
45
265
53
45
265
53
45
265
53
45
90
18
15
120
24
20
90
18
15
55
11
9
4.0
20
24
.
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns
ns
MHz
TEST CONDITIONS
V
CC
WAVEFORMS+25 −40 to +85 −40 to +125
(V)
Fig.6
4.5
6.0
Fig.7
4.5
6.0
Fig.8
4.5
6.0
Fig.9
4.5
6.0
Fig.9
4.5
6.0
Fig.10
4.5
6.0
Fig.10
4.5
6.0
Fig.6 and Fig.8
4.5
6.0
Fig.7
4.5
6.0
2.0
4.5
Fig.7
6.0
2.0
4.5
Fig.7
6.0
2.0
4.5
Fig.7
6.0
September 1993 6
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Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT646
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
) for a unit load of 1 is given in the family specifications.
CC
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
SAB, S
BA
A
to A7and B0 to B
0
0.60
0.75
7
INPUT UNIT LOAD COEFFICIENT
CPAB,CP
OE
DIR
BA
1.50
1.50
1.25
September 1993 7
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Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT646
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
= 6 ns; CL=50pF
r=tf
SYMBOL PARAMETER
t
PHL
t
PHL
/ t
/ t
propagation delay
PLH
An,Bn to Bn,A
propagation delay
PLH
n
CPAB,CPBA to Bn,A
t
PHL
t
PZH
t
PHZ
t
PZH
t
PHZ
t
THL
t
W
/ t
/ t
/ t
/ t
/ t
/ t
propagation delay
PLH
SAB,SBA to Bn,A
3-state output enable time
PZL
OE to An,B
3-state output disable time
PLZ
OE to An,B
3-state output enable time
PZL
DIR to An,B
3-state output disable time
PLZ
DIR to An,B
output transition time 5 12 15 18 ns 4.5 Fig.6 and Fig.8
TLH
n
n
n
n
n
clock pulse width
HIGH or LOW
CPAB or CP
t
su
set-up time
BA
An,Bnto CPAB,CP
t
h
hold time
An,Bnto CPAB,CP
f
max
maximum clock pulse
frequency
BA
BA
(°C)
T
amb
TEST CONDITIONS
74HCT
UNIT
V
CC
WAVEFORMS+25 −40 to +85 −40 to +125
(V)
min. typ. max. min. max. min. max.
16 30 38 45 ns 4.5 Fig.6
23 44 55 66 ns 4.5 Fig.7
n
26 46 58 69 ns 4.5 Fig.8
21 40 50 60 ns 4.5 Fig.9
20 35 44 53 ns 4.5 Fig.9
21 40 50 60 ns 4.5 Fig.10
21 35 44 53 ns 4.5 Fig.10
16 8 20 24 ns 4.5 Fig.7
12 3 15 18 ns 4.5 Fig.7
5 1 5 5 ns 4.5 Fig.7
30 77 24 20 MHz 4.5 Fig.7
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Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT646
AC WAVEFORMS
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.6 Waveforms showing the input An, Bn to output Bn, An propagation delays and the output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.7 Waveforms showing the An,Bn to CPAB, CPBA set-up and hold times, clock CPAB,CPBA pulse width,
maximum clock pulse frequency and the CPAB,CPBA to output Bn,An propagation delays.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.8 Waveforms showing the input SAB,SBA to output Bn,An propagation delays and output transition times.
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Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT646
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.9 Waveforms showing the input OE to output An,Bn 3-state enable and disable times.
(1) HC : VM= 50%; VI= GND to VCC.
= 1.3 V; VI= GND to 3 V.
HCT: V
M
Fig.10 Waveforms showing the input DIR to output An, Bn 3-state enable and disable times.
September 1993 10
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Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT646
APPLICATION INFORMATION
Fig.11 Data storage from A and/or B bus.
Fig.12 Real-time transfer from bus A to bus B.
Fig.13 Real-time transfer from bus B to bus A.
September 1993 11
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Philips Semiconductors Product specification
Octal bus transceiver/register; 3-state 74HC/HCT646
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
September 1993 12
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