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INTEGRATED CIRCUITS
DATA SH EET
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
74HC/HCT597
8-bit shift register with input
flip-flops
Product specification
File under Integrated Circuits, IC06
December 1990
Page 2
Philips Semiconductors Product specification
8-bit shift register with input flip-flops 74HC/HCT597
FEATURES
• 8-bit parallel storage register inputs
• Shift register has direct overriding load and clear
• Output capability: standard
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT597 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT597 consist each of an 8-bit storage
register feeding a parallel-in, serial-out 8-bit shift register.
Both the storage register and the shift register have
positive edge-triggered clocks. The shift register also has
direct load (from storage) and clear inputs.
QUICK REFERENCE DATA
GND = 0 V; T
=25°C; tr=tf= 6 ns
amb
SYMBOL PARAMETER CONDITIONS
t
PHL
/ t
PLH
propagation delay CL= 15 pF; VCC=5V
SH
to Q 17 20 ns
CP
ST
to Q 25 29 ns
CP
PL to Q 21 26 ns
f
max
C
C
I
PD
maximum clock frequency SH
CP
input capacitance 3.5 3.5 pF
power dissipation capacitance per package notes 1 and 2 29 32 pF
TYPICAL
UNIT
HC HCT
96 83 MHz
Notes
1. C
is used to determine the dynamic power dissipation (PD in µW):
PD
PD=CPD× V
2
× fi+ ∑ (CL× V
CC
2
× fo) where:
CC
fi= input frequency in MHz
fo= output frequency in MHz
∑ (CL× V
2
× fo) = sum of outputs
CC
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to V
CC
For HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
December 1990 2
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Philips Semiconductors Product specification
8-bit shift register with input flip-flops 74HC/HCT597
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
8 GND ground (0 V)
9 Q serial data output
10
11 SH
12 ST
13
14 D
15, 1, 2, 3, 4, 5, 6, 7 D
16 V
MR asynchronous reset input (active LOW)
CP
CP
shift clock input (LOW-to-HIGH, edge-triggered)
storage clock input (LOW-to-HIGH, edge-triggered)
PL parallel load input (active LOW)
S
to D
0
CC
7
serial data input
parallel data inputs
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
December 1990 3
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Philips Semiconductors Product specification
8-bit shift register with input flip-flops 74HC/HCT597
Fig.4 Functional diagram.
FUNCTION TABLE
ST
CP
SH
PL MR FUNCTION
CP
↑ X X X data loaded to input latches
↑ X L H data loaded from inputs to shift register
no clock edge X L H data transferred from input flip-flops to shift register
X X L L invalid logic, state of shift register indeterminate when signals removed
X X H L shift register cleared
X ↑ H H shift register clocked Q
n=Qn−1
, Q0=D
S
Notes
1. H = HIGH voltage level
L = LOW voltage level
X = don’t care
↑ = LOW-to-HIGH CP transition
December 1990 4
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Philips Semiconductors Product specification
8-bit shift register with input flip-flops 74HC/HCT597
Fig.5 Logic diagram.
December 1990 5
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Philips Semiconductors Product specification
8-bit shift register with input flip-flops 74HC/HCT597
Fig.6 Timing diagram.
December 1990 6
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Philips Semiconductors Product specification
8-bit shift register with input flip-flops 74HC/HCT597
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
Output capability: standard
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
= 6 ns; CL=50pF
r=tf
SYMBOL PARAMETER
t
PHL
/ t
propagation delay
PLH
SHCP to Q
t
PHL
propagation delay
MR to Q
t
PHL
/ t
propagation delay
PLH
STCP to Q
t
PHL
/ t
propagation delay
PLH
PL to Q
t
THL
t
W
/ t
output transition time 19
TLH
STCPpulse width
HIGH or LOW
t
W
SHCPpulse width
HIGH or LOW
t
W
MR pulse width
LOW
t
W
PL pulse width
LOW
t
t
rem
su
removal time
MR to SH
set-up time
Dnto ST
CP
CP
(°C)
T
amb
74HC
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
55
80
16
14
80
16
14
80
16
14
80
16
14
60
12
10
60
12
10
20
16
58
21
17
80
29
23
69
25
20
7
6
11
4
3
14
5
4
22
8
6
22
8
6
−3
−1
−1
8
3
2
175
35
30
175
35
30
250
50
43
215
43
37
75
15
13
100
20
17
100
20
17
100
20
17
100
20
17
75
15
13
75
15
13
220
44
37
220
44
37
315
63
54
270
54
46
95
19
16
265
53
45
265
53
45
375
75
64
325
65
55
110
22
19
120
24
20
120
24
20
120
24
20
120
24
20
90
18
15
90
18
15
.
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
ns 2.0
TEST CONDITIONS
WAVEFORMS
V
CC
(V)
Fig.7
4.5
6.0
Fig.8
4.5
6.0
Fig.7
4.5
6.0
Fig.9
4.5
6.0
Fig.9
4.5
6.0
Fig.7
4.5
6.0
Fig.7
4.5
6.0
Fig.8
4.5
6.0
Fig.9
4.5
6.0
Fig.10
4.5
6.0
Fig.11
4.5
6.0
December 1990 7
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Philips Semiconductors Product specification
8-bit shift register with input flip-flops 74HC/HCT597
T
SYMBOL PARAMETER
t
su
t
su
t
h
t
h
f
max
set-up time
DSto SH
CP
set-up time
PL to SH
CP
hold time
Dnto ST
CP
hold time
PL, DS to SH
CP
maximum pulse frequency
SH
CP
(°C)
amb
74HC
+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
60
12
10
60
12
10
5
5
5
5
5
5
6.0
30
35
11
4
3
11
4
3
−3
−1
−1
−6
−2
−2
29
87
104
75
15
13
75
15
13
5
5
5
5
5
5
4.8
24
28
90
18
15
90
18
15
5
5
5
5
5
5
4.0
20
24
UNIT
ns 2.0
ns 2.0
ns 2.0
ns 2.0
MHz 2.0
TEST CONDITIONS
WAVEFORMS
V
CC
(V)
Fig.11
4.5
6.0
Fig.12
4.5
6.0
Fig.11
4.5
6.0
Fig.11
4.5
6.0
Fig.7
4.5
6.0
December 1990 8
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Philips Semiconductors Product specification
8-bit shift register with input flip-flops 74HC/HCT597
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: standard
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
) for a unit load of 1 is given in the family specifications.
CC
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
INPUT UNIT LOAD COEFFICIENT
D
S
D
n
PL, MR
STCP, SH
CP
0.25
0.30
1.50
1.50
December 1990 9
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Philips Semiconductors Product specification
8-bit shift register with input flip-flops 74HC/HCT597
AC WAVEFORMS FOR 74HCT
GND = 0 V; t
= 6 ns; CL=50pF
r=tf
SYMBOL PARAMETER
t
PHL
/ t
propagation delay
PLH
SHCP to Q
t
PHL
propagation delay
MR to Q
t
PHL
/ t
propagation delay
PLH
STCP to Q
t
PHL
/ t
propagation delay
PLH
PL to Q
t
THL
t
W
/ t
output transition time 7 15 19 22 ns 4.5 Fig.9
TLH
SHCPpulse width
HIGH or LOW
t
W
STCPpulse width
HIGH or LOW
t
W
MR pulse width
LOW
t
W
PL pulse width
LOW
t
rem
t
su
t
su
t
su
t
h
t
h
f
max
removal time
MR to SH
CP
set-up time
Dnto ST
CP
set-up time
DSto SH
CP
set-up time
PL to SH
CP
hold time
Dnto ST
CP
hold time
PL, DS to SH
CP
maximum pulse frequency
SH
CP
T
amb
(°C)
TEST CONDITIONS
74HCT
UNIT
V
CC
WAVEFORMS+25 −40 to +85 −40 to +125
(V)
min. typ. max. min. max. min. max.
23 40 50 60 ns 4.5 Fig.7
28 49 61 74 ns 4.5 Fig.8
33 57 71 86 ns 4.5 Fig.7
30 52 65 78 ns 4.5 Fig.9
16 7 20 24 ns 4.5 Fig.7
16 6 20 24 ns 4.5 Fig.7
25 14 31 38 ns 4.5 Fig.8
20 10 25 30 ns 4.5 Fig.9
12 −2 15 18 ns 4.5 Fig.10
12 5 15 18 ns 4.5 Fig.11
12 2 15 18 ns 4.5 Fig.11
12 4 15 18 ns 4.5 Fig.12
5 −1 5 5 ns 4.5 Fig.11
5 −2 5 5 ns 4.5 Fig.11
30 75 24 20 MHz 4.5 Fig.7
December 1990 10
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Philips Semiconductors Product specification
8-bit shift register with input flip-flops 74HC/HCT597
AC WAVEFORMS
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
= 1.3 V; VI= GND to 3 V.
M
Fig.7 Waveforms showing the SHCP and ST
inputs to Q output propagation delays, the
SHCP and STCP pulse widths and maximum
clock pulse frequency.
CP
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
= 1.3 V; VI= GND to 3 V.
M
Fig.8 Waveforms showing the MR input to Q
output propagation delays and the MR
pulse width.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
= 1.3 V; VI= GND to 3 V.
M
Fig.9 Waveforms showing the PL input to Q
output propagation delays, PL pulse width
and output transition times.
December 1990 11
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
= 1.3 V; VI= GND to 3 V.
M
Fig.10 Waveforms showing the MR input to SHCP,
STCP removal times.
Page 12
Philips Semiconductors Product specification
8-bit shift register with input flip-flops 74HC/HCT597
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
= 1.3 V; VI= GND to 3 V.
M
Fig.11 Waveforms showing hold and set-up times
for DS, Dn inputs to SHCP, STCP inputs.
(1) HC : VM= 50%; VI= GND to VCC.
HCT : V
= 1.3 V; VI= GND to 3 V.
M
Fig.12 Waveforms showing set-up times for PL
input to SHCP input.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
December 1990 12
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