Page 1
DATA SH EET
Product specification
Supersedes data of September 1993
File under Integrated Circuits, IC06
1998 Jun 04
INTEGRATED CIRCUITS
74HC/HCT595
8-bit serial-in/serial or parallel-out
shift register with output latches;
3-state
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
Page 2
1998 Jun 04 2
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
FEATURES
• 8-bit serial input
• 8-bit serial or parallel output
• Storage register with 3-state outputs
• Shift register with direct clear
• 100 MHz (typ) shift out frequency
• Output capability:
– parallel outputs; bus driver
– serial output; standard
• ICC category: MSI.
APPLICATIONS
• Serial-to-parallel data conversion
• Remote control holding register.
DESCRIPTION
The 74HC/HCT595 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The “595” is an 8-stage serial shift register with a storage
register and 3-state outputs. The shift register and storage
register have separate clocks.
Data is shifted on the positive-going transitions of the
SHCP input. The data in each register is transferred to the
storage register on a positive-going transition of the ST
CP
input. If both clocks are connected together, the shift
register will always be one clock pulse ahead of the
storage register.
The shift register has a serial input (DS) and a serial
standard output (Q7’) for cascading. It is also provided with
asynchronous reset (active LOW) for all 8 shift register
stages. The storage register has 8 parallel 3-state bus
driver outputs. Data in the storage register appears at the
output whenever the output enable input (OE) is LOW.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; tr=tf= 6 ns.
Notes
1. C
PD
is used to determine the dynamic power dissipation (PD in µW):
PD=CPD× V
CC
2
× fi+∑ (CL× V
CC
2
× fo) where:
fi= input frequency in MHz
fo= output frequency in MHz
∑(CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF
VCC= supply voltage in V
2. For HC the condition is VI= GND to VCC; for HCT the condition is VI= GND to VCC− 1.5 V.
SYMBOL PARAMETER CONDITIONS
TYP.
UNIT
HC HCT
t
PHL/tPLH
propagation delay CL= 15 pF; VCC=5V
SH
CP
to Q7’ 1621ns
ST
CP
to Q
n
17 20 ns
MR to Q7’ 1419ns
f
max
maximum clock frequency SHCP, ST
CP
100 57 MHz
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per package notes 1 and 2 115 130 pF
Page 3
1998 Jun 04 3
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
ORDERING INFORMATION
PINNING
TYPE NUMBER
PACKAGE
NAME DESCRIPTION VERSION
74HC595N DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1
74HC595D SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
74HC595DB SSOP16 plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
74HC595PW TSSOP16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm SOT403-1
74HCT595N DIP16 plastic dual in-line package; 16 leads (300 mil); long body SOT38-1
74HCT595D SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
SYMBOL PIN DESCRIPTION
Q
0
to Q
7
15, 1 to 7 parallel data output
GND 8 ground (0 V)
Q
7
’ 9 serial data output
MR 10 master reset (active LOW)
SH
CP
11 shift register clock input
ST
CP
12 storage register clock input
OE 13 output enable (active LOW)
D
S
14 serial data input
V
CC
16 positive supply voltage
Fig.1 Pin configuration.
handbook, halfpage
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Q7'
Q
0
D
S
GND
ST
CP
SH
CP
V
CC
OE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
595
MLA001
MR
Fig.2 Logic symbol.
handbook, halfpage
OEMR
9
15
1
2
3
4
5
6
7
1310
14
11 12
MLA002
Q
1
Q
0
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Q7'
D
S
ST
CP
SH
CP
Page 4
1998 Jun 04 4
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
Fig.3 IEC logic symbol.
handbook, halfpage
MSA698
15
9
1
2
3
4
5
6
7
1D 2D
C1/
10
11
14
C2
12
13
EN3
SRG8
R
3
OE
MR
Q
1
Q
0
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Q7'
D
S
ST
CP
SH
CP
Fig.4 Functional diagram.
handbook, full pagewidth
ST
CP
D
S
SH
CP
MR
Q7'
8-STAGE SHIFT REGISTER
8-BIT STORAGE REGISTER
14
11
10
12
9
OE
3-STATE OUTPUTS
Q
1
Q
2
Q
3
Q
5
Q
6
Q
7
Q
4
Q
0
15
1
2
3
4
5
6
7
13
MLA003
Page 5
1998 Jun 04 5
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
Fig.5 Logic diagram.
handbook, full pagewidth
STAGE 0 STAGES 1 TO 6 STAGE 7
FF0
DCPQ
R
LATCH
DCPQ
FF7
DCPQ
R
LATCH
DCPQ
MLA010
DQ
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Q
7
'
Q
0
D
S
ST
CP
SH
CP
OE
MR
Page 6
1998 Jun 04 6
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
FUNCTION TABLE
Notes
1. H = HIGH voltage level; L = LOW voltage level
↑ = LOW-to-HIGH transition; ↓ = HIGH-to-LOW transition
Z = high-impedance OFF-state; NC = no change
X = don’t care.
INPUTS OUTPUTS
FUNCTON
SH
CP
ST
CP
OE MR D
S
Q7’Q
N
X X L L X L NC a LOW level on MR only affects the shift registers
X ↑ L L X L L empty shift register loaded into storage register
X X H L X L Z shift register clear. Parallel outputs in high-impedance
OFF-state
↑ XLHHQ
6
’ NC logic high level shifted into shift register stage 0. Contents
of all shift register stages shifted through, e.g. previous
state of stage 6 (internal Q
6
’) appears on the serial output
(Q7’)
X ↑ LHXNCQ
n
’ contents of shift register stages (internal Qn’) are
transferred to the storage register and parallel output
stages
↑↑LHXQ
6
’Qn’ contents of shift register shifted through. Previous
contents of the shift register is transferred to the storage
register and the parallel output stages.
Page 7
1998 Jun 04 7
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
Fig.6 Timing diagram.
handbook, full pagewidth
high-impedance OFF-state
ST
CP
D
S
SH
CP
MR
OE
Q
1
Q
0
Q7'
Q
6
Q
7
MLA005 - 1
Page 8
1998 Jun 04 8
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see chapter
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: parallel outputs, bus driver, serial output, standard ICC category: MSI.
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r=tf
= 6 ns; CL=50pF.
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITION
+25 −40 to +85 −40 to +125
V
CC
(V)
WAVEFORMS
min typ max min max min max
t
PHL/tPLH
propagation delay
SHCP to Q7’
− 52 160 − 200 − 240 ns 2.0 Fig.7
− 19 32 − 40 − 48 4.5
− 15 27 − 34 − 41 6.0
t
PHL/tPLH
propagation delay
STCP to Q
n
− 55 175 − 220 − 265 ns 2.0 Fig.8
− 20 35 − 44 − 53 4.5
− 16 30 − 37 − 45 6.0
t
PHL
propagation delay
MR to Q7’
− 47 175 − 220 − 265 ns 2.0 Fig.10
− 17 35 − 44 − 53 4.5
− 14 30 − 37 − 45 6.0
t
PZH/tPZL
3-state output
enable time
OE to Q
n
− 47 150 − 190 − 225 ns 2.0 Fig.11
− 17 30 − 38 − 45 4.5
− 14 26 − 33 − 38 6.0
t
PHZ/tPLZ
3-state output
disable time
OE to Q
n
− 41 150 − 190 − 225 ns 2.0 Fig.11
− 15 30 − 38 − 45 4.5
− 12 26 − 33 − 38 6.0
t
W
shift clock pulse
width HIGH or
LOW
75 17 − 95 − 110 − ns 2.0 Fig.7
15 6 − 19 − 22 − 4.5
13 5 − 16 − 19 − 6.0
t
W
storage clock
pulse width HIGH
or LOW
75 11 − 95 − 110 − ns 2.0 Fig.8
15 4 − 19 − 22 − 4.5
13 3 − 16 − 19 − 6.0
t
W
master reset
pulse width LOW
75 17 − 95 − 110 − ns 2.0 Fig.10
15 6.0 − 19 − 22 − 4.5
13 5.0 − 16 − 19 − 6.0
t
su
set-up time DS to
SH
CP
50 11 − 65 − 75 − ns 2.0 Fig.9
10 4.0 − 13 − 15 − 4.5
9.0 3.0 − 11 − 13 − 6.0
t
su
set-up time SH
CP
to ST
CP
75 22 − 95 − 110 − ns 2.0 Fig.8
15 8 − 19 − 22 − 4.5
13 7 − 16 − 19 − 6.0
Page 9
1998 Jun 04 9
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
t
h
hold time DS to
SH
CP
3 −6 − 3 − 3 − ns 2.0 Fig.9
3 −2 − 3 − 3 − 4.5
3 −2 − 3 − 3 − 6.0
t
rem
removal time MR
to SH
CP
50 −19 − 65 − 75 − ns 2.0 Fig.10
10 −7 − 13 − 15 − 4.5
9 −6 − 11 − 13 − 6.0
f
max
maximum clock
pulse frequency
SHCP or ST
CP
930− 4.8 − 4 − MHz 2.0 Figs 7 and 8
30 91 − 24 − 20 − 4.5
35 108 − 28 − 24 − 6.0
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITION
+25 −40 to +85 −40 to +125
V
CC
(V)
WAVEFORMS
min typ max min max min max
Page 10
1998 Jun 04 10
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see chapter
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: parallel outputs, bus driver; serial output, standard ICC category: MSI.
Note to HCT types
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
GND = 0 V; t
r=tf
= 6 ns; CL=50pF.
INPUT UNIT LOAD COEFFICIENT
D
S
0.25
MR 1.50
SH
CP
1.50
ST
CP
1.50
OE 1.50
Page 11
1998 Jun 04 11
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r=tf
= 6 ns; CL=50pF.
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITION
+25 −40 to +85 −40 to +125
V
CC
(V)
WAVEFORMS
min typ max min max min max
t
PHL
/ t
PLH
propagation delay
SHCP to Q7’
− 25 42 − 53 − 63 ns 4.5 Fig.7
t
PHL
/ t
PLH
propagation delay
STCP to Q
n
− 24 40 − 50 − 60 ns 4.5 Fig.8
t
PHL
propagation delay
MR to Q7’
− 23 40 − 50 − 60 ns 4.5 Fig.10
t
PZH
/ t
PZL
3-state output enable
time OE to Q
n
− 21 35 − 44 − 53 ns 4.5 Fig.11
t
PHZ
/ t
PLZ
3-state output disable
time OE to Q
n
− 18 30 − 38 − 45 ns 4.5 Fig.11
t
W
shift clock pulse
width HIGH or LOW
16 6 − 20 − 24 − ns 4.5 Fig.7
t
W
storage clock pulse width
HIGH or LOW
16 5 − 20 − 24 − ns 4.5 Fig.8
t
W
master reset
pulse width LOW
20 8 − 25 − 30 − ns 4.5 Fig.10
t
su
set-up time DS to
SH
SP
16 5 − 20 − 24 − ns 4.5 Fig.9
t
su
set-up time SH
CP
to ST
CP
16 8 − 20 − 24 − ns 4.5 Fig.8
t
h
hold time DS to SH
CP
3 −2 − 3 − 3 − ns 4.5 Fig.9
t
rem
removal time MR
to SH
CP
10 −7 − 13 − 15 − ns 4.5 Fig.10
f
max
maximum clock
pulse frequency
SHCP or ST
CP
30 52 − 24 − 20 − MHz 4.5 Figs 7 and 8
Page 12
1998 Jun 04 12
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
AC WAVEFORMS
Fig.7 Waveforms showing the clock (SHCP) to output (Q7’) propagation delays, the shift clock pulse width and
maximum shift clock frequency.
(1) HC: VM= 50%; VI= GND to V
CC
HCT: VM= 1.3 V; VI= GND to 3 V.
handbook, full pagewidth
MSA699
t
PLH
t
PHL
t
W
1/f
max
V
M
(1)
V
M
(1)
SH
CP
INPUT
Q7' OUTPUT
t
THL
t
TLH
90%
10%
Fig.8 Waveforms showing the storage clock (STCP) to output (Qn) propagation delays, the storage clock pulse
width and the shift clock to storage clock set-up time.
(1) HC: VM= 50%; VI= GND to V
CC
HCT: VM= 1.3 V; VI= GND to 3 V.
handbook, full pagewidth
MSA700
t
PLH
t
PHL
t
W
1/f
max
V
M
(1)
V
M
(1)
V
M
(1)
ST
CP
INPUT
t
su
SH
CP
INPUT
Qn OUTPUT
Page 13
1998 Jun 04 13
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
Fig.9 Waveforms showing the data set-up and hold times for the DS input.
(1) HC: VM= 50%; VI= GND to V
CC
HCT: VM= 1.3 V; VI= GND to 3 V.
handbook, full pagewidth
MLB196
t
h
t
su
t
h
t
su
Q7' OUTPUT
SHCP INPUT
DS INPUT
V
M
(1)
V
M
(1)
V
M
(1)
Fig.10 Waveforms showing the master reset (MR) pulse width, the master reset to output (Q7’) propagation delay
and the master reset to shift clock (SHCP) removal time.
(1) HC: VM= 50%; VI= GND to V
CC
HCT: VM= 1.3 V; VI= GND to 3 V.
handbook, full pagewidth
MLB197
t
PHL
t
W
V
M
(1)
V
M
(1)
V
M
(1)
SH
CP
INPUT
t
rem
MR INPUT
Q7' OUTPUT
Page 14
1998 Jun 04 14
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
Fig.11 Waveforms showing the 3-state enable and disable times for input OE.
(1) HC: VM= 50%; VI= GND to V
CC
HCT: VM= 1.3 V; VI= GND to 3 V.
handbook, full pagewidth
MSA697
t
PLZ
t
PHZ
outputs
disabled
outputs
enabled
90%
10%
outputs
enabled
OE INPUT
V
M
(1)
t
PZL
t
PZH
V
M
(1)
V
M
(1)
Qn OUTPUT
LOW-to-OFF
OFF-to-LOW
Qn OUTPUT
HIGH-to-OFF
OFF-to-HIGH
t
r
t
f
90%
10%
Page 15
1998 Jun 04 15
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
PACKAGE OUTLINES
UNIT
A
max.
1 2
b
1
cEe M
H
L
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC EIAJ
mm
inches
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
SOT38-1
92-10-02
95-01-19
A
min.
A
max.
b
max.
w
M
E
e
1
1.40
1.14
0.055
0.045
0.53
0.38
0.32
0.23
21.8
21.4
0.86
0.84
6.48
6.20
0.26
0.24
3.9
3.4
0.15
0.13
0.2542.54 7.62
0.30
8.25
7.80
0.32
0.31
9.5
8.3
0.37
0.33
2.2
0.087
4.7 0.51 3.7
0.15
0.021
0.015
0.013
0.009
0.010.100.0200.19
050G09 MO-001AE
M
H
c
(e )
1
M
E
A
L
seating plane
A
1
w M
b
1
e
D
A
2
Z
16
1
9
8
b
E
pin 1 index
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
(1) (1)
D
(1)
Z
DIP16: plastic dual in-line package; 16 leads (300 mil); long body
SOT38-1
Page 16
1998 Jun 04 16
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
X
w M
θ
A
A
1
A
2
b
p
D
H
E
L
p
Q
detail X
E
Z
e
c
L
v M
A
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT
A
max.
A
1
A2A
3
b
p
cD
(1)E(1) (1)
eHELLpQZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC EIAJ
mm
inches
1.75
0.25
0.10
1.45
1.25
0.25
0.49
0.36
0.25
0.19
10.0
9.8
4.0
3.8
1.27
6.2
5.8
0.7
0.6
0.7
0.3
8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
1.0
0.4
SOT109-1
95-01-23
97-05-22
076E07S MS-012AC
0.069
0.010
0.004
0.057
0.049
0.01
0.019
0.014
0.0100
0.0075
0.39
0.38
0.16
0.15
0.050
1.05
0.041
0.244
0.228
0.028
0.020
0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm
SOT109-1
Page 17
1998 Jun 04 17
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
UNIT A
1
A2A3b
p
cD
(1)E(1)
eHELLpQZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC EIAJ
mm
0.21
0.05
1.80
1.65
0.25
0.38
0.25
0.20
0.09
6.4
6.0
5.4
5.2
0.65 1.25
7.9
7.6
1.03
0.63
0.9
0.7
1.00
0.55
8
0
o
o
0.130.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT338-1
94-01-14
95-02-04
(1)
w M
b
p
D
H
E
E
Z
e
c
v M
A
X
A
y
1
8
16
9
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
MO-150AC
pin 1 index
0 2.5 5 mm
scale
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm
SOT338-1
A
max.
2.0
Page 18
1998 Jun 04 18
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
UNIT A1A2A3b
p
cD
(1)E(2) (1)
eHELLpQZywv θ
REFERENCES
OUTLINE
VERSION
EUROPEAN
PROJECTION
ISSUE DATE
IEC JEDEC EIAJ
mm
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
5.1
4.9
4.5
4.3
0.65
6.6
6.2
0.4
0.3
0.40
0.06
8
0
o
o
0.13 0.10.21.0
DIMENSIONS (mm are the original dimensions)
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
0.75
0.50
SOT403-1 MO-153
94-07-12
95-04-04
w M
b
p
D
Z
e
0.25
18
16
9
θ
A
A
1
A
2
L
p
Q
detail X
L
(A )
3
H
E
E
c
v M
A
X
A
y
0 2.5 5 mm
scale
TSSOP16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm
SOT403-1
A
max.
1.10
pin 1 index
Page 19
1998 Jun 04 19
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
SOLDERING
Introduction
There is no soldering method that is ideal for all IC
packages. Wave soldering is often preferred when
through-hole and surface mounted components are mixed
on one printed-circuit board. However, wave soldering is
not always suitable for surface mounted ICs, or for
printed-circuits with high population densities. In these
situations reflow soldering is often used.
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our
“Data Handbook IC26; Integrated Circuit Packages”
(order code 9398 652 90011).
DIP
S
OLDERING BY DIPPING OR BY WAVE
The maximum permissible temperature of the solder is
260 °C; solder at this temperature must not be in contact
with the joint for more than 5 seconds. The total contact
time of successive solder waves must not exceed
5 seconds.
The device may be mounted up to the seating plane, but
the temperature of the plastic body must not exceed the
specified maximum storage temperature (T
stg max
). If the
printed-circuit board has been pre-heated, forced cooling
may be necessary immediately after soldering to keep the
temperature within the permissible limit.
R
EPAIRING SOLDERED JOINTS
Apply a low voltage soldering iron (less than 24 V) to the
lead(s) of the package, below the seating plane or not
more than 2 mm above it. If the temperature of the
soldering iron bit is less than 300 °C it may remain in
contact for up to 10 seconds. If the bit temperature is
between 300 and 400 °C, contact may be up to 5 seconds.
SO, SSOP and TSSOP
R
EFLOW SOLDERING
Reflow soldering techniques are suitable for all SO, SSOP
and TSSOP packages.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
Several techniques exist for reflowing; for example,
thermal conduction by heated belt. Dwell times vary
between 50 and 300 seconds depending on heating
method.
Typical reflow temperatures range from 215 to 250 °C.
Preheating is necessary to dry the paste and evaporate
the binding agent. Preheating duration: 45 minutes at
45 °C.
W
AVE SOLDERING
Wave soldering can be used for all SO packages. Wave
soldering is not recommended for SSOP and TSSOP
packages, because of the likelihood of solder bridging due
to closely-spaced leads and the possibility of incomplete
solder penetration in multi-lead devices.
If wave soldering is used - and cannot be avoided for
SSOP and TSSOP packages - the following conditions
must be observed:
• A double-wave (a turbulent wave with high upward
pressure followed by a smooth laminar wave) soldering
technique should be used.
• The longitudinal axis of the package footprint must be
parallel to the solder flow and must incorporate solder
thieves at the downstream end.
Page 20
1998 Jun 04 20
Philips Semiconductors Product specification
8-bit serial-in/serial or parallel-out shift
register with output latches; 3-state
74HC/HCT595
Even with these conditions:
• Only consider wave soldering SSOP packages that
have a body width of 4.4 mm, that is
SSOP16 (SOT369-1) or SSOP20 (SOT266-1).
• Do not consider wave soldering TSSOP packages
with 48 leads or more, that is TSSOP48 (SOT362-1)
and TSSOP56 (SOT364-1).
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Maximum permissible solder temperature is 260 °C, and
maximum duration of package immersion in solder is
10 seconds, if cooled to less than 150 °C within
6 seconds. Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
R
EPAIRING SOLDERED JOINTS
Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron
(less than 24 V) applied to the flat part of the lead. Contact
time must be limited to 10 seconds at up to 300 °C. When
using a dedicated tool, all other leads can be soldered in
one operation within 2 to 5 seconds between
270 and 320 °C.
DEFINITIONS
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
Data sheet status
Objective specification This data sheet contains target or goal specifications for product development.
Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
Product specification This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
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