Page 1
DATA SH EET
Product specification
File under Integrated Circuits, IC06
December 1990
INTEGRATED CIRCUITS
74HC/HCT573
Octal D-type transparent latch;
3-state
For a complete data sheet, please also download:
•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information
•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines
Page 2
December 1990 2
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74HC/HCT573
FEATURES
• Inputs and outputs on opposite
sides of package allowing easy
interface with microprocessors
• Useful as input or output port for
microprocessors/microcomputers
• 3-state non-inverting outputs for
bus oriented applications
• Common 3-state output enable
input
• Functionally identical to the “563”
and “373”
• Output capability: bus driver
• ICC category: MSI
GENERAL DESCRIPTION
The 74HC/HCT573 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard no.
7A.
The 74HC/HCT573 are octal D-type
transparent latches featuring
separate D-type inputs for each latch
and 3-state outputs for bus oriented
applications.
A latch enable (LE) input and an
output enable (OE) input are common
to all latches.
The “573” consists of eight D-type
transparent latches with 3-state true
outputs. When LE is HIGH, data at
the D
n
inputs enter the latches. In this
condition the latches are transparent,
i.e. a latch output will change state
each time its corresponding D-input
changes.
When LE is LOW the latches store the
information that was present at the
D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the
8 latches are available at the outputs.
When OE is HIGH, the outputs go to
the high impedance OFF-state.
Operation of the OE input does not
affect the state of the latches.
The “573” is functionally identical to
the “563” and “373”, but the “563” has
inverted outputs and the “373” has a
different pin arrangement.
QUICK REFERENCE DATA
GND = 0 V; T
amb
=25°C; tr=tf= 6 ns
Notes
1. C
PD
is used to determine the dynamic power dissipation (PD in µW):
PD=CPD× V
CC
2
× fi+∑ (CL× V
CC
2
× fo) where:
fi= input frequency in MHz; fo= output frequency in MHz
∑ (CL× V
CC
2
× fo) = sum of outputs
CL= output load capacitance in pF; VCC= supply voltage in V
2. For HC the condition is VI= GND to VCC; for HCT the condition is VI= GND to VCC− 1.5 V
ORDERING INFORMATION
See
“74HC/HCT/HCU/HCMOS Logic Package Information”
.
SYMBOL PARAMETER CONDITIONS
TYPICAL
UNIT
HC HCT
t
PHL/ tPLH
propagation delay CL= 15 pF; VCC=5 V
D
n
to Q
n
14 17 ns
LE to Q
n
15 15 ns
C
I
input capacitance 3.5 3.5 pF
C
PD
power dissipation capacitance per latch notes 1 and 2 26 26 pF
Page 3
December 1990 3
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74HC/HCT573
PIN DESCRIPTION
PIN NO. SYMBOL NAME AND FUNCTION
2, 3, 4, 5, 6, 7, 8, 9 D
0
to D
7
data inputs
11 LE latch enable input (active HIGH)
1
OE 3-state output enable input (active LOW)
10 GND ground (0 V)
19, 18, 17, 16, 15, 14, 13, 12 Q
0
to Q
7
3-state latch outputs
20 V
CC
positive supply voltage
Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.
Page 4
December 1990 4
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74HC/HCT573
Fig.4 Functional diagram.
FUNCTION TABLE
Notes
1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW
LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW
LE transition
Z = high impedance OFF-state
OPERATING
MODES
INPUTS
INTERNAL
LATCHES
OUTPUTS
OE LE D
N
Q0to Q
7
enable and read
register
(transparent mode)
LLH
H
L
H
L
H
L
H
latch and read
register
LLL
L
l
h
L
H
L
H
latch register and
disable outputs
HHL
L
l
h
L
H
Z
Z
Fig.5 Logic diagram.
Page 5
December 1990 5
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74HC/HCT573
DC CHARACTERISTICS FOR 74HC
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICC category: MSI
AC CHARACTERISTICS FOR 74HC
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HC
V
CC
(V)
WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
Dn to Q
n
47
17
14
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.6
t
PHL
/ t
PLH
propagation delay
LE to Q
n
50
18
14
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.7
t
PZH
/ t
PZL
3-state output enable
time OE to Q
n
44
16
13
140
28
24
175
35
30
210
42
36
ns 2.0
4.5
6.0
Fig.8
t
PHZ
/ t
PLZ
3-state output disable
time OE to Q
n
55
20
16
150
30
26
190
38
33
225
45
38
ns 2.0
4.5
6.0
Fig.8
t
THL
/ t
TLH
output transition time 14
5
4
60
12
10
75
15
13
90
18
15
ns 2.0
4.5
6.0
Fig.6
t
W
enable pulse width
HIGH
80
16
14
14
5
4
100
20
17
120
24
20
ns 2.0
4.5
6.0
Fig.7
t
su
set-up time
Dn to LE
50
10
9
11
4
3
65
13
11
75
15
13
ns 2.0
4.5
6.0
Fig.9
t
h
hold time
Dn to LE
5
5
5
3
1
1
5
5
5
5
5
5
ns 2.0
4.5
6.0
Fig.9
Page 6
December 1990 6
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74HC/HCT573
DC CHARACTERISTICS FOR 74HCT
For the DC characteristics see
“74HC/HCT/HCU/HCMOS Logic Family Specifications”
.
Output capability: bus driver
ICC category: MSI
Note to HCT types
The value of additional quiescent supply current (∆I
CC
) for a unit load of 1 is given in the family specifications.
To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.
AC CHARACTERISTICS FOR 74HCT
GND = 0 V; t
r=tf
= 6 ns; CL= 50 pF
INPUT UNIT LOAD COEFFICIENT
D
n
LE
OE
0.35
0.65
1.25
SYMBOL PARAMETER
T
amb
(°C)
UNIT
TEST CONDITIONS
74HCT
V
CC
(V)
WAVEFORMS+25 −40 to +85 −40 to +125
min. typ. max. min. max. min. max.
t
PHL
/ t
PLH
propagation delay
Dn to Q
n
20 35 44 53 ns 4.5 Fig.6
t
PHL
/ t
PLH
propagation delay
LE to Q
n
18 35 44 53 ns 4.5 Fig.7
t
PZH
/ t
PZL
3-state output enable
time
OE to Q
n
17 30 38 45 ns 4.5 Fig.8
t
PHZ
/ t
PLZ
3-state output disable
time
OE to Q
n
18 30 38 45 ns 4.5 Fig.8
t
THL
/ t
TLH
output transition time 5 12 15 18 ns 4.5 Fig.6
t
W
enable pulse width
HIGH
16 5 20 24 ns 4.5 Fig.7
t
su
set-up time
Dn to LE
13 7 16 20 ns 4.5 Fig.9
t
h
hold time
Dn to LE
9 4 11 14 ns 4.5 Fig.9
Page 7
December 1990 7
Philips Semiconductors Product specification
Octal D-type transparent latch; 3-state 74HC/HCT573
AC WAVEFORMS
Fig.6 Waveforms showing the data input (Dn) to
output (Qn) propagation delays and the
output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Fig.7 Waveforms showing the latch enable input
(LE) pulse width, the latch enable input to
output (Qn) propagation delays and the
output transition times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
Fig.8 Waveforms showing the 3-state enable and
disable times.
(1) HC : VM= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
PACKAGE OUTLINES
See
“74HC/HCT/HCU/HCMOS Logic Package Outlines”
.
Fig.9 Waveforms showing the data set-up and
hold times for Dn input to LE input.
The shaded areas indicate when the input is permitted to
change for predictable output performance.
(1) HC : V
M
= 50%; VI= GND to VCC.
HCT: V
M
= 1.3 V; VI= GND to 3 V.
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