Datasheet 74 hct573 DATASHEETS (Philips)

INTEGRATED CIRCUITS

DATA SH EET

For a complete data sheet, please also download:

•The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Information

•The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines

74HC/HCT573

Octal D-type transparent latch;
3-state

Product specification
File under Integrated Circuits, IC06

December 1990

Philips Semiconductors Product specification

Octal D-type transparent latch; 3-state 74HC/HCT573

the D

FEATURES

• Inputs and outputs on opposite
sides of package allowing easy
interface with microprocessors

• Useful as input or output port for
microprocessors/microcomputers

• 3-state non-inverting outputs for
bus oriented applications

• Common 3-state output enable
input

• Functionally identical to the “563”
and “373”

• Output capability: bus driver

• ICC category: MSI

QUICK REFERENCE DATA

GND = 0 V; T

=25°C; tr=tf= 6 ns

amb

GENERAL DESCRIPTION

The 74HC/HCT573 are high-speed
Si-gate CMOS devices and are pin
compatible with low power Schottky
TTL (LSTTL). They are specified in
compliance with JEDEC standard no.
7A.

The 74HC/HCT573 are octal D-type
transparent latches featuring
separate D-type inputs for each latch
and 3-state outputs for bus oriented
applications.
A latch enable (LE) input and an
output enable (OE) input are common
to all latches.

The “573” consists of eight D-type
transparent latches with 3-state true
outputs. When LE is HIGH, data at

inputs enter the latches. In this

n

condition the latches are transparent,
i.e. a latch output will change state
each time its corresponding D-input
changes.

When LE is LOW the latches store the
information that was present at the
D-inputs a set-up time preceding the
HIGH-to-LOW transition of LE.
When OE is LOW, the contents of the
8 latches are available at the outputs.
When OE is HIGH, the outputs go to
the high impedance OFF-state.
Operation of the OE input does not
affect the state of the latches.

The “573” is functionally identical to
the “563” and “373”, but the “563” has
inverted outputs and the “373” has a
different pin arrangement.

SYMBOL PARAMETER CONDITIONS

TYPICAL

HC HCT

t

PHL/ tPLH

C

I

C

PD

propagation delay CL= 15 pF; VCC=5 V

D

to Q

n

LE to Q

n

n

14 17 ns

15 15 ns
input capacitance 3.5 3.5 pF
power dissipation capacitance per latch notes 1 and 2 26 26 pF

Notes

1. C

is used to determine the dynamic power dissipation (PD in µW):

PD

PD=CPD× V

2

× fi+∑ (CL× V

CC

2

× fo) where:

CC

fi= input frequency in MHz; fo= output frequency in MHz
∑ (CL× V

2

× fo) = sum of outputs

CC

CL= output load capacitance in pF; VCC= supply voltage in V

2. For HC the condition is VI= GND to VCC; for HCT the condition is VI= GND to VCC− 1.5 V

ORDERING INFORMATION

“74HC/HCT/HCU/HCMOS Logic Package Information”

See

.

UNIT

December 1990 2

Philips Semiconductors Product specification

Octal D-type transparent latch; 3-state 74HC/HCT573

PIN DESCRIPTION

PIN NO. SYMBOL NAME AND FUNCTION

2, 3, 4, 5, 6, 7, 8, 9 D
11 LE latch enable input (active HIGH)
1
10 GND ground (0 V)
19, 18, 17, 16, 15, 14, 13, 12 Q
20 V

to D

0

7

data inputs

OE 3-state output enable input (active LOW)

to Q

0
CC

7

3-state latch outputs
positive supply voltage

Fig.1 Pin configuration. Fig.2 Logic symbol. Fig.3 IEC logic symbol.

December 1990 3

Philips Semiconductors Product specification

Octal D-type transparent latch; 3-state 74HC/HCT573

FUNCTION TABLE

Fig.4 Functional diagram.

OPERATING

MODES

enable and read
register

INPUTS

OE LE D

LLH

H

INTERNAL
LATCHES

N

L
H

L

H

OUTPUTS

Q0to Q

(transparent mode)
latch and read

register
latch register and

disable outputs

L
L

HHL

L

l

L

h

l

L

h

L

H

L

H

Notes

1. H = HIGH voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW

LE transition
L = LOW voltage level
l = LOW voltage level one set-up time prior to the HIGH-to-LOW

LE transition

Z = high impedance OFF-state

7

L

H

L

H
Z

Z

Fig.5 Logic diagram.

December 1990 4

Philips Semiconductors Product specification

Octal D-type transparent latch; 3-state 74HC/HCT573

DC CHARACTERISTICS FOR 74HC

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

Output capability: bus driver
ICC category: MSI

AC CHARACTERISTICS FOR 74HC

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

SYMBOL PARAMETER

t

PHL

t

PHL

t

PZH

t

PHZ

t

THL

t

W

/ t

/ t

/ t

/ t

/ t

propagation delay

PLH

Dn to Q

propagation delay

PLH

LE to Q

3-state output enable

PZL

time OE to Q

3-state output disable

PLZ

time OE to Q

output transition time 14

TLH

n

n

n

n

enable pulse width

HIGH

t

su

set-up time

Dn to LE

t

h

hold time

Dn to LE

(°C)

T

amb

74HC

min. typ. max. min. max. min. max.

47

80
16
14

50
10
9

5
5
5

17
14

50
18
14

44
16
13

55
20
16

5
4

14
5
4

11
4
3

3
1
1

150
30
26

150
30
26

140
28
24

150
30
26

60
12
10

100
20
17

65
13
11

5
5
5

190
38
33

190
38
33

175
35
30

190
38
33

75
15
13

225
45
38

225
45
38

210
42
36

225
45
38

90
18
15

120
24
20

75
15
13

5
5
5

.

UNIT

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

ns 2.0

TEST CONDITIONS

V

CC

WAVEFORMS+25 −40 to +85 −40 to +125

(V)

Fig.6

4.5

6.0
Fig.7

4.5

6.0
Fig.8

4.5

6.0
Fig.8

4.5

6.0
Fig.6

4.5

6.0
Fig.7

4.5

6.0
Fig.9

4.5

6.0
Fig.9

4.5

6.0

December 1990 5

Philips Semiconductors Product specification

Octal D-type transparent latch; 3-state 74HC/HCT573

DC CHARACTERISTICS FOR 74HCT

For the DC characteristics see

“74HC/HCT/HCU/HCMOS Logic Family Specifications”

.

Output capability: bus driver
ICC category: MSI

Note to HCT types

The value of additional quiescent supply current (∆I

) for a unit load of 1 is given in the family specifications.

CC

To determine ∆ICC per input, multiply this value by the unit load coefficient shown in the table below.

INPUT UNIT LOAD COEFFICIENT

D
LE
OE

n

0.35

0.65

1.25

AC CHARACTERISTICS FOR 74HCT

GND = 0 V; t

= 6 ns; CL= 50 pF

r=tf

T

amb

(°C)

TEST CONDITIONS

74HCT

SYMBOL PARAMETER

UNIT

V

CC

(V)

min. typ. max. min. max. min. max.

t

PHL

t

PHL

t

PZH

/ t

/ t

/ t

propagation delay

PLH

Dn to Q

propagation delay

PLH

LE to Q

3-state output enable

PZL

20 35 44 53 ns 4.5 Fig.6

n

18 35 44 53 ns 4.5 Fig.7

n

17 30 38 45 ns 4.5 Fig.8

time

t

PHZ

OE to Q

/ t

3-state output disable

PLZ

n

18 30 38 45 ns 4.5 Fig.8

time

t

THL

OE to Q

/ t

output transition time 5 12 15 18 ns 4.5 Fig.6

TLH

n

WAVEFORMS+25 −40 to +85 −40 to +125

t

W

enable pulse width

16 5 20 24 ns 4.5 Fig.7

HIGH

t

su

set-up time

13 7 16 20 ns 4.5 Fig.9

Dn to LE

t

h

hold time

9 4 11 14 ns 4.5 Fig.9

Dn to LE

December 1990 6

Philips Semiconductors Product specification

Octal D-type transparent latch; 3-state 74HC/HCT573

AC WAVEFORMS

(1) HC : VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

M

Fig.6 Waveforms showing the data input (Dn) to

output (Qn) propagation delays and the
output transition times.

(1) HC : VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

M

Fig.7 Waveforms showing the latch enable input

(LE) pulse width, the latch enable input to
output (Qn) propagation delays and the
output transition times.

The shaded areas indicate when the input is permitted to
change for predictable output performance.

(1) HC : V

= 50%; VI= GND to VCC.

M

= 1.3 V; VI= GND to 3 V.

HCT: V

M

(1) HC : VM= 50%; VI= GND to VCC.

= 1.3 V; VI= GND to 3 V.

HCT: V

M

Fig.8 Waveforms showing the 3-state enable and

disable times.

December 1990 7

Fig.9 Waveforms showing the data set-up and

hold times for Dn input to LE input.

PACKAGE OUTLINES

See

“74HC/HCT/HCU/HCMOS Logic Package Outlines”

.